DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on February 16, 2024 and October 17, 2025 are being considered by the examiner.
Drawings
The drawings were received on September 30, 2022. These drawings are acceptable.
Claim Objections
Claim 13 is objected to because of the following informalities: the phrase “Mach-Zehner Interferometers, Micro Ring Resonsators, phase shifters, or combinations thereof” contain typographical errors and the examiner believes should instead read “Mach-Zehnder” and “Resonators”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-12, and 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Psaila et al. (US Patent 10,698,164, hereinafter referred to as “Psaila”). Psaila anticipates claims:
1. A semiconductor assembly (see figures 1-9) comprising:
an electronic integrated circuit die (the carrier / printed circuit board PCB 102 is interpreted as the electronic integrated circuit die, see figure 9);
a photonic integrated circuit die (the second substrate 24/124, see figures 1-9, is interpreted as the photonic integrated circuit die), coupled to the electronic integrated circuit die (see figure 9); and
a glass – layer (“GLASS” first substrate 22/122 is interpreted as the glass-layer, see figures 1-9) comprising one or more waveguides (waveguides 26/126, see figures 1-9 are interpreted as the one or more waveguides) configured to route one or more optical signals from the photonic integrated circuit die (see column 16, lines 16-45).
2. The semiconductor assembly of claim 1, further comprising a silicon phonic layer (silicon waveguide 28, see figure 3 and 9, is interpreted as the silicon photonic layer) between the photonic integrated circuit die and the glass layer (see figure 9).
3. The semiconductor assembly of claim 1, wherein the glass layer comprises a plurality of waveguides, at least two of the plurality of waveguides at different heights (see figure 9, there are two waveguides, and each are shown at different heights based on their location and curve).
4. The semiconductor assembly of claim 1, wherein the glass layer comprises an amorphous glass (see column 2, lines 9-18).
6. The semiconductor assembly of claim 1, wherein the glass layer is attached between the electronic integrated circuit die and the photonic integrated circuit die (see figure 9).
7. The semiconductor assembly of claim 1, wherein the glass layer is attached to the photonic integrated circuit die on a side opposite the electronic integrated circuit die (see figure 9, the glass layer is attached to the photonic integrated circuit on the top side, which is opposite to the bottom side the glass layer is attached to the electronic integrated circuit die).
8. The semiconductor assembly of claim 1, wherein the glass layer comprises two or more waveguides, each aligned at a different z-axis (see figure 9).
9. The semiconductor assembly of claim 1, wherein the glass layer comprises a substrate (see figure 9, the glass layer is a substrate).
10. The semiconductor assembly of claim I, wherein the glass layer further comprises a component (see figures 1-9, the glass layer is interpreted as a component).
11. The semiconductor assembly of claim 1, further comprising via (vias 170) including through glass via in the glass layer (see figure 9).
12. The semiconductor assembly of claim 11, wherein the through glass via are configured to allow connection from the electronic integrated circuit to power, input, output, or combinations thereof (see figure 9, the vias allow connection from anything).
14. A device (see figures 1-9) comprising:
a semiconductor assembly (see figures 1-9) comprising:
an electronic integrated circuit die (the carrier / printed circuit board PCB 102 is interpreted as the electronic integrated circuit die, see figure 9);
a photonic integrated circuit die (the second substrate 24/124, see figures 1-9, is interpreted as the photonic integrated circuit die) coupled to the electronic integrated circuit die (see figure 9); and
a glass layer (“GLASS” first substrate 22/122 is interpreted as the glass-layer, see figures 1-9) comprising one or more waveguides (waveguides 26/126, see figures 1-9 are interpreted as the one or more waveguides) configured to route one or more optical signals from the photonic integrated circuit die (see column 16, lines 16-45);
a housing (the cladding material 18 is interpreted as the housing as it houses a waveguide 54); and
a touchscreen (bonding material 32, see figure 7, is interpreted as touchscreen as it can be touched and screens the gap between waveguides 28 and 54).
15. The device of claim 14, wherein the glass layer comprises a plurality of waveguides (see figure 9).
16. The device of claim 15, wherein at least two of the plurality of waveguides are at different heights within the glass layer (see figure 9, the two waveguides are each at different heights in the glass layer because of their location and curvature).
17. A method of making a semiconductor assembly (see figures 1-9), the method comprising:
attaching a glass layer (“GLASS” first substrate 22/122 is interpreted as the glass-layer, see figures 1-9) to a photonic integrated circuit (the second substrate 24/124, see figures 1-9, is interpreted as the photonic integrated circuit);
making a plurality of waveguides (waveguides 26/126, see figures 1-9 are interpreted as the one or more waveguides) in the glass layer to produce a glass layer (see figure 9), at least two of the plurality of waveguides at different heights (see figure 9, the two waveguides are each at different heights in the glass layer because of their location and curvature); and
connecting the photonic integrated circuit and the glass layer to an electronic integrated circuit (the carrier / printed circuit board PCB 102 is interpreted as the electronic integrated circuit die, see figure 9).
18. The method of claim 17, wherein making a plurality of waveguides comprises laser direct writing (see column 12, lines 8-28, laser inscription of the waveguide is interpreted as laser direct writing).
19. The method of claim 17, wherein connecting the photonic integrated circuit comprises solder bumps (solder 176 is interpreted as the solder bumps).
20. The method of claim 17, further comprising connecting the photonic integrated circuit to one or more optical fibers (174, see figure 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Psaila, as applied to claim 1 as previously stated.
With respect to claim 5, Psaila discloses the limitations of claim 1 as previously stated. Psaila is silent to the glass layer comprising a partially crystalline glass. However, the examiner takes official notice that partially crystalline glass is a well-known material for use to create optical waveguides. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the glass layer in the device of Psaila as comprising a partially crystalline glass, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
With respect to claim 13, Psaila discloses the limitations of claim 1 as previously stated. Psaila is silent to the photonic integrated circuit comprises one or more Mach-Zehner Interferometers, Micro Ring Resonsators, phase shifters, or combinations thereof. However, the examiner takes official notice that Mach-Zehnder interferometers, micro-ring resonators, and phase shifters are known optical components for use in photonic integrated circuits and are used to beneficially allow functionality like optical modulation to allow the optical devices to be used in optical communication. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include one or more Mach-Zehnder Interferometers, Micro Ring Resonators, phase shifters, or combinations thereof into the device of Psaila, to allow for optical communication.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M BEDTELYON whose telephone number is (571)270-1290. The examiner can normally be reached 8:00am - 4:30pm.
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/John Bedtelyon/Primary Examiner, Art Unit 2874