DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Miscellaneous
The Applicant has cancelled claim 2 and added new claims 21; therefore, only claims 1 and 3-21 remain for this Office Action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 8-9, 11-15, 17-18 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nequist et al. (US 2018/0331072).
In regards to claim 1, Nequist discloses of a programmable logic device comprising: a first set of layers on a first side of a die formed using backside metallization on a back plane of the programmable logic device (for example see Fig 22 and Paragraphs 0123-0129), wherein the first set of layers is coupled to one or more bumps (see 2240) and comprises: first fabric routing circuitry (for example on 2210) to route first data within a programmable fabric of the programmable logic device (see Paragraphs 0123-0129); and clock routing circuitry (for example on 2210, 2205) to route clock signals within the programmable fabric (see Paragraphs 0124, 0126, 0129); and a second set of layers on a second side of the die that is opposite the first side (for example on 2205) comprises second fabric routing circuitry to route second data within the programmable fabric (for example see Fig 22 and Paragraphs 0123-0129), wherein the first set of layers (on 2210) are configured to route at least a portion of the first data between the second fabric routing circuitry and at least one bump of the one or more bumps (on 2240, see Fig 22 and Paragraphs 0123-0129).
In regards to claim 3, Nequist discloses of the programmable device of claim 2, comprising input/output circuitry and power delivery circuitry coupled to the bumps (2240, see Fig 22 and Paragraphs 0123, 0126, includes one or more input/output interface circuit(s)).
In regards to claim 4, Nequist discloses of the programmable logic device of claim 1, wherein the second fabric routing circuitry is coupled to the first fabric routing circuitry (see Fig 22 and Paragraphs 0123-0129).
In regards to claim 8, Nequist discloses of the programmable logic device of claim 1, comprising a plurality of transistors disposed between the first set of layers and the second set of layers (for example see Figs 22-23, 27 and Paragraphs 0041, 0124, 0131, 0134, transistors disposed between 2205, 2210 and/or 2405, 2410).
In regards to claim 9, Nequist discloses of the programmable logic device of claim 1, comprising a plurality of transistors of disposed within the first set of layers (for example see Figs 22-23, 27 and Paragraphs 0041, 0124, 0131, 0134, transistors disposed within 120, 2210, 2405, 2410).
In regards to claim 11, Nequist discloses of the programmable logic device of claim 1, wherein the second set of layers (2205) comprises power delivery circuitry to deliver power within the programmable fabric (for example see Fig 22 and Paragraphs 0124, 0126-0129, power signals are delivered to 2205 through bonded connections).
In regards to claim 12, Nequist discloses of a programmable logic device comprising: a first set of layers on a first side of a die formed using backside metallization on a back plane of the programmable logic device (for example on 2210, see Fig 22 and Paragraphs 0123-0129), wherein the first set of layers is coupled to a plurality of bumps and comprises: clock routing circuitry (for example on 2210, 2205) to route clock signals within a programmable fabric of the programmable logic device (see Paragraphs 0124, 0126, 0129); and power delivery circuitry (for example on 2210, 2205) to deliver power within the programmable fabric (see Paragraphs 0124, 0126-0129); and a second set of layers (on 2205) on a second side of the die that is opposite the first side of the programmable logic device (for example on 2205), wherein the second set of layers comprises fabric routing circuitry to route data within the programmable fabric (see Fig 22 and Paragraphs 0123-0129), wherein the first set of layers are configured to route at least a portion of the clock signals between the fabric routing circuitry and a subset of the plurality of bumps (on 2240, see Fig 22 and Paragraphs 0123-0129).
In regards to claim 13, Nequist discloses of the programmable logic device of claim 12, wherein the first set of layers (on 2210) are coupled to a plurality of input/output bumps and a plurality of power delivery bumps (see Fig 22 and Paragraphs 0123-0129, 2210 receives power, clock and/or data signals through the ball grid array 2240).
In regards to claim 14, Nequist discloses of the programmable logic device of claim 13, wherein the power delivery bumps (included in 2240) are coupled to the power delivery circuitry, wherein the power delivery circuitry delivers power within the programmable fabric through the first set of layers (see Paragraphs 0123-0129, power signals delivered through micro bump ball grid array 2240 to layers within 2205 and 2210).
In regards to claim 15, Nequist discloses of the programmable logic device of claim 13, comprising second fabric routing circuitry within the first set of layers coupled to the input/output bumps (within 2240) and to route second data within the programmable fabric (see Paragraphs 0123-0129, input/output data can be routed to 2205 and 2210 via the micro bump ball grid array 2240).
In regards to claim 17, Nequist discloses of a programmable logic device comprising: a first set of layers (on 2205) on a first side of a die comprising first fabric routing circuitry to route first data within a programmable fabric (for example on 2205, see Fig 22 and Paragraphs 0123-0129); a second set of layers (for example on 2210) on a second side of the die that is opposite of the first side, wherein the second set of layers is coupled to a plurality of bumps (see ball grid array 2240, micro bump array, see Paragraphs 0123, 0126) and comprising: second fabric routing circuitry to route second data within the programmable fabric (see Paragraphs 0123-0129); power delivery circuitry to route power within the programmable fabric (see Paragraphs 0124, 0126-0129); and clock routing circuitry to route clock signals within the programmable fabric (see Fig 2 and Paragraphs 0123-0129); and a plurality of transistors between the first set of layers and the second set of layers to at least partially implement a programmable fabric (for example see Figs 22-23, 27 and Paragraphs 0041, 0124, 0131, 0134, transistors disposed between 2205, 2210 and/or 2405, 2410).
In regards to claim 18, Nequist discloses of the programmable logic device of claim 17, comprising input/output circuitry coupled to a set of the plurality of bumps (see ball grid array 2240, micro bump array, see Paragraphs 0123, 0126) to transfer the second data to and from a device coupled to the programmable logic device (see Fig 22 and Paragraphs 0123-0129, includes one or more input/output interface circuit(s)).
In regards to claim 21, Nequist discloses of the programmable logic device of claim 1, wherein the first set of layers (of 2210) and the second set of layers (of 2205) are formed on opposite surfaces of a substrate of the die (see Fig 22), and wherein the one or more bumps are coupled only to the first set of layers (of 2210, see Fig 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nequist et al. (US 2018/0331072).
In regards to claims 5 and 7, Nequist discloses of the integrated circuit device of claim 1 as found within the explanation above, wherein the first fabric routing circuitry comprises first communication wires and the second fabric routing circuitry comprises second communication wires (see Paragraphs 0123-0129, data signals routed between 2205, 2210) wherein connections may be of various lengths (for example see Paragraph 0050).
However, Nequist does not explicitly disclose of wherein the first communication wires are longer than (claim 5) or the same as (claim 7) the second communication wires.
One having ordinary skill in the art would readily recognize that based on the location of the respective wires that different lengths may be required to connect the respective sections of the first and second fabric routing circuit. Furthermore, it has been held that a mere change in the size is generally recognized as an obvious matter of design choice being within the level of ordinary skill in the art (see In re Rose, 105 USPQ 237 (CCPA 1955)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the communications wires being different lengths for establishing the physical connections between elements of the integrated circuit device.
In regards to claim 6, Nequist discloses of the integrated circuit device of claim 5, wherein a density of the first communication wires is less than a density of the second communication wires (see teachings of In re Rose above, the density may largely be considered another obvious change in size).
In regards to claim 16, Nequist discloses of the integrated circuit device of claim 15 as found within the explanation above, wherein the first fabric routing circuitry comprises a segment length and the second fabric routing circuitry comprises a segment length; and where the segments may be of various lengths (for example see Paragraph 0050).
However, Nequist does not explicitly disclose of wherein a length of a segment in the second fabric routing circuitry is different than a length of a segment in the fabric routing circuitry.
One having ordinary skill in the art would readily recognize that based on the location of the respective wires that different lengths may be required to connect the respective sections of the first and second fabric routing circuit. Furthermore, it has been held that a mere change in the size is generally recognized as an obvious matter of design choice being within the level of ordinary skill in the art (see In re Rose, 105 USPQ 237 (CCPA 1955)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the communications wires being different lengths for establishing the physical connections between elements of the integrated circuit device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nequist et al. (US 2018/0331072) in view of Clark et al. (US 2018/0230049).
In regards to claim 19, Nequist discloses of the programmable logic device of claim 17 as found within the explanation above.
However, Nequist is silent and does not explicitly disclose of wherein routing of the first data, the second data, power, and clock signals in the programmable logic device are programmed using design software based on timing, wire usage, logic utilization in the programmable fabric, and/or a routability.
Clark discloses of a programmable logic device comprising: a first set of layers on a first side of a die comprising first fabric routing circuitry to route first data within a programmable fabric (for example see Fig 1); a second set of layers on a second side of the die that is opposite of the first side, wherein the second set of layers is coupled to a plurality of bumps (see microbumps 26 between 22, 24 and 38 between 24 and 32 in Fig 1) and comprising: second fabric routing circuitry to route second data within the programmable fabric; power delivery circuitry to route power within the programmable fabric (see Paragraphs 0038-0039, distribute power and routing clock and data signals); and clock routing circuitry to route clock signals within the programmable fabric (see Paragraphs 0038-0039, distribute power and routing clock and data signals); and a plurality of transistors to at least partially implement a programmable fabric (for example see Paragraph 0044), wherein routing of the first data, the second data, power, and clock signals in the programmable logic device are programmed using design software (see 14) based on timing, wire usage, logic utilization in the programmable fabric, and/or a routability (for example see Fig 1 and Paragraph 0033).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use design software to disclose a programmable logic device based on timing, wire usage, logic utilization and/or routability as taught by Clark as widely recognized tool utilized in the art for optimizing and creating designs of integrated circuitry.
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 10, the prior art does not disclose of the integrated circuit device of claim 1, wherein an operating voltage of the clocking routing circuitry is different than an operating voltage of the second fabric routing circuitry, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 20, the prior art does not disclose of the programmable logic device of claim 17, wherein an operational voltage of the clock routing circuitry is different than an operational voltage of the programmable fabric, nor would it have been obvious to one of ordinary skill in the art to do so.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3- have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or now added into the claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Clark et al. (US 2019/0103872)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844