DETAILED ACTION
Status of Claims
Claims 1 – 20 are pending.
Claims 1, 10, and 19 are independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 4 – 6, 8, 13 – 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 7, 9 – 12, 16, 17, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patil et al. (US Patent Application No. 2016/0065213 A1, hereinafter “Patil”).
As per claim 1, Patil teaches an integrated circuit comprising:
programmable logic circuitry [0007: logic cell in a programmable logic device] configurable to be processed combinationally [0007: the logic cell has the flexibility to support either a combinatorial or sequential function, or both, using minimal routing resources];
a main register configurable to receive an output of the programmable logic circuitry and configurable to receive a first clock signal [register of a first logic cell selected by multiplexer and may receive feedback signal, 0023, 0038];
and a first register that splits the programmable logic circuitry into a first portion and a second portion [register for second logic cell, in which multiple cell can be in a sequential configuration 0004: Programmable logic devices include a number of programmable logic blocks that are interconnected by a programmable routing network, sometimes referred to as a programmable interconnect. A logic block may be comprised of one or more logic cells, wherein a logic cell, in general, is made up of one of more logic elements with a defined number of inputs and outputs coupled to the routing network;0007: the logic cell has the flexibility to support either a combinatorial or sequential function, or both, using minimal routing resources; 0038], wherein the first register is configurable to receive a pulse of a second clock signal [TBS signal, 0023] and wherein the pulse is configurable to arrive at the first register at a time that reduces an amount of dynamic power consumed by the second portion of the programmable logic circuitry prior to arrival of the pulse at the first register [0007: A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells., 0038: the clock signal to the registers in each logic cell within the super logic cell may be independently gated based on the function of the logic cell in which resides, thereby reducing dynamic power consumption.].
As per 2, Patil teaches the integrated circuit of claim 1, wherein the first register is configurable to latch a first intermediate result of the first portion based on receiving the pulse of the second clock signal [“first” register output is selected, 0007, 0023].
As per claim 3, Patil teaches the integrated circuit of claim 1, comprising a second register that splits the programmable logic circuitry into a third portion and a fourth portion, wherein the second register is configurable to receive the first clock signal and to latch a second intermediate result of the third portion on a negative edge of the first clock signal, and wherein the fourth portion does not receive an input until the second intermediate result has been latched by the second register [0038: super logic cell has four logic cells, each can be gated independently].
As per claim 7, Patil teaches The integrated circuit of claim 1, wherein the logic circuitry comprises at least two lookup tables (LUTs), flip-flops, or both [0023: The logic cell 200 is illustrated as including two four-input Look-Up Tables (LUTs) 202 and 204, as well as three two-input multiplexors 206, 208, and 212,and a register 210. The number of LUTs, the number of inputs to the LUTs, as well as the number of inputs to the multiplexors may be altered, if desired.], and wherein a dynamic power consumption of the at least two LUTs is at least twice the dynamic power consumption of the flip-flops excluding the flip-flops associated with the first register [0026, 0038: multiple flip-flops per super cell].
As per claim 9, Patil teaches the integrated circuit of claim 1, wherein the main register is configurable to provide an input to the programmable logic circuitry [register used as input to another logic cell, 0007: register is selected as an output signal, 0023: As illustrated, the logic cell 200 includes combinatorial as well as sequential logic implemented within it. As can be seen in FIG. 3, the logic cell 200 receives a TBS input signal from a routing network 201, which can be any type of signal coming to logic cell 200 (e.g., as feedback) or from another logic cell, e.g., as the output of either a combinatorial or sequential function.].
As pe claim 10, Patil teaches a method comprising:
receiving a first clock signal via a main register, wherein the main register is configurable to receive an output of programmable logic circuitry [register of a first logic cell selected by multiplexer and may receive feedback signal, 0023, 0038];
receiving a first pulse of a second clock signal via a first register that splits the programmable logic circuitry into a first portion and a second portion, wherein the second portion consumes less dynamic power prior to the first register receiving the first pulse than the second portion would consume without the first register preceding it in a signal propagation path [register of the second logic cell is power gated, consuming less power 0007: A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells., 0038: the clock signal to the registers in each logic cell within the super logic cell may be independently gated based on the function of the logic cell in which resides, thereby reducing dynamic power consumption.];
and receiving a second pulse of the second clock signal via a second register in the signal propagation path [register of the second logic cell is selected, 0007, 0023: logic cells are in a sequential configuration, 0038].
As per claims 11, 12, 16 and 17, it is directed a method of steps to implement the on the apparatus set forth in claims 2,3,7 and 9. Patil teaches the claimed apparatus. Therefore, Patil teaches the method to implement the claims steps.
As per claims 19, it is directed a non-transitory computer readable medium to implement the method of steps as set forth in claims 10. Patil teaches the claimed method. Therefore, Patil teaches the computer readable medium to implement the claims steps.
As per claims 20, it is directed a non-transitory computer readable medium to implement on the apparatus as set forth in claims 9. Patil teaches the claimed apparatus. Therefore, Patil teaches the computer readable medium to implement the claims steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li; Haoran et al. (US Patent Application Publication No. 2023/0141475 A1) “Power Management Method, Multi-Processing Unit System And Power Management Module” is cited to teach a power management method, a multi-processing unit system, and a power management module thereof. The multi-processing unit system comprises a plurality of local power management units and a global power management unit, each of the local power management units corresponds to a processing unit of the multi-processing unit system. The power management method comprises: obtaining, using the global power management unit, a global power budget for the multi-processing unit system; allocating, using the global power management unit, local power budget for each of the local power management units according to the global power budget and power management parameters of the processing units; managing, using the local power management unit, local power resources of corresponding processing unit based on the allocated local power budget; reporting, using the local power management unit, the power management parameters of the processing unit to the global power management unit. The present disclosure improves the overall power efficiency for the multi-processing unit system.
Yoshihara; Toshio. (US Patent Application Publication No. 2013/0318384 A1) “Power Management Apparatus, Image Forming Apparatus And Power Management Method” is cited to teach a sleep mode in which power consumption is reduced to a prescribed value or smaller is achieved, while convenience for a user is maintained by shortening the time taken to recover from the sleep mode. The temperature of an LSI is measured or estimated when shifting to the sleep mode, and an apparatus enters a power supply shutoff sleep mode using power supply separation or a clock-gating sleep mode in accordance with the measured or estimated value of the temperature. In the case where power supply shutoff is selected, after entering the sleep mode, power supply is resumed and then the apparatus enters the clock-gating sleep mode in accordance with the measured temperature or the estimated temperature of the LSI.
Wang; Chung-Hsing et al. (US Patent Application Publication No. 2010/0259308 A1) “Clock Circuit And Method For Pulsed Latch Circuits” is cited to teach circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.
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/TERRELL S JOHNSON/ Primary Examiner, Art Unit 2176