DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election
Applicant’s election without traverse of invention I (claims 1-18) in the reply filed on 11/12/2025 is acknowledged. Claims 19-20 are withdrawn from consideration as being directed to a non-elected invention.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because they use reference number 122 to designate multiple elements. Initially figure 1 uses 122 to designate another sidewall of PIC 104 (note [0030]), but both figures 1 and 2 later use 122 to designate a mold material. It appears that a different reference number should be chosen to designate the mold material in both figures.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification Objections
The specification is objected to for the following issues:
[0030] uses 120 and 122 to designate sidewalls of PIC 104, but [0031] uses both 120 and 122 to designate a mold material. As mentioned above, it appears that a different reference number should be used to designate the mold material.
The specification does not identify element 145 which appears in figure 4.
[0043] mentions 176 which does not appear in the figures. It is possible that one instance of 174 in figure 4 should be changed to 176 (by analogy to figure 20).
Claim Objection (informality)
Claim 8 is objected to because of the following informalities:
Claim 8 is objected to because line 1 recites "adjoins" instead of "adjoining".
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 18 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 18 is indefinite because there is insufficient antecedent basis for "the optical waveguide" in line 12. It appears that "the optical waveguide" should be replaced with "the first optical interconnect".
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 10-11, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 5780875.
Claim 1: '875 discloses a device comprising (see mainly fig. 4B):
a substrate (stack of layers 13 / 14 / 15) comprising:
a first surface (top surface of 15);
a second surface (bottom surface of 13) opposite the first surface;
an optical waveguide 14 integral within the substrate; and
a hole (which exposes the upper surface of terrace 11) extending from the first surface to the second surface, the hole comprising a first sidewall (vertical wall which faces 20), wherein the optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end at the first sidewall; and
an integrated circuit (IC) die 2 (numbered in fig. 2A and in the description of fig. 4A) within the hole, the IC die comprising:
a second sidewall (left vertical wall which faces 14); and
an optical port (left end of 21) at the second sidewall, wherein the second sidewall is proximate to the first sidewall, and the first end of the optical waveguide is proximate to the optical port.
Claim 2: The IC die 2 further comprises: a first fiducial marker ("index pattern stamped on the semiconductor laser 2", col. 5 first full paragraph); a third surface (lower surface in fig. 4A); and a fourth surface (upper surface) opposite the third surface; wherein the second sidewall is orthogonal to the third surface, and the first fiducial marker is at the third surface.
Claim 10: The device further comprises a mold material 63 between the IC die and the substrate (fig. 6B variant).
Claim 11: The device further comprises a dielectric material layer 12 contacting the second surface of the substrate, wherein the dielectric material layer comprises an artifact of a grinding process or a polishing process ("the under cladding layer 12 is polished", col. 4 lns. 44-47).
Claim 14: The IC die 2 further comprises a laser (it is a semiconductor laser).
Claim 15: The first end of the optical waveguide 14 is aligned with the optical port; and the optical port is coupled with an optical source operable to transmit a signal (2 is a laser), or the optical port is coupled with an optical detector operable to a receive a signal.
Claims 1, 4, 7, 10, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2004/0001661 A1.
Claim 1: '661 discloses a device comprising (see mainly figs. 2 and 7A-7I):
a substrate 104 comprising:
a first surface (upper surface);
a second surface (lower surface) opposite the first surface;
an optical waveguide 105 integral within the substrate; and
a hole 115 extending from the first surface to the second surface, the hole comprising a first sidewall (vertical wall which faces 103), wherein the optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end (a right end) at the first sidewall; and
an integrated circuit (IC) die 103 within the hole, the IC die comprising:
a second sidewall (vertical wall which faces 105); and
an optical port at the second sidewall, wherein the second sidewall is proximate to the first sidewall, and the first end of the optical waveguide is proximate to the optical port ([0050]).
Claim 4: The substrate further comprises a recess at the first surface to receive another device 101, the recess comprising a third sidewall (vertical wall which faces 101), wherein the third sidewall comprises a second end (left end) of the optical waveguide 105.
Claim 7: The IC die 103 further comprises: a third surface (lower surface); a fourth surface (upper surface) opposite the third surface, wherein the second sidewall is orthogonal to the third surface; and a hardware interface comprising a plurality of electrically conductive contacts (which engage wiring patterns 121a, see e.g. figs. 7C-7D and [0072]) at the third surface.
Claim 10: The device further comprises a mold material 109 between the IC die and the substrate.
Claim 13: The device further comprises an index matching material 109 between the optical port and the substrate ("use of a light-transmitting resin material having a refractive index close to the refractive index of the core layer of the optical waveguide is preferable", [0055]).
Claim 14: The IC die 103 further comprises a laser ([0051]-[0052]).
Claim 15: The first end of the optical waveguide is aligned with the optical port; and the optical port is coupled with an optical source operable to transmit a signal (103 is a light emission device), or the optical port is coupled with an optical detector operable to a receive a signal.
Claims 1, 7, 9, and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6477286 B1.
Claim 1: '286 discloses a device comprising (see mainly fig. 3):
a substrate 2 comprising:
a first surface (upper surface);
a second surface (lower surface facing PCB 1) opposite the first surface;
an optical waveguide 4 integral within the substrate; and
a hole ("recess") extending from the first surface to the second surface, the hole comprising a first sidewall, wherein the optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end 12 at the first sidewall; and
an integrated circuit (IC) die 6 within the hole, the IC die comprising:
a second sidewall; and
an optical port 9 (or 8) at the second sidewall, wherein the second sidewall is proximate to the first sidewall, and the first end of the optical waveguide is proximate to the optical port (col. 6 last paragraph).
Claim 7: The IC die 6 further comprises: a third surface (lower surface); a fourth surface (upper surface) opposite the third surface, wherein the second sidewall is orthogonal to the third surface; and a hardware interface comprising a plurality of electrically conductive contacts 10 at the third surface.
Claim 9: The IC die 6 further comprises a thermally conductive layer 7, and wherein the fourth surface is an outside surface of the device.
Claim 14: The IC die 6 further comprises a laser (col. 5 lns. 51-55).
Claim 15: The first end 12 of the optical waveguide is aligned with the optical port; and the optical port is coupled with an optical source 9 operable to transmit a signal, or the optical port is coupled with an optical detector 8 operable to a receive a signal.
Claim 16: '286 discloses a system comprising (see mainly figs. 3 and 5):
an optical interposer comprising (see above with regard to claim 1):
a substrate 2 comprising a first surface; a second surface opposite the first surface; and a hole extending from the first surface to the second surface, the hole comprising a first sidewall;
a first optical interconnect 4 between the first surface and the second surface, and comprising a first end at the first sidewall; and
a photonic integrated circuit (PIC) 6 within the hole, the PIC comprising a second sidewall; and a first optical port at the second sidewall; wherein the second sidewall is proximate to the first sidewall, and the first end of the first optical interconnect is proximate to and aligned with the first optical port;
a logic integrated circuit (IC) device 32 (fig. 5); and
a memory IC device 39 (paragraph spanning cols. 7-8; note that motherboard 30 of fig. 5 can be constructed as the mixed optoelectronic substrate / board of fig. 3).
Claim 17: The substrate further comprises: a second optical interconnect (another waveguide 4) integral with the substrate and between the first surface and the second surface, the second optical interconnect comprising a second end at the first sidewall; wherein the PIC further comprises a second optical port 8 (or 9) at the second sidewall, and a second end of the second optical interconnect is proximate to and aligned with the second optical port; and wherein the first optical port is coupled with an optical source operable to transmit a signal, and the second optical port is coupled with an optical detector operable to a receive a signal (fig. 3).
Allowable Subject Matter
Claims 3, 5-6, 8, 12, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of their respective base claims and all applicable intervening claims (and for claims 8 and 18, if the rewriting avoids the respective informality objection and indefiniteness rejection above).
As to claim 3, US 5780875 is the only reference applied to ancestor claim 2. '875 mentions an "index pattern stamped on the upper surface of the silicon substrate" (col. 5 first full paragraph), but this is not part of the substrate as interpreted in the above rejection (i.e. the stack of layers 13 / 14 / 15). There is no apparent motivation or suggestion to relocate the index pattern (fiducial marker) to a surface of layer 13 or layer 15.
As to claim 5, the only reference applied to ancestor claim 4 is US 2004/0001661 A1. '661 does not disclose or suggest that the other device 101 includes all of the additional structures required by claim 5. Claim 6 depends from claim 5.
As to claim 8, the references applied to ancestor claim 7 do not disclose or suggest that their IC die includes a dielectric material adjoining their electrically conductive contacts, or further that the dielectric material is patterned to expose a first fiducial marker on the third surface of the IC die.
As to claim 12 there is no apparent motivation or suggestion for the substrates, as interpreted in the above rejections, to include a patterned glass.
As to claim 18, US 6477286 B1 is the only reference applied to base claim 16. '286 does not disclose or suggest another recess and a device within that recess which includes all the additional structures required by claim 18.
Conclusion
The additional references listed on the attached 892 form are considered generally relevant to the subject matter of this application. Several of them disclose other examples of devices having an optical waveguide interfaced with an IC die.
Contact Information
Examiner: 571-272-2360
Examiner's direct supervisor: 571-272-2397
Official correspondence by fax: 571-273-8300
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/Michael Stahl/Primary Examiner, Art Unit 2874