DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-13, 28 and 29 are rejected unde5r 35 U.S.C. 103 as being unpatentable over Muff et al. (US 9,251,116), hereinafter referred to as Muff in view of Choresh et al. (US 2022/0075685), hereinafter referred to as Choresh and Suresh et al. (US 11,270,051), hereinafter referred to as Suresh.
Referring to claim 1, Muff disclsoes, as claimed, an integrated circuit device comprising: first memory to store data (i.e.-integrated circuit device including memory, col. 3, lines 31-34 and col. 7, lines 10-16); data utilization circuitry to operate on the data (i.e.-an execution register of a processor block to execute data by the processor, col. 3, lines 62-64); compression and decompression circuitry disposed along the data distribution path between the first memory and the data utilization circuitry (i.e.-compression 244 and decompression 242, see fig. 6 and col. 3, lines 29-31) to enable the first memory to store the data in compressed form (i.e.-storing compressed data packets into the execution register, col. 3, lines 44-48 and 52-55) and to enable the data utilization circuitry to operate on the data in uncompressed form (i.e.- decompressed data are moved into execution register for execution, col. 3, lines 58-64).
However, Muff does not teach a configurable data distribution path to transfer data between the first memory and the data utilization circuitry, wherein the data distribution path comprises a first network-on-chip (NOC) on the integrated circuit device.
On the other hand, Choresh disclsoes data storage system for improving data throughput and decode capabilities using a configurable data distribution path (page 3, ¶29, lines 1-7) to transfer data between the first memory and the first NOC (page 3, ¶29, lines 10-12 and 17-22). Furthermore, Suresh discloses an integrated circuit comprised of a processing system and a Network-on-Chip (col. 5, lines 14-17), wherein the NoC is configured to establish data path connectivity between elements on the integrated circuit device (col. 8, lines 45-63).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Muff and incorporate a configurable data distribution path to transfer data between the first memory and the data utilization circuitry, as taught by Choresh. The motivation for doing so would have been to determine and configure the number of I/O data lines (i.e.-width) of a bus, thereby enhancing data transfer/transmission efficiency between a memory and a controller; and further to provide a user circuit design that is programmable and modifiable to establish connectivity between IC elements.
As to claim 2, the modified Muff in view of Suresh teaches the integrated circuit device of claim 1, wherein the first NOC is configurable to transmit the data from the first memory toward the data utilization circuitry (see Suresh, col. 4, lines 50-55).
As to claim 5, the modified Muff teaches the integrated circuit device of claim 1, wherein the data distribution path comprises a second network-on-chip (NOC) on the integrated circuit device of a different width than the first network-on-chip (NOC) (i.e.-NOC 26 or 28, see Muff, fig. 1 and see Choresh, page 3, ¶29, lines 17-28).
As to claim 6, the modified Muff innately teaches the integrated circuit device of claim 1, wherein the data distribution path comprises embedded memory coupled to the first network-on-chip (NOC), wherein the compression and decompression circuitry is disposed between the embedded memory and the first network-on-chip (NOC) (see Muff, col. 3, lines 28-39 and see fig. 6).
As to claim 7, the modified Muff teaches the integrated circuit device of claim 1, wherein the first network-on-chip (NOC) is formed from hardened circuitry (see Muff, col. 5, lines 32-33).
As to claim 8, the modified Muff teaches the integrated circuit device of claim 1, wherein the compression and decompression circuitry is formed in programmable logic circuitry of the integrated circuit device (see Muff, col. 5, lines 53-57 and col. 14, lines 58-59) and the first network-on-chip (NOC) comprises ingress and egress ports to the programmable logic circuitry to provide access to the compression and decompression circuitry (see Muff, col. 7, lines 4-7).
As to claim 9, the modified Muff innately teaches the integrated circuit device of claim 8, wherein the ingress and egress ports are substantially collocated with one another and with respect to the compression and decompression circuitry (see Muff, fig. 2 and col. 7, lines 2-8 and col. 12, lines 24-28).
As to claim 10, the modified Muff teaches the integrated circuit device of claim 1, wherein the compression and decompression circuitry is by passable (see Muff, col. 10, lines 43-48).
As to claim 11, the modified Muff in view of Choresh teaches the integrated circuit device of claim 1, wherein the data utilization circuitry comprises a digital signal processing circuit (see Muff, col. 4, lines 35-40 and/or see Choresh, page 2, ¶20, lines 5-7).
As to claim 12, the modified Muff in view of Choresh teaches the integrated circuit device of claim 1, wherein the data utilization circuitry comprises programmable logic circuitry configurable to be programmed with a user system design (see Muff, col. 5, lines 54-57 & col. 6, lines 10-17; and see Choresh, page 2, ¶20, lines 5-9).
As to claim 13, the modified Muff innately teaches the integrated circuit device of claim 1, wherein the integrated circuit device comprises a multi-die package (see Muff, fig. 2) and the first memory is disposed on a different die than the data utilization circuitry (see Muff, col. 7, lines 22-24 and col. 3, lines 36-39).
As to claim 28, the modified Muff teaches the integrated circuit device of claim 1, wherein the compression and decompression circuitry is configurable to selectively decompress the data traveling from the first memory toward the data utilization circuitry (see Muff, col. 17, lines 38-42 and 45-50).
As to claim 29, the modified Muff teaches the integrated circuit device of claim 28, wherein the compression and decompression circuitry is configurable to selectively compress the data traveling from the data utilization circuitry toward the first memory (see Muff, col. 18, lines 18-21 and 26-33).
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Muff, Choresh and Suresh, as applied to claim 1 above, and further in view of Park et al. (US 2019/0190538), hereinafter referred to as Park.
As to claims 14-17, the modified Muff teaches the claimed invention except the limitations of claims 14-17.
On the other hand, Park discloses systems and methods for data access operations by compressing and decompressing data using various schemes such as lossless encoding (i.e.-sparse, LUT based,…) and Huffman encoding (see page 4, ¶42, lines 7-10 and 15-17).
Therefore, before the effective filing date of the clamed invention, it would have been obvious to a person of ordinary skill in the art to further modify the teachings of Muff so that the compression and decompression circuitry uses: lossless sparse encoding, lossless multiprecision encoding, Huffman encoding and lossless prefix lookup table-based encoding, as taught by Park. The motivation for doing wo would have been to utilize reversible compression scheme/techniques since these schemes can allow original data to be completely reconstructed from compressed data.
As to claim 18, the modified Muff in view of Park innately teaches the integrated circuit device of claim 1, comprising second compression and decompression circuitry disposed along the data distribution path, wherein the compression and decompression circuitry uses a first form of encoding and the second compression and decompression circuitry uses a second form of encoding (see Park, page 5, ¶49).
Claims 19-24 are rejected under 35 U.S.C. 103 as being unpatentable over Muff in view of Suresh and Park.
Referring to claim 19, Muff disclsoes, as claimed, an integrated circuit system comprising: data utilization circuitry (i.e.-an execution register of a processor block, col. 3, lines 62-64) to operate on data in uncompressed form (i.e.-decompressed data are moved into execution register for execution, col. 3, lines 58-64); memory to store the data in compressed form (i.e.-input buffer storing compressed data, col. 1, lines 65-66); and decompression circuitry disposed between the memory and the NOC, the decompression circuitry to decompress the data (i.e.-decompression logic to decompress data, col. 1, lines 59-63).
However, Muff does not teach decompressing using lossless prefix lookup table-based encoding before the data reaches the data utilization circuitry; and a network-on-chip (NOC) to transmit the data from the memory toward the data utilization circuitry.
On the other hand, Park teaches systems and methods for data access operations by compressing and decompressing data using various schemes such as lossless encoding (i.e.-sparse, LUT based,…) and Huffman encoding (see page 4, ¶42, lines 7-10 and 15-17). Furthermore, Suresh teaches a network-on-chip (NOC) to transmit the data from the memory toward the data utilization circuitry. (col. 5, lines 14-17 and col. 8, lines 45-63).
Therefore, before the effective filing date of the clamed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Muff and use lossless prefix lookup table-based encoding before the data reaches the data utilization circuitry; and a network-on-chip (NOC) to transmit the data from the memory toward the data utilization circuitry, as taught by Park and Suresh. The motivation for doing so would have been to utilize reversible compression scheme/techniques since these schemes can allow original data to be completely reconstructed from compressed data; and further to provide a user circuit design that is programmable and modifiable to establish connectivity between IC elements.
As to claim 20, the modified Muff teaches the claimed invention except the limitation of claim 20. It would have been obvious to a person of ordinary skill the art at the effective filing date of the claimed invention to dispose the decompression circuitry in an interface of the memory, since it has been held that rearranging of parts of an invention involves only routine skill in the art, In re Japikse, 86 USPQ 70.
As to claim 21, the modified Muff teaches the claimed invention except the limitation of claim 21. It would have been obvious to a person of ordinary skill the art at the effective filing date of the claimed invention to further modify so that the data utilization circuitry is disposed on a first die; the memory is disposed on a second die; and the decompression circuitry is disposed on the second die, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. V. Bemis Co., 193 USPQ 8.
As to claim 22, the modified Muff in view of Park teaches the system of claim 19, comprising compression circuitry to compress data to be stored in the memory using lossless prefix lookup table-based encoding (see Park, page 4, ¶42, lines 7-10 and 15-17).
As to claim 23, the modified Muff in view of Park teaches the system of claim 19, wherein the data utilization circuitry comprises a plurality of embedded function circuits and wherein the decompression circuitry is connected between two of the plurality of embedded function circuits (see Park, fig. 5 and page 4, ¶47).
Referring to claim 24, the claim is substantially the same as claim 19, hence the rejection of claim 19 is applied accordingly.
Examiner’s note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Claim Objections
Claims 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed ON 07/24/2026 have been fully considered but they are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184
