Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 02/04/2026 have been fully considered. The rejection has been reinterpreted based on the arguments. See the rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-22 are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (Pub NO. US 2023/0077784 A1; hereinafter Weng) in view of Stark et al. (Pub NO. US 2003/0006796 A1; hereinafter Stark).
Regarding Claim 1, Weng teaches an apparatus (apparatus in Fig. 3-Fig. 4 and Fig. below) comprising:
an interposer interface (See interposer interface 410 in fig. 4 and Fig. below) coupled between a first component and a second component (See Fig. 4 and Fig. below) to allow a probe (allow probe 425 in fig. 4 and Fig. below; See [0050]) to capture one or more waveforms to be exchanged between the first component and the second component (425 captures waveforms from 410 between two components in Fig. 4 and Fig. below; See [0050]); and
a resistive network splitter (See plurality of resistors 415 in fig. 4 and Fig., below; See [0050]) to couple the interposer interface to the probe (resistive network splitter 325 to couple 315 to 340 in Fig. 4 and Fig. below),
wherein the resistive network comprises a plurality of resistors (415 comprises plurality of resistors in Fig. 4 and Fig. below; See [0050]).
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Weng teaches resistive network splitter to couple the interposer interface to the probe (resistive network splitter 325 to couple 315 to 340 in Fig. 4),
However, Weng is silent about resistive network splitter to couple the interposer interface to the probe and the second component; wherein the plurality of resistors is to reduce signal reflection.
Stark teaches resistive network splitter to couple the interposer interface to the probe and the second component (resistive network splitter 313 to couple the interposer interface Z0 to the probe 304 and the second component 106 in Fig. 5; See [0023]-[0025], [0032]); wherein the plurality of resistors (See plurality of resistors R1, R2 and R3 in Fig. 5) is to reduce signal reflection (See [0026]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Weng by using resistive network splitter to couple the interposer interface to the probe and the second component; the plurality of resistors is to reduce signal reflection, as taught by Stark in order to achieve matched impedance by the resistor network such that reflections are not sent back along the transmission line (Stark; [0026]).
Regarding Claim 2, Weng in view of Stark teaches the apparatus of claim 1. Stark further teaches wherein a value of each of the plurality of resistors is to be determined based at least in part on input and/or output transmission line impedances for the resistive network (See [0029]-[0030]).
Regarding Claim 3, Weng in view of Stark teaches the apparatus of claim 1. Stark further teaches wherein the value of each of the plurality of resistors is to be determined as a function of input and out transmission line impedances to reduce signal reflections (See [0026]-[0031]).
Regarding Claim 4, Weng in view of Stark teaches the apparatus of claim 1. Stark further teaches regarding transmission path probe (See Fig. 5; Se [0022]-[0023]) wherein the plurality of resistors comprises three resistors to form a three-way resistor split (See three resistors R1, R2 and R3 in Fig. 5; See [0022]-[0023]), wherein the value of each of the three resistors is to be determined to match an equivalent resistance of a split path looking toward and into the three-way resistor split (impedance match is equivalent resistance match; See [0026]-[0029], [0031]).
Regarding Claim 5, Weng in view of Stark teaches the apparatus of claim 1. Stark further teaches regarding transmission path probe (See Fig. 5; Se [0022]-[0023]) wherein the plurality of resistors comprises a first resistor, a second resistor and a third resistor (See three resistors R1, R2 and R3 in Fig. 5; See [0022]-[0023]), wherein: the first resistor is to couple a resistive network junction to the first component (See Fig. 5 and Fig. below), the second resistor is to couple the resistive network junction to the second component (See Fig. 5 and Fig. below), and the third resistor is to couple the resistive network junction to the probe (See Fig. 5 and Fig. below).
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Regarding Claim 6, Weng in view of Stark teaches the apparatus of claim 5. Weng further teaches wherein the interposer interface is to couple the first component to a first end of the first resistor, wherein a second end of the first resistor is to couple to the resistive network junction (See Fig. 4 and Fig. below).
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Regarding Claim 7, Weng in view of Stark teaches the apparatus of claim 1. Weng further teaches wherein one or more of the plurality of resistors comprise a surface mount resistor or an embedded resistor (all resistors in fig. 4 are surface mounted resistors on surface of substrate; See [0051]).
Regarding Claim 8, Weng in view of Stark teaches the apparatus of claim 1. Weng further teaches wherein the first component comprises a processor having one or more processor cores (See first component 360 have processor 305 in fig. 3; See [0032]-[0035]).
Regarding Claim 9, Weng in view of Stark teaches the apparatus of claim 1. Weng further teaches wherein the second component comprises a storage device (Se the second component has memory 310 in Fig. 3; See [0045]-[0046]).
Regarding Claim 10, Weng in view of Stark teaches the apparatus of claim 9. Weng further teaches wherein the storage device comprises a dynamic random access memory device (See [0004]).
Regarding Claim 11, Weng in view of Stark teaches the apparatus of claim 9. Weng further teaches wherein the storage device comprises a Double Data Rate (DDR) random access memory device (See [0026]).
Regarding Claim 12, Weng in view of Stark teaches the apparatus of claim 11. Weng further teaches wherein the DDR device comprises one of: a DDR2 device (two modulation DDR is DDR2; See [0026]), a DDR3 device, a DDR4 device, a DDR5 device, or a DDR6 device.
Regarding Claim 13, Weng teaches a system (system in Fig. 3-Fig. 4 and Fig. below) comprising:
a processor coupled to a storage device (processor 305 is coupled to storage device 310 in Fig. 3 and Fig. below);
an interposer interface (See interposer interface 315 in fig. 4 and Fig. below) coupled between the processor and the storage device (315 is coupled between 305 and 310 in Fig. 3 and Fig. below) to allow a probe to capture one or more waveforms to be exchanged between the processor and the storage device (See [0050]); and
a resistive network splitter (resistive network splitter 325 in fig. 3 and Fig., below; See [0050]) to couple the interposer interface to the probe (resistive network splitter 325 to couple 315 to 340 in Fig. 4), wherein the resistive network comprises a plurality of resistors (resistive network 325 in Fig. 3 has plurality of resistors 415 in Fig. 4),
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Weng teaches resistive network splitter to couple the interposer interface to the probe (resistive network splitter 325 to couple 315 to 340 in Fig. 4),
However, Weng is silent about resistive network splitter to couple the interposer interface to the probe and the storage device; wherein the plurality of resistors is to reduce signal reflection.
Stark teaches resistive network splitter to couple the interposer interface to the probe and the storage device (resistive network splitter 313 to couple the interposer interface Z0 to the probe 304 and the storage device 106 in Fig. 5; See [0023]-[0025], [0032]); wherein the plurality of resistors (See plurality of resistors R1, R2 and R3 in Fig. 5) is to reduce signal reflection (See [0026]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Weng by using resistive network splitter to couple the interposer interface to the probe and the storage device; the plurality of resistors is to reduce signal reflection, as taught by Stark in order to achieve matched impedance by the resistor network such that reflections are not sent back along the transmission line (Stark; [0026]).
Regarding Claim 14, Weng in view of Stark teaches the system of claim 13. Stark further teaches wherein a value of each of the plurality of resistors is to be determined based at least in part on input and/or output transmission line impedances for the resistive network (See [0029]-[0030]).
Regarding Claim 15, Weng in view of Stark teaches the system of claim 13. Stark further teaches wherein the value of each of the plurality of resistors is to be determined as a function of input and out transmission line impedances to reduce signal reflections (See [0026]-[0031]).
Regarding Claim 16, Weng in view of Stark teaches the system of claim 13. Stark further teaches wherein the plurality of resistors comprises three resistors to form a three-way resistor split (See three resistors R1, R2 and R3 in Fig. 5; See [0022]-[0023]), wherein the value of each of the three resistors is to be determined to match an equivalent resistance of a split path looking toward and into the three-way resistor split (impedance match is equivalent resistance match; See [0026]-[0029], [0031]).
Regarding Claim 17, Weng in view of Stark teaches the system of claim 13. Stark further teaches wherein the plurality of resistors comprises a first resistor, a second resistor and a third resistor (See three resistors R1, R2 and R3 in Fig. 5; See [0022]-[0023]), wherein: the first resistor is to couple a resistive network junction to the processor (See Fig. 5 and Fig. below), the second resistor is to couple the resistive network junction to the storage device (See Fig. 5 and Fig. below), and the third resistor is to couple the resistive network junction to the probe (See Fig. 5 and Fig. below).
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Regarding Claim 18, Weng in view of Stark teaches the system of claim 17. Weng further teaches wherein the interposer interface is to couple the processor to a first end of the first resistor, wherein a second end of the first resistor is to couple to the resistive network junction (See Fig. 4 and Fig. below).
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Regarding Claim 19, Weng in view of Stark teaches the system of claim 13. Weng further teaches wherein one or more of the plurality of resistors comprise a surface mount resistor or an embedded resistor (all resistors in fig. 4 are surface mounted resistors on surface of substrate; See [0051]).
Regarding Claim 20, Weng in view of Stark teaches the system of claim 13. Weng further teaches wherein the processor comprises one or more processor cores (See first component 360 have processor 305 in fig. 3; See [0032]-[0035]).
Regarding Claim 21, Weng in view of Stark teaches the system of claim 13. Weng further teaches wherein the storage device comprises a dynamic random access memory device (See [0004]).
Regarding Claim 22, Weng in view of Stark teaches the system of claim 13. Weng further teaches wherein the storage device comprises a Double Data Rate (DDR) random access memory device (See [0026]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bock et al. (Patent NO. US 10,180,486 B2) discloses Test Standard Impedance Calibration.
Crippa et al. (Patent NO. US 12,032,003 B2) discloses Probe Head for Electronic Devices.
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858