Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-20, is/are rejected under 35 U.S.C. 103 as being unpatentable over Alexander et al., (US 11,567,768).
It has been noted that, a claimed invention is unpatentable if the differences between it and the prior art are "such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art." 35 U.S.C. § 103(a) (2000); KSRInt'lr. Teleflex Inc., 127 S.Ct. 1727, 1734 (2007); Graham v.John Deere Co., 383 U.S. 1, 13-14 (1966).
In Graham, the Court held that that the obviousness analysis is bottomed on several basic factual inquiries: "[(1)] the scope and content of the prior art are to be determined; [(2)] differences between the prior art and the claims at issue are to be ascertained; and [(3)] the level of ordinary skill in the pertinent art resolved." 383 U.S. at 17. See also KSR, 127 S.Ct. at 1734. "The combination of familiar elements according to known methods is likely to be obvious when it does no more; than yield predictable results." KSR, at 1739.
"When a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or in a different one. If a person of ordinary skill in the art can implement a predictable variation, § 103 likely bars its patentability." Id. at 1740.
"For the same reason, if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill." Id.
"Under the correct analysis, any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the elements in the manner claimed." Id. 11742.
As per claim 1, Alexander teaches a graphics processor “… as graphics processing units (GPUs) and digital signal processors (DSPs), col. 1, lines 23-25, Fig. 4) comprising: a cache memory (part of repeat cache, 31 Fig.7); and a graphics core (Alexander teaches implementing GPU/DSP therein obviously including an execution architecture type core to be included in a GPU/DSP according to embodiment coupled with the cache memory), the graphics core including execution resources to execute an instruction via a plurality of hardware threads and memory access circuitry to facilitate access to memory by the plurality of hardware threads (Alexander teaches a processor having an execution unit configured to run a plurality of threads, in an instruction cache for caching portions of machine code in a multi-threaded processor, col. 2 lines 43-51), the graphics core configured to: process a plurality of load requests from the plurality of hardware threads (running a first one of the threads including a first instance of a repeat instruction, col. 2, lines 51-60); detect duplicate load requests within the plurality of load requests (“…instructions defined in the instruction set include a repeat instruction which takes a repeat count operand, the execution unit being configured so as: a) when the repeat cache is not currently claimed according to said state and an instance of the repeat instruction is executed in a first thread of said threads, to cache a portion of code from the first thread into the repeat cache, to modify said state to record the repeat cache as claimed, and to execute said portion of code a respective number of times, taking each successive repetition from the repeat cache, and b) when the repeat cache is currently claimed according to said state and another instance of the repeat instruction is then executed as part of any further threads of said threads before the state is next reset to record the repeat cache as unclaimed again, to execute the portion of code as already cached in the repeat cache a respective number of times, each time from the repeat cache,” col. 2, lines 51-67) perform a single read from the cache memory in response to the duplicate load requests; and transmit data associated with the duplicate load requests to requesting hardware threads. (“…not only can the first thread re-use its own code multiple times based on the repeat cache, but also further threads can re-use the same code already cached by the first thread without having to separately fetch that same code from memory, col. 3, lines 7-15, 49-61).
Therein, Alexander teaches that the threads are concurrently being processed by the system, wherein repeat cache runs a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Alexander teaches loading of “duplicate” load requests because he repeated code results in a context switch each time (since it is doing a memory read). The benefit of allowing at least one other thread to execute before resuming would allow the system to discard the contents in the repeat cache.
As per claim 2, Alexander does not expressly teach the use of having the cache memory as a level one (L1) cache memory; however, in Alexander it would have been obvious to one of ordinary skill because L1 is the smallest and fastest memory directly on a CPU therein offering extremely low latency therein further benefiting instruction cache for caching portions of machine code.
As per claim 3, Alexander teaches wherein the cache memory includes or is associated with a shared local memory (SLM), the SLM accessible by the plurality of hardware threads. (“… processing unit 10 is connected to a shared instruction memory 12 common to the plurality of threads, and a shared data memory 22 that is again common to the plurality of threads,” col. 6, lines 48-65)
As per claim 4, Alexander teaches the graphics processor configured to: select a load request from the plurality of load requests from a first hardware thread of the plurality of hardware threads; process the load request received from the first hardware thread via the memory access circuitry; and return data associated with the load request from the first hardware thread according to a broadcast mask. (Alexander teaches a load to repeat cache might trigger a "broadcast" to other cores caches to update or invalidate their copies because Alexander in step (b) it is disclosed that “.when the repeat cache is currently claimed according to said state and another instance of the repeat instruction is then executed as part of any further threads of said threads before the state is next reset to record the repeat cache as unclaimed again, to execute the portion of code as already cached in the repeat cache a respective number of times, each time from the repeat cache,” col. 2, lines 51-67)
As per claim 5, Alexander teaches the graphics processor configured to prevent transmission (“… in response to the opcode of the repeat instruction: determining that a repeat cache of the processor is not claimed,” col. 2, lines 48-60, Alexander teaches determined if thread is currently claimed or not claimed and ‘prevent’ instruction sets based on that determination) of load requests of the plurality of load requests from the plurality of hardware threads based on a broadcast mask to prevent receipt of those load requests at the memory access circuitry.
As per claim 6, Alexander teaches the graphics processor configured to: receive data at the first hardware thread; and transmit data to a second hardware thread according to the broadcast mask. (Alexander teaches a load to repeat cache might trigger a "broadcast" to other cores caches to update or invalidate their copies because Alexander in step (b), see the explanation in claim 4)
As per claim 7, Alexander teaches wherein the execution resources of the graphics processor include a plurality of processing resources and the plurality of hardware threads are distributed across the plurality of processing resources. ( “A particular example of this can occur in a convolutional neural network where many nodes in fact comprise the same weights but with different connections. Consider for example a scenario where each thread is configured to perform the processing of a different respective node in the neural network, such as convolving a common kernel of weights with respective input data to detect a certain feature. In such scenarios, it would be advantageous to provide a mechanism allowing a given arithmetic instruction to operate on a combination of one or more common weight operands shared between threads and one or more operands specific to the individual respective thread. The issue is by no means specific to neural networks and could arise in any application that ends up using some shared operand values and some thread-specific operands, col. 4, lines 56-59)
As per claim 8, Alexander teaches wherein a first processing resource includes the first hardware thread, a second processing resource includes the second hardware thread, and an interconnect fabric couples the first hardware thread with the second hardware thread. (Alexander teaches that the threads are concurrently being processed by the system, wherein repeat cache runs a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots, col. 4, lines 43-col. 5, lines 1-9)
As per claim 9, Alexander teaches wherein the first processing resource includes a third hardware thread and the third hardware thread is configured to access data received at the first hardware thread via an inter-thread interconnect. (Alexander teaches “…processor may be divided into an array of tiles, each comprising its own execution unit and memory for use by that execution unit, thus implementing an array of parallel processing modules on the same chip or even spread across multiple chips. A processor may even combine this arrangement with the concurrent approach, i.e. so as to comprise an array of multiple tiles where each tile is configured to run multiple concurrent threads,” col. 2, lines 16-27).
As per claim 10, Alexander discloses initializing a type of barrier; receive, via the memory access circuitry, a plurality of load requests associated with a barrier identifier of the named barrier; merge load requests of the plurality of load requests (Alexander discloses “…it may be desired for multiple different threads to run the same code, but operating on different data. Again an example can occur in a machine learning application,” col. 4, lines 1-60) associated with the barrier identifier of the named barrier; and process merged load requests upon arrival of all threads participating in the named barrier. Further, Alexander’s execution unit is a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots. Further, optionally a supervisor thread may have other “overseer” or coordinating responsibilities, such as performing external exchanges or barrier synchronizations. Note Alexander’s illustrated case of J=4 is just one example implementation for illustrative purposes. E.g. in another implementation J=6 (six time slots, six worker contexts and one supervisor context). Therein, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Alexander teaches allowing at least one other thread to execute before resuming. And, when it resumes, it will be able to continue from the repeat cache because the contents are locked and the other threads will not have been allowed to discard the contents in the repeat cache.
Regarding claim 11, see the rejection for claim 1 in combination with claim 10 specifically, the as performing external exchanges or barrier synchronizations. Alexander does not expressly use the term “barrier” but does teach a type of “barrier” because Alexander’s execution unit is a barrel-threaded execution unit configured to run a plurality of concurrent threads each in a different respective one of a repeating sequence of interleaved time slots. Therein, optionally a supervisor thread may have other “overseer” or coordinating responsibilities, such as performing external exchanges or barrier synchronizations. See the rejection for claim 10 above.
As per claims 12-20, see the rejections for claims 1-11 above.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). 3. The following references Mukherjee (US 6,823,473) teaches a method for simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. (Abstract)
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/Primary Examiner, Art Unit 2184 December 27, 2025