DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/8/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" “embed” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently disclose a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “to make something an integral part of” respectively. Further note the limitation “contact/attach” is being interpreted to include "direct contact/attached" (no intermediate materials, elements or space disposed there between) and "indirect contact/attached" (intermediate materials, elements or space disposed there between).
Claim(s) 1, 2, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kawakita et al (US 2015/0084080 A1 hereinafter Kawakita) in view of Kawakita et al Fig 9 (US 2015/0084080 A1 hereinafter Kawakita9).
Regarding Claim 1, Kawakita discloses in Fig 10: A semiconductor assembly comprising:
a glass core (10A),
a semiconductor die (80) attached to the glass core;
a layer (50) extending between and connected to the first via and the second via, the layer comprising zinc and at least one of bismuth, antimony, cobalt, manganese, nickel, and chromium
and wherein the layer is embedded in the glass core and electrically coupled to the semiconductor die [0075, 0078, 0098]
Kawakita does not disclose: a first via extending at least partially through the substrate; a second via extending at least partially through the glass core; a layer extending between and connected to the first via and the second via
However, Kawakita9 in a different embodiment teaches in Fig 9: a first via (97 on left) extending at least partially through the substrate (10); a second via (97 on right) extending at least partially through the substrate (10); a layer (50) extending between and connected to the first via and the second via [0097].
References Kawakita and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita with the specified features of Kawakita9 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita and Kawakita9 so that a first via extending at least partially through the substrate; a second via extending at least partially through the glass core; a layer extending between and connected to the first via and the second via as taught by Kawakita9 in Kawakita’s device since, having vias in the substrate provides for electrical connection.
Regarding Claim 2, Kawakita and Kawakita9 disclose: The semiconductor assembly of claim 1, Kawakita discloses in Fig 10: wherein a surface of the layer (50) lies flush with a surface of the glass core (50) See Fig 10.
Regarding Claim 6, Kawakita and Kawakita9 disclose: The semiconductor assembly of claim 1, Kawakita discloses in Fig 10: wherein the layer (50) comprises a horizontal varistor [0097].
Claim(s) 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kawakita et al (US 2015/0084080 A1 hereinafter Kawakita) in view of Kawakita et al Fig 9 (US 2015/0084080 A1 hereinafter Kawakita9) and further in view of Li et al (US 2006/0067021A1 hereinafter Li).
Regarding Claim 7, Kawakita discloses in Fig 9 and 10: The semiconductor assembly of claim 1.
Kawakita does not disclose: wherein the first via comprises a ground via.
However, Li in a similar device teaches in Fig 2: the varistor (104A) is connected between a power terminal (106) and ground (C ) [0023]
References Kawakita, Li and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita and Kawakita9 with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Li and Kawakita9 so that wherein the first via comprises a ground via as taught by Li in Kawakita’s device since, this provides an improved over-voltage and over-current protection circuit.
Regarding Claim 8, Kawakita discloses in Fig 9 and 10: The semiconductor assembly of claim 1.
Kawakkita does not disclose: wherein the second via comprises a power via.
However, Li in a similar device teaches in Fig 2: the varistor (104A) is connected between a power terminal (106) and ground (C ) [0023]
References Kawakita, Li and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita and Kawakita9 with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Li and Kawakita9 so that wherein the second via comprises a power via as taught by Li in Kawakita’s device since, this provides an improved over-voltage and over-current protection circuit.
Regarding Claim 9, Kawakita discloses in Fig 10: A semiconductor substrate comprising:
a glass core (10A) having a first via and a second via extending therethrough;
a layer (50) embedded in the glass core,
the layer comprising zinc and at least one of bismuth, antimony, cobalt, manganese, nickel, and chromium, wherein the layer is electrically connected through the first via and the second via [0075, 0078,0097,0098].
Kawakita does not disclose: the layer extending between the first via and the second via, wherein the first via comprises a ground via and the second via comprises a power via.
However, Kawakita9 in a different embodiment teaches in Fig 9: a first via (97 on left) extending at least partially through the substrate (10); a second via (97 on right) extending at least partially through the substrate (10); a layer (50) extending between and connected to the first via and the second via [0097]
References Kawakita and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita with the specified features of Kawakita9 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita and Kawakita9 so that a first via extending at least partially through the substrate; a second via extending at least partially through the glass core; a layer extending between and connected to the first via and the second via as taught by Kawakita9 in Kawakita’s device since, having vias in the substrate provides for electrical connection.
However, Li in a similar device teaches in Fig 2: the varistor (104A) is connected between a power terminal (106) and ground (C ) [0023]
References Kawakita, Li and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita and Kawakita9 with the specified features of Li because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Li and Kawakita9 so that wherein the first via comprises a ground via and the second via comprises a power via as taught by Li in Kawakita’s and Kawakita9’s device since, this provides an improved over-voltage and over-current protection circuit.
Regarding Claim 10, Kawakita, Kawakita9, Li disclose: The semiconductor substrate of claim 9, Kawakita discloses in Fig 10: wherein the layer (50) comprises a horizontal varistor [0098].
Regarding Claim 11, Kawakita, Kawakita9, Li disclose: The semiconductor substrate of claim 9, Kawakita discloses in Fig 10: wherein a surface of the layer (50) lies flush with a surface of the glass core (10a) (See Fig 10).
Regarding Claim 12, Kawakita, Kawakita9, Li disclose: The semiconductor substrate of claim 9, Kawakita discloses in Fig 10: wherein a surface of the layer extends past a surface of the glass core (See Fig 10, left and right side where the surface of layer extends past the side surface of glass core).
Claim(s) 21-23, 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kawakita et al (US 2015/0084080 A1 hereinafter Kawakita) in view of Feichtinger et al (US 10,014,459 B2 hereinafter Feichtinger).
Regarding Claim 21, Kawakita discloses in Fig 10: A device comprising:
a substrate comprising:
a glass layer (10A);
a first conductive contact (60);
a second conductive contact (60);
a circuit component (50) at least partially embedded in the glass layer and connected
between the first conductive contact and the second conductive contact (See Fig 10);
Kawakita does not disclose; and a build-up layer on the glass layer.
However, Feichtinger in a similar device teaches in Fig 3: further comprising a build-up layer (15) between the substrate (2) and the semiconductor die (3).
References Kawakita, Feichtinger and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita with the specified features of Feichtinger because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Feichtinger and Kawakita9 so that a build-up layer between the glass core and the semiconductor die as taught by Kawakita9 in Kawakita’s device since, this provides for an improved thermal performance (Col 1 lines 29-35).
Regarding Claim 22, Kawakita and Feichtinger disclose: The device of claim 21, Kawakita discloses in Fig 10: wherein a surface of the circuit component (50) lies flush with a surface of the glass layer (10A).
Regarding Claim 23, Kawakita and Feichtinger disclose: The device of claim 21, Kawakita discloses in Fig 10: wherein a surface of the circuit component (50) extends past a surface of the glass layer (side surface of 10A).
Regarding Claim 26, Kawakita and Feichtinger disclose: The device of claim 21, Kawakita discloses in Fig 10: wherein the circuit component comprises a layer comprising zinc and at least one of bismuth, antimony, cobalt, manganese, nickel, and chromium [0078]
Regarding Claim 27, Kawakita and Feichtinger disclose: The device of claim 21, Kawakita discloses in Fig 10: wherein the circuit component is a varistor [0078].
Regarding Claim 28, Kawakita and Feichtinger disclose: The device of claim 21, Kawakita discloses in Fig 10: further comprising a semiconductor die (80) comprising an electronic integrated circuit (LED), the semiconductor die coupled to the substrate (10) and electrically coupled to the circuit component (50) in the glass layer (10A).
Claim(s) 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kawakita et al (US 2015/0084080 A1 hereinafter Kawakita) in view of Feichtinger et al (US 10,014,459 B2 hereinafter Feichtinger) and further in view of Kawakita et al Fig 8 (US 2015/0084080 A1 hereinafter Kawakita8).
Regarding Claim 24, Kawakita and Feichtinger disclose: The device of claim 21,
Kawakita and Feichtinger do not disclose: wherein the circuit component comprises a first layer electrically coupled to the first conductive contact and a second layer on the first layer and electrically coupled to the second conductive contact.
However, Kawakita teaches in Fig 8A: wherein the circuit component comprises a first layer electrically coupled to the first conductive contact and a second layer on the first layer and electrically coupled to the second conductive contact [0095].
References Kawakita, Kawakita8 and Feichtinger are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita and Feichtinger with the specified features of Kawakita8 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Kawakita8 and Feichtinger so that a build-up layer between the glass core and the semiconductor die.
as taught by Kawakita8 in Kawakita’s device since, this provides for a means to connect a varistor.
Regarding Claim 25, Kawakita and Feichtinger disclose: The device of claim 24.
Kawakita does not disclose: wherein the circuit component is a diode or a capacitor.
However, Feichtinger in a similar device teaches in Fig 3: wherein the circuit component (7) is a diode or a capacitor (Col 4 lines 12-30).
References Kawakita, Feichtinger and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita with the specified features of Feichtinger because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Feichtinger and Kawakita9 so that the circuit component is a diode as taught by Kawakita9 in Kawakita’s device since, this provides for an improved esd and thermal performance (Col 1 lines 29-35).
Claim(s) 3, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kawakita et al (US 2015/0084080 A1 hereinafter Kawakita) in view of Kawakita et al Fig 9 (US 2015/0084080 A1 hereinafter Kawakita9) and further in view of Feichtinger et al (US 10,014,459 B2 hereinafter Feichtinger).
Regarding Claim 3, Kawakita discloses: The semiconductor assembly of claim 1.
Kawakita does not disclose: further comprising a build-up layer between the glass core and the semiconductor die.
However, Feichtinger in a similar device teaches in Fig 3: further comprising a build-up layer (15) between the substrate (2) and the semiconductor die (3).
References Kawakita, Feichtinger and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita with the specified features of Feichtinger because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Feichtinger and Kawakita9 so that a build-up layer between the glass core and the semiconductor die.
as taught by Kawakita9 in Kawakita’s device since, this provides for an improved thermal performance (Col 1 lines 29-35).
Regarding Claim 4, Kawakita and Feichtinger disclose: The semiconductor assembly of claim 3.
Kawakita does not disclose: wherein the build-up layer comprises one or more dielectric layers.
However, Feichtinger in a similar device teaches in Fig 3: further comprising a build-up layer (15) between the substrate (2) and the semiconductor die (3).
References Kawakita, Feichtinger and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita with the specified features of Feichtinger because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Feichtinger and Kawakita9 so that a first via extending at least partially through the substrate; a second via extending at least partially through the glass core; a layer extending between and connected to the first via and the second via as taught by Kawakita9 in Kawakita’s device since, this provides for an improved thermal performance (Col 1 lines 29-35).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kawakita et al (US 2015/0084080 A1 hereinafter Kawakita) in view of Kawakita et al Fig 9 (US 2015/0084080 A1 hereinafter Kawakita9) and further in view of Rogers et al (US 2012/0320581 A1 hereinafter Rogers).
Regarding Claim 5, Kawakita discloses in Fig 9 and 10: The semiconductor assembly of claim 1.
Kawakita does not disclose: wherein the semiconductor die comprises an interconnect bridge.
However, Rogers in a similar device teaches in Fig 1A: wherein the semiconductor die comprises an interconnect bridge (300A).
References Kawakita, Rogers and Kawakita9 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Kawakita and Kawakita9 with the specified features of Rogers because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Kawakita, Rogers and Kawakita9 so that the semiconductor die comprises an interconnect bridge as taught by Rogers in Kawakita’s device since, this provides a means to connect various LED die.
Conclusion
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811