Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "each multiplexer output". The antecedent basis for this limitation is unclear. There are multiple different “multiplexer output” limitations previously claimed, and it is unclear to which multiplexer output this limitation refers.
Dependent claim 7 is rejected for being dependent upon a rejected parent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 8-11, 12, 15-17, 19, 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ozgul et al., US Patent 11,061,673 (hereinafter Ozgul) in view of Pfister, US Patent Application Publication 2021/0382686 (hereinafter Pfister).
Regarding claim 1, Ozgul teaches:
An integrated circuit comprising: a vector data processing unit comprising: multiplexing logic operative to shuffle source lane values each corresponding to one of a plurality of vector lanes, to different output vector result lane positions (see e.g. fig. 9, col. 9 lines 52-55, col. 11 line 56-8, multiplexing logic as part of a single permute circuit) by: controlling the multiplexing logic to select source lane values to be placed in a first group of output vector result lane positions of a memory (see e.g. col. 9 lines 52-55, col. 11 line 53 – col. 12 line 3, permutation multiplexers as part of the same single permute circuit); and reusing the multiplexing logic to select source lane values to be placed in a second group of output vector result lane positions of the memory (col. 9 lines 52-55, col. 11 line 53 – col. 12 line 3, the permutation multiplexers as part of the same single permute circuit can select any input and can output to different lane positions), the multiplexing logic comprising a plurality of selected multiplexer outputs that provide a fewer number of output vector result lanes than the full vector result (col. 9 lines 52-55, col. 11 line 53 – col. 12 line 3, the full number of outputs includes a fewer number of outputs, e.g. 2 outputs, that are fewer than the full vector result).
Ozgul fails to explicitly teach the selecting being done in a first cycle and in at least a second cycle for a first portion of a full vector result and a second portion of the full vector result.
Pfister teaches performing multiple iterations (cycles) of permutation by reusing a permutation unit on multiple portions of a full vector (see e.g. para. [0048], [0068]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Ozgul and Pfister to include the selecting being done in a first cycle and in at least a second cycle for a first portion of a full vector result and a second portion of the full vector result. This would have provided “additional flexibility to support larger vectors, without needing to replicate the above described bit permute unit” (see Pfister para. [0048]).
Regarding claim 2, Ozgul in view of Pfister teaches or suggests:
The integrated circuit of claim 1 wherein the memory is a vector result lane register (see e.g. Pfister fig. 7D, para. [0092-3]).
Regarding claim 6, Ozgul in view of Pfister teaches or suggests:
The integrated circuit of claim 2 comprising control logic, operatively coupled to the multiplexing logic, wherein the control logic is operative to programmably control the multiplexing logic to provide multicycle lane shuffling in response to an instruction (see e.g. Ozgul col. 10 lines 30-32).
Regarding claim 8, Ozgul in view of Pfister teaches or suggests:
The integrated circuit of claim 1 wherein the multiplexing logic is operative to: place the selected source lane values from the first cycle into a first set of vector result lane storage elements (see e.g. Pfister para. [0068]); place the selected source lane values from the second cycle into a second and different set of vector result lane storage elements (see e.g. Pfister para. [0068]); and store contents of the two sets of storage elements into a vector result lane register having a same number of positions as the plurality of vector lanes (see e.g. Pfister para. [0072]).
Regarding claim 9, Ozgul in view of Pfister teaches or suggests:
The integrated circuit of claim 2 wherein the multiplexing logic is operative to: place the selected source lane values from the first cycle into a first portion of a vector result lane register (see e.g. Pfister para. [0068]); and place the selected source lane values from the second cycle into a second portion of the vector result lane register different from the first portion thereby concatenating the first and second vector lane values into the vector result lane register (see e.g. Pfister para. [0068]).
Regarding claim 10, Ozgul in view of Pfister teaches or suggests:
The integrated circuit of claim 9 wherein the multiplexing logic is operative to: place the selected source lane values from the first cycle into a first set of vector result lane storage elements as first vector result lane values (see e.g. Pfister para. [0068]); move the first vector result lane values to a vector result register (see e.g. Pfister para. [0068], [0092-3]); place the selected source lane values from the second cycle into the first set of vector result lane storage elements as second vector result lane values (see e.g. Pfister para. [0068]); and move the second vector result lane values to the vector result lane register to concatenate the first and second vector lane values into the vector result lane register (see e.g. Pfister para. [0068]).
Regarding claim 11, Ozgul in view of Pfister teaches or suggests:
The integrated circuit of claim 2 wherein the vector processing unit comprises: the plurality of vector lanes each operative to perform an operation on input vector data and produce respective source lane values for each lane; and to pack the source lane values in a source register (see e.g. Ozgul col. 11 line 53 – col. 12 line 3, Pfister para. [0006]).
Claims 12, 15-17, 19 are rejected for reasons corresponding to those given above for claims 1-2, 6, 8-11 (see also Ozgul col. 8 lines 29-30, floating-point data path).
Claims 20-23 are rejected for reasons corresponding to those given above for claims 1-2, 6, 8-11.
Claims 3-5, 7, 13-14, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ozgul in view of Pfister, further in view of Hung et al., US Patent Application Publication 2023/0076599 (hereinafter Hung).
Regarding claim 3, Ozgul in view of Pfister teaches or suggests:
The integrated circuit of claim 2.
Ozgul in view of Pfister fails to explicitly teach wherein the multiplexing logic comprises a multiplexer per output vector result lane wherein each multiplexer includes an input coupled to receive the source lane values, and a multiplexer output that provides a result lane value per output vector result lane.
Hung teaches a multiplexer per output vector result lane wherein each multiplexer includes an input coupled to receive the source lane values, and an output that provides a result lane value per output vector result lane (see e.g. fig. 5C, para. [0159]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Ozgul, Pfister, and Hung such that the multiplexing logic comprises a multiplexer per output vector result lane wherein each multiplexer includes an input coupled to receive the source lane values, and a multiplexer output that provides a result lane value per output vector result lane. This would have provided an advantage such as described by Hung to “aid in non-aligned accesses, such that a load operation may start from any address and then be aligned down.” (see para. [0159]).
Regarding claim 4, Ozgul in view of Pfister and Hung teaches or suggests:
The integrated circuit of claim 3 and wherein the vector processing unit stores the result lane values from both the first and second cycles in the vector result register as packed vector lane values (see e.g. Pfister para. [0006], Hung para. [0156]).
Regarding claim 5, Ozgul in view of Pfister and Hung teaches or suggests:
The integrated circuit of claim 3 wherein each multiplexer output is coupled to a respective result lane storage element that stores the selected source values output from each multiplexer during each of the first and at least second cycle and wherein the control logic is operative to control the respective result storage elements to store lane values based on which cycle is being processed (see e.g. Pfister para. [0006], [0068]).
Regarding claim 7, Ozgul in view of Pfister and Hung teaches or suggests:
The integrated circuit of claim 5 wherein each respective vector result lane storage element comprises a first set of latches corresponding to the first cycle and at least a second set of latches corresponding to the second cycle (see e.g. Pfister para. [0006], [0068]).
Claims 13-14, 18 are rejected for reasons corresponding to those given above for claims 3-5, 7.
Response to Arguments
Applicant's arguments filed 3/13/26 have been fully considered but they are not persuasive.
Applicant argues a lack of teaching of “reusing the multiplexing logic in at least a second cycle and storing the result lane values from both the first and second cycles in the vector result register as packed lane values and wherein the multiplexing logic [that is reused] comprises a fewer number of output vector result lanes than a number of the plurality of vector lanes and wherein the vector processing unit stores the result lane values from both the first and second cycles from the reused multiplexing logic in the vector result register as packed vector lane values”
Examiner respectfully disagrees. Ozgul was not relied upon to teach the multiplexing logic selection being done in a first cycle and in at least a second cycle for a first portion of a full vector result and a second portion of the full vector result. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Further, the full number of outputs of Ozgul includes a fewer number of outputs, e.g. 2 outputs, that are fewer than the full vector result (col. 9 lines 52-55, col. 11 line 53 – col. 12 line 3). The claim(s) only requires the inclusion of (“comprising”) some number of multiplexer outputs (“a plurality of multiplexer outputs”) that provide a fewer number of output vector result lanes than the full vector result.
Applicant argues that “Combining the teachings of Pfister with those of Ozgul would, inter alia, change the principal of operation of Ozgul.”
Examiner respectfully disagrees. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). There are situations, such as operating on a vector that is larger than Ozgul’s maximum width, that would benefit from being done over multiple cycles. Pfister explains the advantage that this would have provided: “additional flexibility to support larger vectors, without needing to replicate the above described bit permute unit” (see Pfister para. [0048]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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