Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/04/2026 has been entered.
Claims 1- 18 are presented for examination.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chieh (U.S Patent Application Publication 2007/0074054; Reference cited as prior art in previous office action) in view of Matta et.al. (U.S Patent Application Publication 2023/0213997; hereinafter “Mattta) further in view of Mcdonnell et.al. (U.S Patent Application Publication 2019/0042331; hereinafter “Mcdonnell”; Reference cited as prior art in previous office action))
Regarding Claims 1, 7, 13, Chieh discloses A network interface controller comprising[“ The computing device 100 may comprise .. a processor 150..”, 0016; .Fig.1]:
interface circuitry to receive data to be transmitted in a network packet by the network interface controller[“The network interface 130 may provide an interface between the computing device 100 and a network to facility data communication between the computing device 100 and other devices coupled to a network. In particular, the network interface 110 may comprise analog circuitry, digital circuitry, antennae, and/or other components that provide physical, electrical, and protocol interfaces to transfer packets between the computing device 100 and a wired and/or wireless network.”, 0017; “a processor 150”,0016; Fig.1 ; (Processor corresponds to the Network Interface controller)]; and
packet processing pipeline circuitry including network device pipeline stage circuitry including idleness detection circuitry to monitor instructions received by the network device pipeline stage [0017; “The processor 150 may comprise one or more pipelines 160 to process instructions…The pipeline 160 may execute or process a single instruction in a series of pipeline stages 170.sub.0, 170.sub.1 . . . 170.sub.N such as stages, 10 stages, 20 stages,”, 0019; [0017; “The processor 150 may comprise one or more pipelines 160 to process instructions…The pipeline 160 may execute or process a single instruction in a series of pipeline stages 170.sub.0, 170.sub.1 . . . 170.sub.N such as stages, 10 stages, 20 stages,”, 0019; 0021; The stages 170 may also assert an idle signal id to indicate an idle condition of the pipeline 160. For example, stages 170 in one embodiment may assert the idle signal id in response to a swap instruction that causes the processor 150 to change to another thread of instructions at a time when no other thread is ready to be executed. Other components may also assert the idle signal id. ..”, 0022;( i.e. the device pipeline stage circuitry including an idleness detection circuitry to generate an idle signal at a time when there are no instructions/ threads to execute by a stage.)]and to send an idle detection signal to a clock subsystem to reduce a clock frequency of a stage clock for the network device pipeline stage circuitry upon detecting no received data packets in the network device pipeline stage circuitry for a time period[ [ “The stages 170 may be driven by a clock signal clk of the oscillator 120 or a gated clock signal gclk derived from the clock signal of the oscillator 120 in order to control the flow of an instruction from one stage 170.sub.X to the next stage 170.sub.X+1. Due to interdependencies between stages 170, the frequency of the clock signal may be based upon the stage 170 having the longest execution time to ensure each stage 170 completes its phase of an instruction before processing its phase of the next instruction in the pipeline 160…”, 0020;” However, due to flushing of the pipeline 160 in clock cycle T.sub.3, each of stages 170.sub.1, 170.sub.2, 170.sub.3, 170.sub.4 have no instruction to process and thus each is idle in clock cycle T.sub.4. ….”, 0025; “the processor 150 may comprise gated clock logic 180 to gate pipeline stages 160 that have no instruction to execute from the clock signal clk of the oscillator 120. ..The gated clock logic 600 may comprise pipeline clock logic 230, local clock logic 250 and decision logic 620...” ; Fig.6;0033; ( i.e the gated clock logic including the decision, local clock logic and pipeline logic corresponds to the clock subsystem)]; “The decision logic 620 may comprise circuitry such as, for example, the depicted AND gate and latches of FIG. 6 that determine based upon an idle signal id and a local clock signal lclk (i) which stages 170 have instructions and are active, and (ii) which stages 170 do not have instructions and are idle. ..The decision logic 620 may generate control signals ctrl.sub.0, ctrl.sub.1, ctrl.sub.2, and ctrl.sub.3 that cause the pipeline clock logic 230 to gate or prevent the clock signal clk of the oscillator 120 from driving idle stages 170 and that cause the pipeline clock logic 230 to allow or permit the clock signal clk to drive active or non-idle stages 170.”, 0034; Fig.2, 7; ( i.e. based on the idle signal id received by the gated clock logic from a pipeline stage, that indicates that there are no instructions to execute for a time period , clock signal from the oscillator is gated / prevented from driving the corresponding idle pipeline stage . Therefore, the gated clock logic reduces the clock frequency by not driving the clock for a pipeline stage for a time period)];
wherein:
the clock frequency of the stage clock for the network device pipeline stage circuitry is selectable at least in part, based upon configurable control data [0026; “The decision logic 220 may comprise circuitry such as, for example, the depicted AND gate, OR gates, and latches of FIG. 3 that determine based upon a kill signal k and a local clock signal lclk (i) which stages 170 have instructions and are active, and (ii) which stages 170 do not have instructions and are idle. However, other embodiments may implement the decision logic 220 using circuitry components other than the components depicted in FIG. 3. The decision logic 220 may generate control signals ctrl.sub.0, ctrl.sub.1, ctrl.sub.2, and ctrl.sub.3 that cause the pipeline clock logic 230 to gate or prevent the clock signal clk of the oscillator 120 or derived from the oscillator 120 from driving idle stages 170 and that cause the pipeline clock logic 230 to allow or permit the clock signal clk to drive active or non-idle stages 170.”, 0027;( i.e. based on the control signals configured, selectively allowing or gating the clock for the respective stages)];
the configurable control data is configurable to enable and/or disable, at least in part, operation of the idleness detection circuitry[ “..determine based upon an idle signal id and a local clock signal lclk (i) which stages 170 have instructions and are active, and (ii) which stages 170 do not have instructions and are idle..”, 0027;” determine to sequentially assert each control signals ctrl in response to the idle signal id being asserted and may determine to sequentially de-assert each control signal ctrl in response to the idle signal id being de-asserted. s depicted in FIG. 7, the idle signal id is asserted in clock cycle T.sub.1 and de-asserted in clock cycle T.sub.6. Accordingly, the decision logic 620 may determine to sequentially assert each control signal ctrl in clock cycle T.sub.1 and may determine to sequentially de-assert each control signal ctrl in clock cycle T.sub.6. As depicted, the decision logic 620 may sequentially assert one control signal ctrl per a clock cycle in response to the as…”, 0035; “.. the decision logic 220, 620 may determine based upon a local clock signal lclk, a kill signal k, and an idle signal id which stages 170 are idle and which stages 170 are active. Further, the decision logic 220, 620 may generate control signals ctrl indicative of which stages 170 are active and which stages 170 are idle”, 0036; ( i.e. Configuring the control signals to enable or disable the clock for the respective stages based on assertion or de-assertion of the idle signal id generated by the idleness detection circuitry of the pipeline stage)];
the configurable control data is configurable to select respective clock frequencies for respective stages of the pipeline circuitry[ . The decision logic 220 may generate control signals ctrl.sub.0, ctrl.sub.1, ctrl.sub.2, and ctrl.sub.3 that cause the pipeline clock logic 230 to gate or prevent the clock signal clk of the oscillator 120 or derived from the oscillator 120 from driving idle stages 170 and that cause the pipeline clock logic 230 to allow or permit the clock signal clk to drive active or non-idle stages 170.”, 0027; 0035-0036]
However, Chieh does not expressly disclose monitor data packets and detecting no received data packets, the configurable control data is configurable to comprise respective clock divider ratio data for respective stages of the packet processing pipeline circuitry.
In the same field of endeavor (e.g. controlling the system clock frequency of respective pipeline stages based on their performance metric), Matta teaches,
the configurable control data is configurable to comprise respective clock divider ratio data for respective stages of the processing pipeline circuitry[ “ Clock generator 106 can include, for example, an oscillator circuit that provides a system clock signal for components in system 100. As discussed in more detail below, storage controller 110 of DSD 108 can receive this clock signal and generate different clock signals for different pipeline stages 114 based on at least one performance metric and the system clock signal.”, 0012; “ circuitry 112 includes pipeline control modules 20.sub.1 to 20.sub.5 for controlling operation of respective pipeline stages 114.sub.1 to 114.sub.5, performance monitor 10 for determining or measuring one or more performance metrics of pipeline stages 114, and gearboxes 12.sub.1 to 12.sub.5 for generating, adjusting, or setting a clock signal for performing operations by a respective pipeline stage 114.sub.1 to 114.sub.5. In some implementations, gearboxes 12 can include state machines that can scale up and scale down the frequency of their respective output clock signals O(s) to pipeline stages 114.”, 0020; “the overall performance metric C(s) can indicate an overall throughput of commands processed by pipeline stages 114.sub.1 to 114.sub.5. .., a throughput for the one or more pipeline stages can indicate a proportion or percentage of processed commands versus pending commands to be processed by the one or more pipeline stages.”, 0025;0027; “ the one or more performance metrics determined in block 406 can indicate a ratio or other comparison of the number of processed commands during the predetermined period of time to the total number of commands waiting to be processed by the pipeline stage during the predetermined period of time...”, 0039; “For example, if the throughput for the pipeline stage is determined to be greater than a threshold value for the throughput and a number of pending commands is determined to be less than another threshold value, the process returns to block 404 to further decrease the frequency of the clock signal by the predetermined frequency (e.g., masking a second clock cycle out of sixteen clock cycles of the system clock signal). ...”, 0040; ( i.e.. The clock frequency of the respective pipeline stage is increased or decreased with respect to the predetermined system clock frequency based on the proportion/ ratio of the commands processed by the respective pipeline stage. Hence configuring a clock divider ratio data for the respective pipeline stages)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chieh with Matta. Matta’s teaching of controlling the system clock frequency of respective pipeline stages based on their performance metric will substantially improve Cheih’s system to balance pipeline stage delays while saving power for non-throughput intensive traffic profiles based on determining the throughput / performance metric of the respective pipeline stage with a threshold[ 0027].
However, Chieh, Matta does not expressly disclose monitor data packets and detecting no received data packets, packet processing circuitry. Specifically, Chieh discloses monitoring the idle time of a pipeline stage based on whether there are no instructions to be executed by the processing / pipeline stage and generating an idle signal id.. Chieh does not expressly disclose monitoring whether the packets or received or not.
In the same field of endeavor ( e.g. packet distribution among processor cores based on the network traffic and transitioning the worker cores to low power mode when there are no packets available to process by monitoring their respective consumer queues), Mcdonnell teaches ,
monitor data packets and detecting no received data packets [ “..application 160 is a packet processing application… circuitry 120 such as processing cores 122-1 to 122-m, ..and application 160 are executed by one or more processing cores 122-1 to 122-m.”, 0021; ” 0024; “hardware queue manager (HQM) 180 to assist in managing queues of data units. ..HQM 180 is part of circuitry 120”, 0026;” uncore 182 includes a plurality of consumer queues CQ 1 204, CQ 2 206, . . . CQ N 208, ..In an embodiment, a block of metadata is a packet descriptor including information describing a packet. ..“, 0028; HQM 180 distributes packet processing tasks to enabled worker cores 210, 212, . . . 214 by adding packet descriptors to consumer queues CQ 1 204, CQ 2 206, . . . CQ N 208 in uncore 182. …”, 0029; ( i.e each core corresponds to a processing stage to process the packets received form the network); 0035; “At block 706, each worker queue independently polls the worker core's associated consumer queue (or consumer queues, if a worker core is associated with multiple consumer queues). If the consumer queue is not empty at block 708, the worker core gets and processes the next packet descriptor (i.e., a new packet descriptor) in the consumer queue. Processing loops back to block 708. If the consumer queue is empty at block 708, the worker core enters a low power state at block 712 to pend on a next available (e.g., new) consumer queue entry. That is, the worker core will not process any more packet descriptors until a next available packet descriptor is added to the worker core's consumer queue by HQM 180. In an embodiment, the worker core enters a low power state by executing a MWAIT instruction.”, 0039; ( i.e each core monitors whether the packet descriptors are added or empty for the respective consumer queues . If the consumer queue is empty the core enters a low power / sleep state to reduce the power consumption)] , packet processing circuitry[ “Circuitry 120 ..”, 0023; Fig.1;0027; Fig. 2]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chieh in Matta with Mcdonnell. Mcdonnell’s teaching of power aware load balancing among processor cores based on the network traffic and transitioning the worker cores to low power mode when there are no packets available to process will substantially improve Chieh in view of Matta’s system to reduce power consumption and increase efficiency by allowing the cores that are not required to process the packets to be redirected to other tasks and only required when recalled by monitoring their dedicated consumer queue[0003-0004].
Regarding Claims 2, 8, 14, Chieh discloses, wherein the idleness detection circuitry [0022] .
Mcdonnell, monitor a number of received data packets stored in an input First In First Out (FIFO) queue[ 0030; 0033]
Regarding Claims 3, 9, 15, Chieh discloses wherein the clock frequency of the network device pipeline stage circuitry is in idle mode while the idle detection signal is asserted [ 0022] .
Regarding Claims 4, 10, 16, Chieh discloses, wherein the clock frequency of the network device pipeline stage circuitry is in normal mode while the idle detection signal is not asserted [0022; 0034; “the decision logic 220 may ..determine to sequentially de-assert each control signal ctrl in response to the idle signal id being de-asserted. ..”, 0035; ( i.e. determining whether the stages are active and have instructions to execute, accordingly allowing the clock from the oscillator to drive the non-idle stages when the idle signal is de-asserted)] .
Regarding Claim 5, 11, 17, Chieh discloses wherein a first subset of the network device pipeline stage circuitry shares a first idle detection signal [ 0025; Fig.2, 5].
Regarding Claim 6, 12, 18, Chieh discloses wherein each network device pipeline circuitry has an idle detection signal [0022; 0033-0034; Fig.6].
Response to Arguments
Applicant’s arguments with respect to the amended limitations for claim(s) 1,7, 13 have been considered but are moot because the arguments do not apply to Chieh in view of Matta in view of Mcdonnell references as set forth in the current rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shearer et al., U.S Patent Application Publication 2016/0342192, teaches A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
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