DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8-9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0098737) in view of Gardner et al. (US 5,898,317).
With respect to claim 1,
Figures 1A-1C of Sharma disclose an apparatus comprising:
a plurality of logic blocks (104) comprising transistors (106) on a substrate (102), the logic blocks to implement logic functions;
a plurality of input/output (I/O) blocks (128) to connect the logic blocks with components external to the apparatus (see Figure 1B and Paragraph 18);
a plurality of interconnect layers comprising wires (314, 317) and vias (310, 315) surrounded by interlayer dielectric above the substrate, the wires and vias to conductively couple the plurality of logic blocks and the plurality of I/O blocks (see Figure 3A and Paragraph 32);
a plurality of programmable switches (108) to configure connections between the plurality of logic blocks and the plurality of I/O blocks (Paragraph 10).
However, Sharma is silent to a ferroelectric material contacting a metal in a conductive path of a gate of one or more of the transistors.
Gardner, in the same field of endeavor, teaches a field programmable gate array (32) having ferroelectric transistors (Column 2, lines 47-49). Gardner further teaches the use of ferroelectric transistors for the purpose of storing data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use ferroelectric transistors as taught by Gardner, in the logic block of Sharma for the purpose of storing and maintaining data when power is lost (Column 5, lines 3-11).
With respect to claim 8,
The combination of Sharma and Gardner further teaches wherein the logic blocks comprise a static random access memory (SRAM) cell (116) of a field programmable gate array (FPGA) (Paragraph 22).
With respect to claim 9,
Figures 1A-1C of Sharma disclose a field programmable gate array (FPGA) comprising:
a plurality of digital circuits (104) comprising transistors (106) on a substrate (102), the digital circuits to implement logic functions (Paragraph 14);
a plurality of external interfaces (128) to connect the logic blocks with components external to the FPGA (see Figure 1B and Paragraph 18);
a plurality of interconnect layers comprising wires (314, 317) and vias (310, 315) surrounded by interlayer dielectric above the substrate, the wires and vias to conductively couple the plurality of digital circuits and the plurality of external interfaces (see Figure 3A and Paragraph 32);
a plurality of programmable switches (108) to configure connections between the plurality of digital circuits and the plurality of external interfaces (Paragraph 10).
However, Sharma is silent to a ferroelectric material contacting a metal in a conductive path of a gate of one or more of the transistors.
Gardner, in the same field of endeavor, teaches a field programmable gate array (32) having ferroelectric transistors (Column 2, lines 47-49). Gardner further teaches the use of ferroelectric transistors for the purpose of storing data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use ferroelectric transistors as taught by Gardner, in the logic block of Sharma for the purpose of storing and maintaining data when power is lost (Column 5, lines 3-11).
With respect to claim 15,
Figures 1A-1C and 4 of Sharma disclose a system comprising:
a host board (402);
an integrated circuit device (404) coupled to the host board (Paragraph 56), the integrated circuit device comprising:
a plurality of logic blocks (104) comprising static random access memory (SRAM) cells (114) comprising transistors (106) on a semiconductor substrate (102), the logic blocks to implement logic functions;
a plurality of input/output (I/O) blocks (128) connecting the logic blocks with components external to the integrated circuit device (see Figure 1B and Paragraph 18);
a plurality of interconnect layers comprising wires (314, 317) and vias (310, 315) surrounded by interlayer dielectric above the substrate, the wires and vias to conductively couple the plurality of logic blocks and the plurality of I/O blocks (see Figure 3A and Paragraph 32);
a plurality of programmable switches (108) to configure connections between the plurality of logic blocks and the plurality of I/O blocks (Paragraph 10); and
a power supply (Battery of Figure 4) to provide power to the integrated circuit device through the host board (Paragraph 17).
However, Sharma is silent to a ferroelectric material contacting a metal in a conductive path of a gate of one or more of the transistors.
Gardner, in the same field of endeavor, teaches a field programmable gate array (32) having ferroelectric transistors (Column 2, lines 47-49). Gardner further teaches the use of ferroelectric transistors for the purpose of storing data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use ferroelectric transistors as taught by Gardner, in the logic block of Sharma for the purpose of storing and maintaining data when power is lost (Column 5, lines 3-11).
Claim(s) 2, 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma and Gardner as applied to claims 1, 8 and 15 above, and further in view of Masui et al. (US 6,924,663).
With respect to claim 2,
The combination of Sharma and Gardner teaches the invention as claimed, but is silent to wherein the ferroelectric material comprises a ferroelectric fluoride or a perovskite ferroelectric.
Masui, in the same field of endeavor, teaches a programmable logic device with ferroelectric configuration memories and also teaches various ferroelectric materials consisting of lead zirconate titanate (PZT), or other ferroelectric materials with a bismuth-layered perovskite structure, including strontium bismuth tantalate (SBT) (Column 9, lines 47-51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a ferroelectric material such having a bismuth-layered perovskite structure as taught by Masui, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
With respect to claim 10,
The combination of Sharma and Gardner teaches the invention as claimed, but is silent to wherein the ferroelectric material comprises a ferroelectric fluoride or a perovskite ferroelectric.
Masui, in the same field of endeavor, teaches a programmable logic device with ferroelectric configuration memories and also teaches various ferroelectric materials consisting of lead zirconate titanate (PZT), or other ferroelectric materials with a bismuth-layered perovskite structure, including strontium bismuth tantalate (SBT) (Column 9, lines 47-51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a ferroelectric material such having a bismuth-layered perovskite structure as taught by Masui, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
With respect to claim 16,
The combination of Sharma and Gardner teaches the invention as claimed, but is silent to wherein the ferroelectric material comprises a ferroelectric fluoride or a perovskite ferroelectric.
Masui, in the same field of endeavor, teaches a programmable logic device with ferroelectric configuration memories and also teaches various ferroelectric materials consisting of lead zirconate titanate (PZT), or other ferroelectric materials with a bismuth-layered perovskite structure, including strontium bismuth tantalate (SBT) (Column 9, lines 47-51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a ferroelectric material such having a bismuth-layered perovskite structure as taught by Masui, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
Claims 3-7, 11-14 and 17-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JANY RICHARDSON/ Primary Examiner, Art Unit 2844