DETAILED ACTION
This office action is in response to arguments filed 2/2/2026.
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) Claim(s) 1 – 8 and 10 – 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tu (US 20140281385, hereinafter Tu).
As per claim 1, Tu discloses: A processor comprising: a plurality of processing engines; and a sequencing circuit to:
detect a completed execution of a first workload by a first processing engine; (Tu figure 3 and [0035]: “The firmware running a first processing core 310 processes the incoming packets by reading from the input FIFO interface 306 associated with that processing core. When the processing core 310 completes processing of the incoming packet, the firmware of the core outputs an intermediate packet on the output FIFO interface 308 associated with the core. An "intermediate packet" refers to a packet output by a core processor, which results from the processing--by that processing core--of a packet input to the processing core”.)
in response to a detection of the completed execution of the first workload by the first processing engine, identify at least one processing engine specified as consecutive to the first processing engine in a sequence mapping; and activate the at least one processing engine specified as consecutive to execute a second workload. (Tu figure 3 and [0035]: “the intermediate packet is input to the input FIFO interface 306 of the next processing core and processed in accordance with the firmware of that processing core. The processing and forwarding of intermediate packets continues until a final packet is output by the last processing core in the pipeline.”; [0050] – [0051]: “The first processing core 612a processes the packet; changes the packet ID to correspond to the ID of the second processing core 612b (Core1); and inputs the packet to the FIFO interface F0_in. The packet passes through the bus 604 and is received by the fabric logic 606. Based on the packet ID, the fabric logic 606 sends the packet to the FIFO interface F1_out of the second processing core 612b. The second processing core 612b processes the packet; changes the packet ID to correspond to the ID of the third processing core 612c (Core2); and inputs the packet to the FIFO interface F1_in. The packet is then received by the fabric logic 606. Based on the packet ID, the fabric logic 606 sends the packet to the FIFO interface F2_out of the third processing core 612c.”. Examiner notes that the fabric logic 606 sends the packet to the FIFO interface F1_out of the second processing core 612b, and the second processing core 612b processes the packet is mapped to the claimed activating “the at least one processing engine specified as consecutive”.)
As per claim 2, Tu further discloses:
The processor of claim 1, the sequencing circuit comprising a memory to store the sequence mapping. (Tu [0031])
As per claim 3, Tu further discloses:
The processor of claim 1, wherein the at least one processing engine comprises a second processing engine and a third processing engine that are both specified as consecutive to the first processing engine. (Tu [0050] – [0054].)
As per claim 4, Tu further discloses:
The processor of claim 1, the sequencing circuit to: receive a configuration change input via a hardware-software interface; and update, during an execution of the processor, the sequence mapping based on the configuration change input. (Tu [0050] – [0054].)
As per claim 5, Tu further discloses:
The processor of claim 1, the sequencing circuit to: detect the completed execution of a first workload based on an idle signal received from the first processing engine; and send an enable signal to activate the at least one processing engine. (Tu [0050] – [0054].)
As per claim 6, Tu further discloses:
The processor of claim 1, the sequencing circuit to: receive a ready signal indicating that the second workload is available to be executed by the second processing engine; and activate the at least one processing engine in response to a receipt of the ready signal. (Tu [0050] – [0054].)
As per claim 7, Tu further discloses:
The processor of claim 1, wherein the plurality of processing engines is divided into a first domain and a second domain, wherein the first domain comprises the sequencing circuit, and wherein the second domain comprises a second sequencing circuit. (Tu figure 3)
As per claim 8, Tu further discloses:
The processor of claim 1, wherein the plurality of processing engines comprises a plurality of intellectual property blocks included in the processor. (Tu [0006])
As per claim 10, it is the method variant of claim 1 and is therefore rejected under the same rationale.
As per claim 11, it is the method variant of claim 3 and is therefore rejected under the same rationale.
As per claim 12, it is the method variant of claim 4 and is therefore rejected under the same rationale.
As per claim 13, it is the method variant of claim 5 and is therefore rejected under the same rationale.
As per claim 14, it is the method variant of claim 6 and is therefore rejected under the same rationale.
As per claim 15, it is the method variant of claim 7 and is therefore rejected under the same rationale.
As per claim 16, it is the system variant of claim 1 and is therefore rejected under the same rationale.
As per claim 17, it is the system variant of claim 3 and is therefore rejected under the same rationale.
As per claim 18, it is the system variant of claim 4 and is therefore rejected under the same rationale.
As per claim 19, it is the system variant of claim 5 and is therefore rejected under the same rationale.
As per claim 20, it is the system variant of claim 6 and is therefore rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu, in view of Poothia et al (US 20220083389, hereinafter Poothia).
As per claim 9, Tu did not explicitly disclose:
The processor of claim 1, wherein the plurality of processing engines comprises a decoder engine, an inference engine, an encoder engine and a graphic processing unit (GPU).
However, Poothia teaches:
The processor of claim 1, wherein the plurality of processing engines comprises a decoder engine, an inference engine, an encoder engine and a graphic processing unit (GPU). (Poothia [0043])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Poothia into that of Tu in order to have the plurality of processing engines comprises a decoder engine, an inference engine, an encoder engine and a graphic processing unit (GPU). One of ordinary skill in the art can easily recognize that GPU is commonly known and used resources for processing, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Response to Arguments
Applicant's arguments filed 1 – 20 have been fully considered but they are not persuasive.
Claims 1, 10 and 16:
Applicant argued on pages 6 – 7 that Tu does not anticipate the claimed limitations of claims 1, 10 and 16. More specifically, applicant argued that Tu does not teach “activating and/or deactivating its cores” and therefore can not anticipate the limitation “and activate the at least one processing engine specified as consecutive to execute a second workload”.
The examiner disagrees. Tu [0050] – [0051] teaches “The first processing core 612a processes the packet; changes the packet ID to correspond to the ID of the second processing core 612b (Core1); and inputs the packet to the FIFO interface F0_in. The packet passes through the bus 604 and is received by the fabric logic 606. Based on the packet ID, the fabric logic 606 sends the packet to the FIFO interface F1_out of the second processing core 612b. The second processing core 612b processes the packet; changes the packet ID to correspond to the ID of the third processing core 612c (Core2);”. The examiner contents that under broadest reasonable interpretation, The first core process the packet, change the packet ID to the corresponding ID of the second processing core, and input the packet into FIFO to fabric logic, which sends the packet to the second processing core for execution” is the same as activating the at least one processing engine as claimed. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “enabling and disabling of separate hardware units (processing engines)”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196