DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment dated 01/14/2026 has been acknowledged. Claims 1-12 & 19 are cancelled. Claims 13-18, 20-22 are amended. New claims 23-32 are added. Claims 13-18, 20-32 remain pending in application.
Response to Arguments
Applicant’s argument dated 01/14/2026 has been acknowledged.
Applicant’s argument that “FIG. 1K does not show the trench 126 in the base wafer 106. Even if…..a bottom extent of the trench 126 were below an interface between HU's base wafer 106 and semiconductor material 108, the trench bottom would be in a buried layer 112, not the base wafer 106” is not persuasive. Examiner argues, Hu, para [0017] states “The trenches 126 may extend to the buried layer 112, as depicted in FIG. 1C , so that the buried layer 112 extends under the trenches 126”, which renders that the trench 126 may extend into the buried layer 112 as depicted in FIG. 1C (emphasis added)”. However, as annotated FIG. 1C below, the curved bottom surface of the trench 126 is formed below the interface (marked as A-B) between 106 and 108 (emphasis added). Accordingly, examiner argues, trench 126 is formed in the buried layer 112 and since the buried layer 112 is formed in the base wafer 106, therefore, trench 126 is also formed in the base wafer 106.
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Applicant’s further argument that “Hu Is excepted as prior art against claim 21” due to common ownership is not persuasive because common ownership under 102(b)(2)(C) exception only applies to disclosures that qualify as prior art under 102(a)(2) and does not apply to public disclosure under 102(a)(1). The cited Hu reference is a 102(a)(1) public disclosure published more than one year of the effective filing date of the instant application and therefore common ownership can’t disqualify the reference.
Amendment overcomes rejections under 35 USC § 112. Accordingly, 112(b) rejection of original claims 18, 20 & 22 are hereby withdrawn. However, amended claim 22 and new claims 24 & 26 are subject to 112(b) issue under 35 USC § 112 (See 112(b) rejection section below).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22, 24 & 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites, “the deep well” in line 1. It is not clear if it was intended to refer to the “n-type deep well” as recited in line 13 of claim 21 or a different deep well. For examination purpose, examiner is interpreting the recitation as “wherein the n-type deep well provides electrical connection between the second capacitor terminal and the first epitaxial layer.
Claim 24 recites, “…deep well...” in line 2. It is not clear if it was intended to refer to the “n-type deep well” as recited in line 13 of claim 21 or a different deep well. For examination purpose, examiner is interpreting the recitation as “wherein an n-type buried layer is formed in the first epitaxial layer contacting the n-type deep well”.
Claim 26 recites “……the liner…” in line 1 and “ the trench-fill material” in lines 1-2. It is not clear if it was intended to respectively refer to “buried capacitor trench liner dielectric” and “buried capacitor trench-fill material” as recited in line 7 and line 8 respectively or different element. For examination purpose, examiner is interpreting the recitation as “further comprising forming a gap in the buried capacitor trench liner dielectric through which the buried capacitor trench-fill material contacts the base wafer portion”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-22, 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0028316 A1) and further in view of Lu (US patent 4,649,625)
Regarding claim 21, Hu teaches,
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A method of forming a microelectronic device (FIG. 1K) with a buried capacitor (102, para [0012]) including:
forming a first epitaxial layer (108 formed by epitaxial process, para [0013]) on a base wafer portion (106, para [0012]) of a substrate (104, para [0012]);
forming a buried trench capacitor array (102, para [0012]) including:
forming a buried capacitor trench (126, para [0016]) in the first epitaxial layer and in the base wafer portion;
forming a buried capacitor trench liner dielectric (capacitor dielectric 128 comprising 130-132, para [0018]) on the buried capacitor trench;
forming a ……electrically conductive buried capacitor trench-fill material (136, para [0021])) on the buried capacitor trench liner dielectric;
…..forming a first capacitor terminal (112, para [0013], which contacts capacitor plate 108, para [0009], and hence functions as capacitor terminal) contacting the base wafer portion;
and forming a second capacitor terminal (176, para [0044]) contacting an n-type deep well (114 which may be n type, para [0014])) around the buried capacitor trench (126),
But Hu does not explicitly teach,
The trench-fill material 136 is n-type
and forming a second p-type epitaxial layer on the buried trench capacitor array
Meanwhile, Lu teaches,
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and forming a second epitaxial layer (P type 22, col 4, line 31-32) on a buried trench capacitor (including 12 & 14, Col. 4, lines 12-14) extending into a first epitaxial layer (10)
Thus, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify Hu’s method such that the method further comprises forming a second P type epitaxial layer 22 on the buried trench capacitor array 102 extending into first epitaxial layer 108, according to teaching of Lu, in order to bias an access transistor through the epi region 22 (Col. 5, line 4-5) for the purpose of forming a DRAM device using the buried trench capacitor array (Col. 2, lines 55-56).
Hu & Lu still do not explicitly teach,
the trench-fill material 136 is n-type
But Lu teaches, trench fill material 12 may also be N type Poly (see FIG. 1).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Hu’s method such that trench fill material is N type, according to teaching of Lu, in order to form a DRAM device with trench capacitor, as taught by Lu (Col. 2, line 50-52).
Regarding claim 22,Hu & Lu teach the method of claim 21 and Hu further teach, wherein the deep well (114) provides electrical connection between a second buried trench capacitor terminal (176, para[0044] ) and the first epitaxial layer (108).
Regarding claim 24,Hu & Lu teach the method of claim 21 and further teach, wherein an n-type buried layer (layer of 112, para [0013], FIG. 1K) is formed in the first epitaxial layer (108, para [0012]) contacting the deep well (114).
Regarding claim 25,Hu & Lu teach the method of claim 21 and Hu but does not explicitly teaches, wherein a transistor is electrically connected to the first or second capacitor terminal.
But Lu additionally teaches,
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A DRAM device (FIG. 1, Col. 2, ll. 50-51) comprising,
a first epitaxial layer (p-type epitaxial layer 30, Col. 4, line 2) on a base wafer (p+ wafer, col. 4, line 2),
a buried trench capacitor (including 12 & 14, Col. 4, lines 12-14) extending into the first epitaxial layer(as seen);
and a second epitaxial layer (22, which is epitaxially grown, col 4, line 31-32) on the buried trench capacitor, and
an access transistor (including gate 26, Col. 3, ll. 26-27) is formed on top of the buried trench capacitor.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to further modify the method such that an access transistor including gate 26 is formed on top of the buried trench capacitor such that it is electrically connected to the second capacitor terminal 176, according to teaching of Lu, in order to form a DRAM device.
Allowable Subject Matter
Claims 13-18 & 20, 27-32 are allowed.
With respect to claim 13, the prior art made of record does not teach or suggest either alone or in combination “wherein the trench liner dielectric layer includes a gap that provides an electrical connection between a capacitor terminal and the conductive fill material” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
The above limitation incorporates allowable subject matter of original claim 19 as indicated in previous office action.
Claims 14-18 & 20 are allowed being dependent on claim 13.
With respect to claim 27, the prior art made of record does not teach or suggest either alone or in combination “forming trench liner gaps through the trench liner dielectric layers thereby exposing the base wafer at the bottoms of the trenches” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
The above limitation incorporates allowable subject matter of original claim 14 as indicated in previous office action.
Claims 28-32 are allowed being dependent on claim 27.
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claim 23, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
“further comprising forming a dielectric cap on the trench-fill material and forming a p-type epitaxial silicon capping layer on the dielectric cap”
Claim 26 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
With respect to claim 26, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
“further comprising forming a gap in the liner through which the trench-fill material contacts the base wafer portion”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. (FP 7.40)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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