Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 14 is objected to because of the following informalities: There should be a “,” between “(QFN)” and “dual” in line 1. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 7 and 20-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5, line 2, the phrase “an encapsulant surface” is unclear as to which encapsulant layer is it being referred to in claim 1.
Claim 7, line 2, the phrase “an uppermost encapsulant layer” is unclear whether it is being referred to the second layer of encapsulant in claim 1.
Claim 20, lines 3-4. The phrase “the first layer of encapsulant” lacks antecedent basis.
Claim 21, line 1, claim 22, line 2, the phrase “the conductive pad” is unclear whether it is being referred to one of the plurality of conductive pads in claim 14.
Claim 22, line 2, the phrase “the package edge” lacks antecedent basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 14-15, 17, 19, 21-24 and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 8664044; hereinafter Jin) in view of Lin et al. (US 8164171; hereinafter Lin).
Regarding claim 1, Jin discloses a small outline no-lead (SON) package without a leadframe, comprising:
a semiconductor chip 102 (figs. 3 and 9) comprising conductive studs 104 (fig. 3) over an active layer of the semiconductor chip 102 (fig. 9), wherein each of the conductive studs 104 comprise a first end directly connected to the active layer of the semiconductor chip 102 (fig. 9);
a first layer of encapsulant (labeled fig. 3, column 2, lines 54+, column 6, lines 61+) disposed as a single layer around four side surfaces of the semiconductor chip 102 and around the conductive studs 104 (fig. 3);
a first conductive layer 112 (fig. 9) and first vertical conductive contacts (lower portion of [158]) (fig. 9) electrically coupled with the conductive studs 104 (fig. 3 and 9) of the semiconductor chip 102, the first conductive layer 112 comprising conductive traces (fig. 9, column 4, lines 56+) formed over a planarized surface of the first layer of encapsulant (fig. 9) and conductive studs 104 (fig. 3);
a second layer of encapsulant [162, 156] disposed over the first encapsulant layer, the first conductive layer 112, the conductive traces (fig. 9, column 4, lines 56+), and the first vertical conductive contacts (lower portion of [158]) (fig. 9);
a plurality of conductive pads [164, 160, upper portion of 158] in the form of land pads formed over a planarized surface of the second layer of encapsulant [162, 156] and in electrical contact with the first vertical conductive contacts (lower portion of [158]) (fig. 9); and
a solderable metal system (SMS) (column 5, lines 27-31) formed over at least a portion of the plurality of conductive pads [164, 160] (column 5, lines 27-31);
wherein each conductive pad [164, 160, upper portion of 158] includes a continuous conductive material path (upper portion of [158]) vertically from the conductive pad to the first conductive layer [112], and a portion of the second layer of encapsulant [162, 156] is horizontally sandwiched between the first conductive layer [112] and the conductive pads [164, 160, upper portion of 158] to lock the second layer of encapsulant [162, 156] between the first conductive layer and the conductive pads.
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Jin does not disclose wherein the conductive studs comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end and the first layer of encapsulant disposed as a single layer over the active layer of the semiconductor chip.
However, Lin discloses a device comprising: the conductive studs 24 (fig. 11) comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end (column 13, lines 4+) and the first layer of encapsulant 85 (fig. 11) disposed as a single layer over the active layer of the semiconductor chip 120 (fig. 11).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin by having the conductive studs comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end and the first layer of encapsulant disposed as a single layer over the active layer of the semiconductor chip, as taught by Lin, in order to increase the device functionality of the package structure.
Regarding claim 2, Jin discloses that wherein the SMS is a single layer comprising at least one of a layer of silver, tin, gold formed over the conductive pads [164, 160] (column 5, lines 27-31) and the SMS (column 5, lines 27-31) comprising a layer of conductive materials over the conductive pads 164 (column 5, lines 27-31).
The recitation of “formed by one or more of electroplating, electroless plating, immersion plating, physical vapor deposition (PVD), and chemical vapor deposition (CVD)” is a process limitation which depends upon the product claim of independent claim 1. All the process limitations in claim 2 do not carry weight. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113.
Regarding claim 3, Jin discloses that at least one of the conductive traces 112 (fig. 9, column 4, lines 56+) is coupled to at least one conductive stud 104 (figs. 3 and 6) such that the at least one conductive trace 112 is narrower in at least one direction than a greatest width of the at least one conductive stud 104 (figs. 3 and 6).
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Regarding claim 14, Jin discloses a small outline no- lead (SON) package without a leadframe, comprising:
a semiconductor chip 102 (figs. 3 and 9) comprising conductive studs 104 (fig. 3) over an active layer of the semiconductor chip 102 (figs. 3 and 9), wherein the conductive studs comprise a first end directly connected to the active layer (figs. 3 and 9);
encapsulant (labeled fig. 3, column 2, lines 53+, column 6, lines 61+) disposed in a single layer around four side surfaces of the semiconductor chip 102, and around a portion of sidewalls of the conductive studs 104 (fig. 3);
conductive traces 112 (fig. 9, column 4, lines 56+) formed over a planarized surface of the encapsulant and conductive studs 104 (figs. 3 and 9);
a plurality of conductive pads [164, 160, 158] (fig. 9) in the form of land pads formed over the encapsulant and in electrical contact with the conductive studs 104 (figs. 3 and 9);
wherein each conductive pad includes a continuous conductive material path [158] vertically from the conductive pad to a first conductive layer [112], and a portion of at least one layer of encapsulant [156, 162] is horizontally sandwiched between at least two layers of conductive material [164, 160, 112] to lock the at least one layer of encapsulant [156, 162] between the at least two layers of conductive material [164, 160, 112].
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Jin does not disclose wherein the conductive studs comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end and the first layer of encapsulant disposed as a single layer over the active layer of the semiconductor chip.
However, Lin discloses a device comprising: the conductive studs 24 (fig. 11) comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end (column 13, lines 4+) and the first layer of encapsulant 85 (fig. 11) disposed as a single layer over the active layer of the semiconductor chip 120 (fig. 11).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin by having the conductive studs comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end and the first layer of encapsulant disposed as a single layer over the active layer of the semiconductor chip, as taught by Lin, in order to increase the device functionality of the package structure.
Regarding claim 15, Jin further discloses a solderable metal system (SMS) (column 5, lines 27-31) formed over at least a portion of the conductive pads [164], wherein the SMS comprising a layer of conductive materials over the conductive pads 164 (column 5, lines 27-31).
The recitation of “formed by one or more of electroplating, electroless plating, immersion
plating, physical vapor deposition (PVD), and chemical vapor deposition (CVD)” is a process limitation
which depends upon the product claim of independent claim 1. All the process limitations in claim 15 do not carry weight. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113.
Regarding claim 17, Jin further discloses each conductive pad [164, 160, 158] includes at least two layers of encapsulant [156, 162] interlocked between at least three layers of conductive material [112, 158, 160, 164].
Regarding claim 19, Jin discloses a solderable metal system (SMS) formed applied over at least a portion of the conductive pads [164], wherein the SMS is a single layer comprising at least one of a layer of silver, tin, gold formed over the conductive pads 164 (column 5, lines 27-31).
Regarding claim 21, Jin discloses that wherein the conductive pad 164 (fig. 9) extends beyond a surface edge of an uppermost encapsulant layer 162 (fig. 9).
Regarding claim 22, Jin discloses the device comprising an offset between an edge or side of the conductive pad 164 (fig. 9) and the package edge (labeled fig. 9).
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Regarding claim 23, Jin discloses that wherein the encapsulant (labeled fig. 3) of at least one of the first layer of encapsulant comprises a mold compound (column 2, lines 54+).
Regarding claim 24, Jin discloses that wherein the SON package (figs. 3 and 9) is formed without exposed copper on the SON package (figs. 3 and 9).
Regarding claim 26, Jin discloses a thermal path (labeled fig. 9) in the form of a thermal stud (labeled fig. 9) configured to conduct thermal energy from the package 150 (fig. 9) to a circuit board (column 4, lines 63-65 and column 5, lines 27-31) to which the package 150 is mounted (fig. 9).
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Jin does not explicitly disclose the circuit board is a printed circuit board.
However, Lin discloses a device comprising: a printed circuit board (column 1, lines 56-57).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin by having the printed circuit board, as taught by Lin, in order to increase the device functionality of the semiconductor package.
Regarding claim 27, Jin discloses a thermal dissipative die plate 154 (fig. 9, column 5, lines 9+) on the SON package 150 (fig. 9).
Jin as modified by Lin do not disclose the dummy thermal conductive stumps formed over the active layer of the semiconductor chip.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the dummy thermal conductive stumps formed over the active layer of the semiconductor chip.
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin and Lin by having the dummy thermal conductive stumps formed over the active layer of the semiconductor chip, in order to provide additional elements and enhance the structural strength of the device.
Regarding claim 28, Jin discloses that wherein the SON package (figs. 3 and 9) includes no solder balls (figs. 3 and 9).
Regarding claim 29, Jin discloses the device further comprising additional conductive studs 104 formed over the encapsulant (labeled fig. 3).
Claim 6-11, 13, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Lin, further in view of Wang et al. (US 2025/0372406).
Regarding claim 6, Jin and Lin differ from the claimed invention by not showing one or more conductive structure over the semiconductor chip and over the second layer of encapsulant.
Wang et al. discloses a conductive structure [300] over the semiconductor chip [100] and over the second layer of encapsulant [IL1] in fig. 3E.
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin and Lin by having the conductive structure of Wang et al. because it provides external connection for the semiconductor chip.
Regarding claim 7, Jin discloses that wherein the conductive pad 164 (fig. 9) extends beyond a surface edge of an uppermost encapsulant layer 162 (fig. 9).
Regarding claim 8, Jin discloses the device comprising an offset between an edge or side of the conductive pad 164 (fig. 9) and the package edge (labeled fig. 9).
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Regarding claim 9, Jin discloses that wherein the encapsulant (labeled fig. 3) of at least one of the first layer of encapsulant comprises a mold compound (column 2, lines 54+).
Regarding claim 10, Jin discloses that wherein the SON package (figs. 3 and 9) is formed without exposed copper on the periphery of the package (figs. 3 and 9).
Regarding claim 11, Jin discloses that wherein the SON package (figs. 3 and 9) is formed without exposed copper on the SON package (figs. 3 and 9).
Regarding claim 13, Jin discloses the device further comprising additional conductive studs 104 (fig. 1B) formed over the first layer of encapsulant (labeled fig. 3).
Regarding claim 16, Jin and Lin differ from the claimed invention by not showing the at least one layer of encapsulant horizontally sandwiched between the at least two layers of conductive material is of a same kind of encapsulant disposed around the semiconductor chip.
Wang et al. discloses the at least one layer of encapsulant [IL1] horizontally sandwiched between the at least two layers of conductive material [M1, M2] is of a same kind of encapsulant (IL1, (epoxy), paragraph [0029]) as the encapsulant (epoxy [200], paragraph [0037]) disposed around the semiconductor chip [100] in fig. 3E.
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin and Lin by having the encapsulants of Wang et al. because it provides solid protection for the semiconductor chip and the wiring layers above the semiconductor chip.
Regarding claim 20, Jin and Lin differ from the claimed invention by not showing one or more conductive structure over the semiconductor chip and over the second layer of encapsulant disposed over the first layer of encapsulant.
Wang et al. discloses a conductive structure [300] over the semiconductor chip [100] and over the second layer of encapsulant [IL1] disposed over the first layer of encapsulant [200] in fig. 3E.
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin and Lin by having the conductive structure of Wang et al. because it provides external connection for the semiconductor chip.
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 8664044; hereinafter Jin in view of Lin et al. (US 8164171).
Regarding claim 4, Jin discloses a small outline no-lead (SON) package without a leadframe, comprising:
a semiconductor chip 102 (figs. 3 and 9) comprising conductive studs 104 (fig. 3) over an active surface of the semiconductor chip 102 (fig. 9), wherein each of the conductive studs 104 comprise a first end coupled to the active layer of the semiconductor chip 102 (fig. 9);
a first layer of encapsulant (labeled fig. 3, column 2, lines 54+, column 6, lines 61+) disposed as a single layer around four side surfaces of the semiconductor chip 102 and around the conductive studs 104 (fig. 3);
a first conductive layer 112 (fig. 9) and first vertical conductive contacts (lower portion of [158]) (fig. 9) electrically coupled with the conductive studs 104 (fig. 3 and 9) of the semiconductor chip 102, the first conductive layer 112 comprising conductive traces (fig. 9, column 4, lines 56+) formed over a planarized surface of the first layer of encapsulant (fig. 9) and conductive studs 104 (fig. 3);
a second layer of encapsulant [156, 162] disposed over the first encapsulant layer, the first conductive layer 112, the conductive traces (fig. 9, column 4, lines 56+), and the first vertical conductive contacts (lower portion of [158]) (fig. 9);
a plurality of conductive pads [164, 160, upper portion of 158] in the form of land pads formed over a planarized surface of the second layer of encapsulant [156, 162] and in electrical contact with the first vertical conductive contacts [lower portion of 158] (fig. 9), wherein each conductive pad includes at least a continuous conductive material path (upper portion of [158)) vertically from the conductive pad [164, 160, upper portion of 158] to the first conductive layer [112], and a portion of the second layer of encapsulant [156, 162] is horizontally sandwiched between the first conductive layer [112] and the conductive pads [164, 160, upper portion of 158] to lock the second layer of encapsulant [156, 162] between the first conductive layer [112] and the conductive pads [164, 160, upper portion of 158]; and
a solderable metal system (SMS) (column 5, lines 27-31) formed over at least a portion of the conductive pads 164 (column 5, lines 27-31).
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Jin does not disclose wherein the conductive studs comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end, the first layer of encapsulant disposed as a single layer over the active layer of the semiconductor.
However, Lin discloses a device comprising: the conductive studs 24 (fig. 11) comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end (column 13, lines 4+) and the first layer of encapsulant 85 (fig. 11) disposed as a single layer over the active layer of the semiconductor chip 120 (fig. 11).
Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin by having the conductive studs comprise a second end opposite the first end wherein the second end is in a range of 1-50 micrometers from the first end and the first layer of encapsulant disposed as a single layer over the active layer of the semiconductor chip, as taught by Lin, in order to increase the device functionality of the package structure.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 8664044; hereinafter Jin) in view of Lin et al. (US 8164171), further in view of Boettcher et al. (“Embedding of Chips for System in Package realization – Technology and Applications.” 2008. Pages 383-386) (IDS filed on 9/30/2022).
Regarding claim 5, as discussed in details above, Jin as modified by Lin substantially discloses all the limitation as claimed above except for a redistribution layer formed directly upon an encapsulant surface, and wherein the second layer of encapsulant is formed directly upon the redistribution layer, wherein the encapsulant surface and the second layer of encapsulant are of the same kind of encapsulant.
However, Boettcher et al. discloses a small outline package comprising: a conductive layer comprises a redistribution layer (labeled fig. 17) formed directly upon an encapsulant surface (labeled fig. 17), and wherein the second layer of encapsulant is formed directly upon the redistribution layer, wherein the encapsulant surface and the second layer of encapsulant (labeled fig. 17) are of the same kind of encapsulant (fig. 17).
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Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin and Lin by having the redistribution layer formed directly upon an encapsulant surface, and wherein the second layer of encapsulant is formed directly upon the redistribution layer, wherein the encapsulant surface and the second layer of encapsulant are of the same kind of encapsulant, as taught by Boettcher et al., in order to improve an efficiency and design flexibility in mounting semiconductor device.
Regarding claim 18, as discussed in details above, Jin as modified by Lin substantially discloses all the limitation as claimed above except for a redistribution layer formed directly upon an encapsulant surface, and encapsulant disposed directly upon the redistribution layer, wherein the encapsulant upon
which the redistribution layer is formed and the encapsulant disposed directly upon the redistribution layer are of the same kind of encapsulant.
However, Boettcher et al. discloses a small outline package comprising: a redistribution layer (labeled below fig.) formed directly upon an encapsulant surface (labeled fig. 17), and encapsulant (labeled fig. 17) disposed directly upon the redistribution layer, wherein the encapsulant (labeled below fig.) upon which the redistribution layer is formed and the encapsulant disposed directly upon the redistribution layer are of the same kind of encapsulant (labeled fig. 17).
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Therefore, it would have been obvious to one skilled in the art before the effective filing of the claimed invention was made to modify the device of Jin and Lin by having the redistribution layer formed directly upon an encapsulant surface, and encapsulant disposed directly upon the redistribution layer, wherein the encapsulant upon which the redistribution layer is formed and the encapsulant disposed directly upon the redistribution layer are of the same kind of encapsulant, as taught by
Boettcher et al., in order to improve an efficiency and design flexibility in mounting semiconductor device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-11, 13-24 and 26-29 have been considered but are moot because the new ground of rejection.
Conclusion
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/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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