DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment
Acknowledgment is made of applicant's Amendment, filed 07-27-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 1, 2, 18 and 19 has/have been amended, and claim(s) 1-12 and 18-20 remain(s) pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 8-10, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Der Sluis, US 20050269611 A1, in view of Manfrini, US 20210398991 A1.
As to claim 1, Van Der Sluis discloses a memory device (see Van Der Sluis Fig 3 Ref 11) comprising:
a memory cell (see Van Der Sluis Fig 3 Ref 10) comprising: a transistor (see Van Der Sluis Fig 3 Ref 6) comprising a first source or drain (S/D) region and a second S/D region each in or on a semiconductor layer of a front end of line portion of an integrated circuit (IC) chip (see Van Der Sluis Fig 1 Refs 7, 8 and 11; CMOS transistors that are manufactured on a semiconductor substrate are fabricated on the FEOL portion of the circuit.);
a ferroelectric (FE) resistive junction structure (see Van Der Sluis Fig 3 Ref 4 and Paras [0002] and [0003]) coupled to the transistor, the FE resistive junction structure comprising: a first electrode structure (see Van Der Sluis Fig 3 Ref 3); a second electrode structure (see Van Der Sluis Fig 3 Ref 5); and a layer of one of a FE oxide or a FE semiconductor between the first electrode structure and the second electrode structure (see Van Der Sluis Paras [0003] and [0006]); wherein:
the first electrode structure, the second electrode structure, and the layer of the one of the FE oxide or the FE semiconductor are in a vertical arrangement relative to each other (see Van Der Sluis Fig 1 Refs 2, 3, and 5).
Van Der Sluis does not appear to explicitly disclose the first S/D region is electrically coupled to a first via structure which extends vertically through a first dielectric material of a first insulator layer of a back end of line portion of the IC chip; and
a body of a second dielectric material other than the first dielectric material, wherein the body adjoins and extends horizontally around the FE resistive junction structure in the first insulator layer
and the second S/D region is electrically coupled to the FE resistive junction structure.
Manfrini discloses the first S/D region is electrically coupled to a first via structure which extends vertically through a first dielectric material of a first insulator layer of a back end of line portion of the IC chip (see Manfrini Fig 5 Refs 620 and 622, and Para [0020]); and
a body of a second dielectric material other than the first dielectric material, wherein the body adjoins and extends horizontally around the FE resistive junction structure in the first insulator layer (see Manfrini Fig 5 Ref 170; The IDL surrounds the resistive structure.)
and the second S/D region is electrically coupled to the FE resistive junction structure (see Manfrini Para [0054]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Van Der Sluis, may implement a particular IDL schema, as disclosed by Manfrini. The inventions are well known variants of memory devices implementing ferroelectric elements, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Manfrini’s attempt to integrate low-power ferroelectric devices (see Manfrini Para [0017]).
As to claim 2, Van Der Sluis and Manfrini disclose the memory device of claim 1, wherein
the transistor comprises a gate terminal, a first S/D terminal, and a S/D terminal (see Van Der Sluis Fig 1 Ref 6), the memory device further comprising: a word line (see Van Der Sluis Fig 3 Ref 30) coupled to the transistor via the gate terminal; a bit line (see Van Der Sluis Fig 3 Ref 20) coupled to the FE resistive junction structure via the first electrode structure, wherein
the first S/D terminal is coupled to the second electrode structure; and a select line (see Van Der Sluis Fig 3 Ref 40) coupled to the transistor via the S/D terminal.
As to claim 8, Van Der Sluis and Manfrini disclose the memory device of claim 1, wherein
the one of the FE oxide or the FE semiconductor is the FE semiconductor (see Van Der Sluis Paras [0003] and [0006]).
As to claim 9, Van Der Sluis and Manfrini disclose the memory device of claim 8, wherein
the FE semiconductor comprises indium (In) and selenium (Se) (see Van Der Sluis Para [0003]).
As to claim 10, Van Der Sluis and Manfrini disclose the memory device of claim 9, wherein
a thickness of one of the first electrode structure or the second electrode structure is in a particular range (see Van Der Sluis Paras [0003] and [0029]), and wherein a thickness of the FE semiconductor is in another particular range (see Van Der Sluis Paras [0003] and [0029]).
Van Der Sluis does not appear to explicitly disclose a range of 5 nanometers (nm) to 30 nm, and a range of 3 nm to 70 nm.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that the ranges disclosed are similar to the ranges claimed (see MPEP 2144.05.I). The broadest of the language of limitation does not disclose criticality of claimed ranges, and the disclosure of Van Der Sluis makes the claimed range obvious (see MPEP 716.02(d).II).
As to claim 18, Van Der Sluis and Manfrini disclose a system (see Van Der Sluis Fig 3) comprising:
a microprocessor (see Van Der Sluis Para [0031]; Applying voltages requires processing circuits. Integrated circuits are well known.). comprising circuitry to execute an instruction (see Van Der Sluis Para [0031]; Reading requires instructions.); a memory device (see Van Der Sluis Fig 3 Ref 11) coupled to the microprocessor, the memory device comprising: a memory cell (see Van Der Sluis Fig 3 Ref 10) comprising: a transistor (see Van Der Sluis Fig 3 Ref 6) comprising a first source or drain (S/D) region and a second S/D region each in or on a semiconductor layer of a front end of line portion of an integrated circuit (IC) chip (see Van Der Sluis Fig 1 Refs 7, 8 and 11; CMOS transistors that are manufactured on a semiconductor substrate are fabricated on the FEOL portion of the circuit.), wherein
the first S/D region is electrically coupled to a first via structure which extends vertically through a first dielectric material of a first insulator layer of a back end of line portion of the IC chip (see Manfrini Fig 5 Refs 620 and 622, and Para [0020]); a ferroelectric (FE) resistive junction structure (see Van Der Sluis Fig 3 Ref 4 and Paras [0002] and [0003]) coupled to the transistor, the FE resistive junction structure comprising: a first electrode structure (see Van Der Sluis Fig 3 Ref 3); a second electrode structure (see Van Der Sluis Fig 3 Ref 5); and a layer of one of a FE oxide or a FE semiconductor between the first electrode structure and the second electrode structure (see Van Der Sluis Paras [0003] and [0006]); and a body of a second dielectric material other than the first dielectric material, wherein the body adjoins and extends horizontally around the FE resistive junction structure in the first insulator layer (see Manfrini Fig 5 Ref 170; The IDL surrounds the resistive structure.); wherein:
the first electrode structure, the second electrode structure, and the layer of the one of the FE oxide or the FE semiconductor are in a vertical arrangement relative to each other (see Van Der Sluis Fig 1 Refs 2, 3, and 5).
and the second S/D region is electrically coupled to the FE resistive junction structure (see Manfrini Para [0054]).
As to claim 19, Van Der Sluis and Manfrini disclose the system of claim 18.
Claim 19 recites substantially the same limitations as claim 2.
All the limitations of claim 19 have already been disclosed by Van Der Sluis in claim 2 above.
As to claim 20, Van Der Sluis and Manfrini disclose the system of claim 18.
Claim 20 recites substantially the same limitations as claim 9.
All the limitations of claim 20 have already been disclosed by Van Der Sluis in claim 9 above.
Claim(s) 1-4, 6, 7, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schröder, US 20170256552 A1, in view of Manfrini, US 20210398991 A1.
As to claim 1, Schröder discloses a memory device (see Schröder Para [0004]) comprising:
a memory cell (see Schröder Fig 8A) comprising: a transistor (see Schröder Para [0067) comprising a first source or drain (S/D) region and a second S/D region each in or on a semiconductor layer of a front end of line portion of an integrated circuit (IC) chip (see Schröder Fig 8A Refs 800A, 801A, and 802A; CMOS transistors that are manufactured on a semiconductor substrate are fabricated on the FEOL portion of the circuit.), wherein the first S/D region is electrically coupled to a first via structure (see Schröder Fig 8A via between Refs 101A and 801A) which extends vertically through a first dielectric material of a first insulator layer (see Schröder Fig 8A unlabeled void between the reference characters; Microelectronic circuits require an IDL to prevent shorting between the components.); a ferroelectric (FE) resistive junction structure (see Schröder Para [0067]) coupled to the transistor, the FE resistive junction structure comprising: a first electrode structure (see Schröder Fig 8A Ref 103A); a second electrode structure (see Schröder Fig 8A Ref 101A); and a layer of one of a FE oxide or a FE semiconductor between the first electrode structure and the second electrode structure (see Schröder Fig 8A Ref 102 and Para [0015]); wherein:
the first electrode structure, the second electrode structure, and the layer of the one of the FE oxide or the FE semiconductor are in a vertical arrangement relative to each other (see Schröder Fig 8A Refs 101A, 102, and 103A); and the second S/D region is electrically coupled to the FE resistive junction structure (see Schröder Fig 8A Ref 801A).
Schröder does not appear to explicitly disclose a first insulator layer of a back end of line portion of the IC chip; and
a body of a second dielectric material other than the first dielectric material, wherein the body adjoins and extends horizontally around the FE resistive junction structure in the first insulator layer.
Manfrini discloses a first insulator layer of a back end of line portion of the IC chip (see Manfrini Fig 5 Refs 620 and 622, and Para [0020]); and
a body of a second dielectric material other than the first dielectric material, wherein the body adjoins and extends horizontally around the FE resistive junction structure in the first insulator layer (see Manfrini Fig 5 Ref 170; The IDL surrounds the resistive structure.).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Schröder , may implement a particular IDL schema, as disclosed by Manfrini. The inventions are well known variants of memory devices implementing ferroelectric elements, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Manfrini’s attempt to integrate low-power ferroelectric devices (see Manfrini Para [0017]).
As to claim 2, Schröder and Manfrini disclose the memory device of claim 1, wherein
the transistor comprises a gate terminal, a first S/D terminal, and a S/D terminal (see Schröder Fig 8A), the memory device further comprising: a word line (see Schröder Fig 8A Ref 804A) coupled to the transistor via the gate terminal; a bit line (see Schröder Fig 8A interconnect above Ref 103A) coupled to the FE resistive junction structure via the first electrode structure, wherein
the first S/D terminal is coupled to the second electrode structure; and a select line (see Schröder Fig 8A Ref 805A) coupled to the transistor via the second S/D terminal.
As to claim 3, Schröder and Manfrini disclose the memory device of claim 1, wherein
the one of the FE oxide or the FE semiconductor is the FE oxide (see Schröder Para [0015]).
As to claim 4, Schröder and Manfrini disclose the memory device of claim 1, wherein
the FE oxide comprises hafnium (Hf), oxygen (O), and one of silicon (Si), germanium (Ge), nitrogen (N), aluminum (Al), yttrium (Y), gadolinium (Gd), or lanthanum (La) (see Schröder Para [0015]).
As to claim 6, Schröder and Manfrini disclose the memory device of claim 3, wherein
the FE resistive junction structure further comprises a first dielectric layer between the FE oxide and the first electrode structure (see Schröder Fig 9A Ref 901A and Para [0016]).
As to claim 7, Schröder and Manfrini disclose the memory device of claim 6, wherein
the FE resistive junction structure further comprises a second dielectric layer between the FE oxide and the second electrode structure (see Schröder Fig 9A Ref 901A and Para [0016]).
As to claim 18, Schröder and Manfrini disclose a system (see Schröder Para [0003]) comprising:
a microprocessor (see Schröder Para [0010]; Applying voltages requires processing circuits. Integrated circuits are well known.) comprising circuitry to execute an instruction (see Schröder Para [0012]; Reading requires instructions.); a memory device (see Schröder Para [0004] coupled to the microprocessor, the memory device comprising: a memory cell (see Schröder Fig 8A) comprising: a transistor (see Schröder Para [0067]) comprising a first source or drain (S/D) region and a second S/D region each in or on a semiconductor layer of a front end of line portion of an integrated circuit (IC) chip (see Schröder Fig 8A Refs 800A, 801A, and 802A; CMOS transistors that are manufactured on a semiconductor substrate are fabricated on the FEOL portion of the circuit.), wherein the first S/D region is electrically coupled to a first via structure (see Schröder Fig 8A via between Refs 101A and 801A) which extends vertically through a first dielectric material of a first insulator layer (see Schröder Fig 8A unlabeled void between the reference characters; Microelectronic circuits require an IDL to prevent shorting between the components.) of a back end of line portion of the IC chip (see Manfrini Fig 5 Refs 620 and 622, and Para [0020]); a ferroelectric (FE
resistive junction structure (see Schröder Para [0067]) coupled to the transistor, the FE resistive junction structure comprising: a first electrode structure (see Schröder Fig 8A Ref 103A); a second electrode structure (see Schröder Fig 8A Ref 101A); and a layer of one of a FE oxide or a FE semiconductor between the first electrode structure and the second electrode structure (see Schröder Fig 8A Ref 102 and Para [0015]) ; and a body of a second dielectric material other than the first dielectric material, wherein the body adjoins and extends horizontally around the FE resistive junction structure in the first insulator layer (see Manfrini Fig 5 Ref 170; The IDL surrounds the resistive structure.); wherein:
the first electrode structure, the second electrode structure, and the layer of the one of the FE oxide or the FE semiconductor are in a vertical arrangement relative to each other (see Schröder Fig 8A Refs 101A, 102, and 103A).
and the second S/D region is electrically coupled to the FE resistive junction structure (see Schröder Fig 8A Ref 801).
As to claim 19, Schröder and Manfrini disclose the system of claim 18.
Claim 19 recites substantially the same limitations as claim 2.
All the limitations of claim 19 have already been disclosed by Schröder in claim 2 above.
As to claim 20, Schröder and Manfrini disclose the system of claim 18.
Claim 20 recites substantially the same limitations as claim 4.
All the limitations of claim 20 have already been disclosed by Schröder in claim 4 above.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schröder, US 20170256552 A1 and Manfrini, US 20210398991 A1, in view of Chang, US 20200286984 A1.
As to claim 5, Schröder and Manfrini disclose the memory device of claim 4, wherein
a thickness of one of the first electrode structure or the second electrode structure is in a particular range, and wherein a thickness of the FE oxide is another particular range (see Schröder Para [0057]).
Schröder and Manfrini do not appear to disclose equal to or less than 0.5 nm.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that the ranges disclosed are similar to the ranges claimed (see MPEP 2144.05.I). The broadest of the language of limitation does not disclose criticality of claimed ranges, and the disclosure of Schröder makes the claimed range obvious (see MPEP 716.02(d).II).
Schröder and Manfrini do not appear to disclose a range of 5 nanometers (nm) to 30 nm.
Chang discloses a range of 5 nanometers (nm) to 30 nm (see Chang Para [0022]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Schröder and Manfrini, may implement particular electrode thickness, as disclosed by Chang. The inventions are well known variants of memory devices implementing ferroelectric elements, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Chang’s attempt to reduce voltage transients (see Chang Para [0018]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Der Sluis, US 20050269611 A1 and Manfrini, US 20210398991 A1, in view of Liu, US 20170301385 A1.
As to claim 11, Van Der Sluis and Manfrini disclose the memory device of claim 8, wherein
the FE resistive junction structure further comprises contact with the electrode.
Van Der Sluis and Manfrini do not appear to explicitly disclose a first dielectric layer between the FE semiconductor and the first electrode structure.
Liu discloses a first dielectric layer between the FE semiconductor and the first electrode structure (see Liu Fig 1 Ref 150 and Para [0085]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Van Der Sluis and Manfrini, may implement particular dielectric structures, as disclosed by Liu. The inventions are well known variants of memory devices implementing ferroelectric elements, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Liu’s attempt to engineer the on/off ratio of the device (see Liu Para [0085]).
Response to Arguments
Applicant's arguments filed 07/27/2026 have been fully considered but they are not persuasive.
New art has been provided which reads on the amended language.
Allowable Subject Matter
Claim(s) 12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior are does not appear to disclose (as recited in claim 12):
the FE resistive junction structure further comprises a second dielectric layer between the FE semiconductor and the second electrode structure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 09/23/2026
