Prosecution Insights
Last updated: August 17, 2026
Application No. 17/957,957

MEMORY ARRAY COMPRISING A FERROELECTRIC DATA STORAGE ELEMENT

Non-Final OA §102
Filed
Sep 30, 2022
Examiner
LUU, PHO M
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
97%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 97% — above average
97%
Career Allowance Rate
1414 granted / 1459 resolved
+28.9% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
21 currently pending
Career history
1474
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
6.8%
-33.2% vs TC avg
§102
58.4%
+18.4% vs TC avg
§112
0.5%
-39.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1459 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Status of claim to be treated in this office action: Independent: 1 and 17. b. Claims 1-10 and 17-20 are pending on the application. Response to Election/Restrictions 2. Applicant’s election with traverse of Group I, claims 1-10 and Group III, claims 17-20 filed 12/29/2025 is acknowledged. Claims 17-20 directed to a system. Pursuant to the procedures set forth in MPEP § 821.04(B), claims 1-10, directed to a device of making or using an allowable product, previously withdrawn from consideration as a result of a restriction requirement, claims 1-10 and 17-20 hereby rejoined and fully examined for patentability under 37 CFR 1.104. Because all claims previously withdrawn from consideration under 37 CFR 1.142 have been rejoined, the restriction requirement as set forth in the Office action mailed on 11/06/2025 is hereby withdrawn. In view of the withdrawal of the restriction requirement as to the rejoined inventions, applicant(s) are advised that if any claim presented in a continuation or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claims 11-16 have been cancelled. Claims 3 and 19 has been amendment. Therefore, claims 1-10 and 17-20 are pending on the application. Drawings 3. The drawings were received on 09/30/2022. These drawings are review and accepted by examiner. Information Disclosure Statement 4. Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) Form PTO-1449; filed 09/30/2022. The information disclosed therein was considered. Specification 5. Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc. The abstract of the disclosure is objected to because it uses the phrase “OF THE DICLOSURE”, “Techniques and mechanisms”, “In an embodiment”, “One such layer comprises” and “In another embodiment” in page 35, line 1, line 2, line 3, line 7 and lines 8-9; respectively, which are implied. Correction is required. See MPEP § 608.01(b). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 6. Claims 1-4 and 17-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Noack. (Pub. No.: US 2021/0327901 A1; “Noack”). Regarding to independent claim 1, Noack in Figures 1-7 are directly disclosed a device (a memory device circuit 200, Figures 2-4) comprising: a crossbar memory array (a memory circuit 200 includes a plurality of memory cells 202, Fig. 2A) comprising: a ferroelectric (FE) circuit element (a FE structure 204, Fig. 2A) comprising: a first electrode structure (a first electrode 210-1, Fig. 2A); a first material layer comprising a FE nitride or a FE oxide (the FE structure 204 may include hafnium oxide material, paragraph 0050); and a second electrode structure (a second electrode 210-2, Fig. 2A), wherein the first material layer is between the first electrode structure and the second electrode structure (the first electrode 210-1 and the second electrode disposed in between the FE structure 204, Fig. 2A); a bit line (a control voltage 208 may be a voltage provide to or via a control line of a memory cell circuit 200 or arrangement, e.g. to or via a bit-line, paragraph 0019, Fig. 2A) which extends to one of the first electrode structure or the second electrode structure; a word line (a control voltage 208 may be a voltage provide to or via a control line of a memory cell circuit 200 or arrangement, e.g. to or via a word-line, paragraph 0019, Fig. 2A) which extends to another of the first electrode structure or the second electrode structure; circuitry (a control circuitry 208, Fig. 2A), coupled to the crossbar memory array (the memory circuit 200), which is to apply a voltage across () the FE circuit element (the FE structure 204), wherein based on the voltage (the voltage supply circuit 218, Fig. 2E), the FE circuit (the voltage supply circuit 218 apply the voltage to the FE structure 204, Fig. 2E) element is to transition to a mode of operation as a diode (a decoupling circuit 214 includes a diode 406, Fig. 4A)(see at least in Figures 2-4, paragraph 0071-0139 and the related disclosures). Regarding dependent claim 2, Noack in Figures 1-7 are directly disclosed a device (a memory device circuit 200, Figures 2-4), wherein the first material layer comprises the FE nitride (a ferroelectric structure 204 may include a ferroelectric material, for example, hafnium oxide, paragraph 0072). Regarding dependent claim 3, Noack in Figures 1-7 are directly disclosed a device (a memory device circuit 200, Figures 2-4), wherein the FE nitride comprises: aluminum (Al), scandium (Sc), and nitrogen (N) (a ferroelectric structure 204 may include a ferroelectric material, for example, hafnium oxide, paragraph 0072). Regarding dependent claim 4, Noack in Figures 1-7 are directly disclosed a device (a memory device circuit 200, Figures 2-4), wherein a thickness of one of the first electrode structure or the second electrode structure is in a range of 5 nanometers (nm) to 30 nm, and wherein a thickness of the FE nitride is in a range of 3 nm to 30 nm (for example, the ferroelectric structure 204 may include a ferroelectric layer or may be a ferroelectric layer having a thickness of about 5 nm, 10 nm or 50 nm, paragraph 0072). Regarding to independent claim 17, Noack in Figures 1-7 are directly disclosed a system (a memory device circuit 200, Figures 2-4) comprising: a microprocessor (inherence/obvious that memory device includes a microprocessor of execute in the device, Fig. 2A) comprising circuitry to execute an instruction; a memory device (a memory circuit 200) coupled to the microprocessor, the memory device comprising: a crossbar memory array (a memory circuit 200 includes a plurality of memory cells 202, Fig. 2A) comprising: a ferroelectric (FE) circuit element (a FE structure 204, Fig. 2A) comprising: a first electrode structure (a first electrode 210-1, Fig. 2A); a first material layer comprising a FE nitride or a FE oxide (the FE structure 204 may include hafnium oxide material, paragraph 0050); and a second electrode structure (a second electrode 210-2, Fig. 2A), wherein the first material layer is between the first electrode structure and the second electrode structure (the first electrode 210-1 and the second electrode disposed in between the FE structure 204, Fig. 2A); a bit line (a bit line such as inherence/obvious in memory, Fig. 2A) which extends to one of the first electrode structure or the second electrode structure (a bit line inherence coupled to the memory circuit 200); a word line (a word line such as inherence/obvious in memory, Fig. 2A) which extends to another of the first electrode structure or the second electrode structure (a bit line inherence coupled to the memory circuit 200); circuitry (a control circuitry 208, Fig. 2A), coupled to the crossbar memory array (the memory circuit 200), which is to apply a voltage across () the FE circuit element (the FE structure 204), wherein based on the voltage (the voltage supply circuit 218, Fig. 2E), the FE circuit (the voltage supply circuit 218 apply the voltage to the FE structure 204, Fig. 2E) element is to transition to a mode of operation as a diode (a decoupling circuit 214 includes a diode 406, Fig. 4A)( see at least in Figures 2-4, paragraph 0071-0139 and the related disclosures). Regarding dependent claim 18, Noack in Figures 1-7 are directly disclosed a device (a memory device circuit 200, Figures 2-4), wherein the first material layer comprises the FE nitride (a ferroelectric structure 204 may include a ferroelectric material, for example, hafnium oxide, paragraph 0072). Regarding dependent claim 19, Noack in Figures 1-7 are directly disclosed a device (a memory device circuit 200, Figures 2-4), wherein the FE nitride comprises: aluminum (Al), scandium (Sc), and nitrogen (N) (a ferroelectric structure 204 may include a ferroelectric material, for example, hafnium oxide, paragraph 0072). Allowable Subject Matter 7. Claims 5-10 and 20, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations. With respected to dependent claims 5-6, the prior art fails to tech or suggest the claimed limitations, namely, the FE circuit element further comprising a layer of a dielectric between the first material layer and the first electrode structure, wherein the dielectric comprises oxygen (O), and one of ruthenium (Ru), iridium (Ir), aluminum (Al), titanium (Ti), indium (In), gallium (Ga), zinc (Zn), tantalum (Ta), lanthanum (La), or sodium (Na). With respected to dependent claims 7-10, the prior art fails to tech or suggest the claimed limitations, namely, the first material layer comprises the FE oxide, and wherein the first electrode structure comprises a metal, the FE circuit element further comprising: a layer of an oxide semiconductor between the first material layer and the first electrode structure, wherein: the FE oxide comprises hafnium (Hf), oxygen (O), and one of silicon (Si), germanium (Ge), nitrogen (N), aluminum (Al), yttrium (Y), gadolinium (Gd), or lanthanum (La); and the oxide semiconductor comprises oxygen (O), and one of indium (In), gallium (Ga), zinc (Zn), tungsten (W), strontium (Sr), or titanium (Ti), the FE circuit element comprising a layer of a dielectric between the first material layer and the second electrode structure, wherein the dielectric comprises oxygen (O), and one of ruthenium (Ru), iridium (Ir), aluminum (Al), titanium (Ti), indium (In), gallium (Ga), zinc (Zn), tantalum (Ta), lanthanum (La), or sodium (Na). With respected to dependent claim 20, the prior art fails to tech or suggest the claimed limitations, namely, the first material layer comprises the FE oxide, and wherein the first electrode structure comprises a metal, the FE circuit element further comprising: a layer of an oxide semiconductor between the first material layer and the first electrode structure. Conclusion Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Higuchi et al (US. 6,737,690 B2) discloses ferroelectric memory and electronic apparatus. Jacob et al (US. 11,101,274 B2) discloses ferroelectric capacitor, a ferroelectric memory cell, an array of ferroelectric memory cell and method of forming a ferroelectric capacitor. When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)). Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is 571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /Pho M Luu/ Primary Examiner, Art Unit 2824. 571-272-1876. Miner.Luu@uspto.gov
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Prosecution Timeline

Sep 30, 2022
Application Filed
May 08, 2023
Response after Non-Final Action
Jul 14, 2026
Non-Final Rejection mailed — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
97%
Grant Probability
99%
With Interview (+3.3%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1459 resolved cases by this examiner. Grant probability derived from career allowance rate.

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