Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 10-14 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anantaraman et al., US PGPub 2015/0378919.
With respect to claim 1, Anantaraman teaches an apparatus comprising:
a memory configured as a memory hierarchy with multiple levels, the memory comprising a first memory having a first level in the memory hierarchy and a second memory having a second level in the memory hierarchy, the second level being lower than the first level in the memory hierarchy (par. 41, cache device 310 being the first, higher level, memory, and memory device 360 being the second, lower level, memory); and
a push-based prefetcher in communication with the memory (par. 53, the prefetch servicing engine), the push-based prefetcher comprising logic to:
monitor memory traffic between the first memory and the second memory (par. 53, the servicing engine monitors demand request and prefetch requests); and
based on the monitoring, push a prefetch of data to the first memory from the second memory (par. 61, the prefetch data is returned (pushed) to cache device 310).
With respect to claim 5, Anantaraman teaches the apparatus of claim 1, wherein the push-based prefetcher is positioned at the second level in the memory hierarchy, the second level being lower than the first level in the memory hierarchy (pars. 24-26, and fig. 1, the prefetch servicing engine 142, which corresponds to the prefetch servicing engine 350 of fig. 3, is located at the higher level cache 140, which is farther from the processing cores 110, which as defined by Applicant, is lower in the memory hierarchy).
With respect to claim 10, Anantaraman teaches the apparatus of claim 1, wherein the push-based prefetcher further comprises logic to drop a resource acquisition request responsive to receiving a negative acknowledgement (par. 74, if there is notification that there are no prefetch credits available, the prefetch request is dropped).
With respect to claim 11, Anantaraman teaches the apparatus of claim 1, wherein the push-based prefetcher further comprises logic to drop a resource acquisition request responsive to expiration of a predefined period of time (par. 59, the request is held until it reaches a threshold period of time).
With respect to claim 12, Anantaraman teaches the apparatus of claim 11, wherein the push-based prefetcher further comprises logic to:
send a resource acquisition request to the first memory (par. 57, the request vector);
receive, based on the resource acquisition request, a negative-acknowledgement of resource acquisition (par. 62, the memory controller 340 indicates to the cache controller when it drops a prefetch hint); and
only after receiving the negative-acknowledgement, drop the prefetch responsive to the negative-acknowledgement (par. 62, dropping the prefetch hint).
With respect to claim 13, Anantaraman teaches the apparatus of claim 1, wherein the push-based prefetcher further comprises logic to:
send a resource acquisition request to the first memory (par. 57, the request vector);
acquire data from a data source in the memory hierarchy (par. 59, acquiring the data at point D); and
responsive to acquiring the data from the data source:
if an acknowledgment of the resource acquisition request has been received, send the acquired data to a data target in the first memory (par. 61, sending the data to the cache device 310); and
if an acknowledgement of the resource acquisition request has not been received, independent of receiving a negative-acknowledgement, drop the prefetch (par. 48, if there is a superline miss, indicating that the superline evicted from the cache controller before the prefetch data could return from the memory controller, the prefetch data and request are dropped).
With respect to claim 14, Anantaraman teaches the apparatus of claim 1, wherein the push-based prefetcher further comprises logic to:
acquire data from a source based on a memory directory for the data when the source of the data is at a lower level than the first memory (par. 24, data is first accessed in the lower level cache if available).
With respect to claim 16, Anantaraman teaches the apparatus of claim 1, wherein the push-based prefetcher further comprises logic to: drop prefetch request for data based on a memory directory for the data indicating that the data is already at first memory (par. 43, if the lookup table indicates that the data is already in the cache controller, the prefetch request is dropped).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-4, 15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anantaraman as applied to claim 1 above, in view of Kumar et al., US PGPub 2022/0365879.
With respect to claim 2, Anantaraman teaches the limitations of the parent claim. Anantaraman teaches a plurality of cores associated with caches (pars. 23-25), but fails to specifically teach that each core has a cache. Kumar teaches the apparatus of claim 1, further comprising:
a plurality of cores, each core having a cache (par. 32, each processor core has a core cache), wherein the first memory comprises one of the caches (par. 32, and fig. 2, the core cache 218-1 corresponds to the first memory), the cores are in communication with a shared memory, and the shared memory comprises the second memory (par. 34, the cluster cache 212 corresponds to the second memory).
It would have been obvious to one of ordinary skill in the art, having the teachings of Anantaraman and Kumar before him before the earliest effective filing date, to modify the multilevel cache memory apparatus of Anantaraman with the multilevel cache memory apparatus of Kumar, in order to give each processing core a core cache, as the core cache has the fastest operational speed of all the levels of caches in the memory hierarchy, as taught by Kumar in par. 34.
With respect to claim 3, Anantaraman teaches the limitations of the parent claim. Anantaraman teaches a plurality of cores (pars. 23-25), but fails to specifically teach that each core has a plurality of caches. Kumar teaches the apparatus of claim 1, further comprising a plurality of cores, each core having a plurality of caches, each cache of a core at a different level of the memory hierarchy, wherein one cache of a core comprises the first memory and a second cache of the core comprises the second memory (par. 34 and the associated fig. 2, the Processors 204 corresponding to the plurality of cores, and the core caches 218 and the cluster cache 212 corresponding to the caches at different levels of the memory hierarchy).
It would have been obvious to one of ordinary skill in the art, having the teachings of Anantaraman and Kumar before him before the earliest effective filing date, to modify the multilevel cache memory apparatus of Anantaraman with the multilevel cache memory apparatus of Kumar, in order to give each processing core a core cache, as the core cache has the fastest operational speed of all the levels of caches in the memory hierarchy, as taught by Kumar in par. 34.
With respect to claim 4, Anantaraman and Kumar teach the limitations of the parent claims. Kumar teaches the apparatus of claim 2, wherein the plurality of cores are configured in one or more core complexes, and the push-based prefetcher is separate from the plurality of core complexes (par. 32, the clusters 202 comprising the core complexes, and pars. 24-26 and fig. 1, the prefetch servicing engine 142 is separate from the processing cores 110).
With respect to claim 15, Anantaraman teaches the limitations of the parent claim. Anantaraman teaches a plurality of cores (pars. 23-25), but fails to specifically teach that each core comprises a cache in communication with a shared memory. Kumar teaches the apparatus of claim 1, further comprising a plurality of cores, each core comprising a cache in communications with a shared memory, wherein the cache comprises the first memory and the shared memory comprises the second memory (pars. 32-34, each processor core has a core cache 218, and the cluster cache 212 is the shared second memory) and the push-based prefetcher further comprises logic to:
acquire data from a source based on a memory directory for the data when the source of the data is at any level within another core separate from the core including the first memory (par. 34, acquiring data from the cluster cache).
It would have been obvious to one of ordinary skill in the art, having the teachings of Anantaraman and Kumar before him before the earliest effective filing date, to modify the multilevel cache memory apparatus of Anantaraman with the multilevel cache memory apparatus of Kumar, in order to give each processing core a core cache, as the core cache has the fastest operational speed of all the levels of caches in the memory hierarchy, as taught by Kumar in par. 34.
With respect to claim 17, Anantaraman teaches the limitations of the parent claim. Anantaraman teaches a plurality of cores (pars. 23-25), but fails to specifically teach that each core comprises a cache in communication with a shared memory. Kumar teaches the apparatus of claim 1, further comprising:
a plurality of cores, each core comprising a cache in communications with a shared memory, wherein the first memory comprises one of the caches and the shared memory comprises the second memory (pars. 32-34, each processor core has a core cache 218, and the cluster cache 212 is the shared second memory); and
a cache controller for the first memory, the cache controller comprising logic configured to throttle responses to resource acquisition requests sent from the push-based prefetcher based on prefetcher statistics (par. 38, throttler 216 throttles prefetches in response to monitoring local congestion level).
It would have been obvious to one of ordinary skill in the art, having the teachings of Anantaraman and Kumar before him before the earliest effective filing date, to modify the multilevel cache memory apparatus of Anantaraman with the multilevel cache memory apparatus of Kumar, in order to give each processing core a core cache, as the core cache has the fastest operational speed of all the levels of caches in the memory hierarchy, as taught by Kumar in par. 34.
With respect to claim 18, Anantaraman and Kumar teach the limitations of the parent claims. Anantaraman teaches the apparatus of claim 17, wherein the cache controller further comprises logic to send a negative-acknowledgement to the push-based prefetcher based on the prefetcher statistics independent of availability of resources for the push-based prefetcher (par. 62, the memory controller indicates a prefetch hint is dropped).
With respect to claim 19, Anantaraman teaches the limitations of the parent claim. Anantaraman teaches a plurality of cores (pars. 23-25), but fails to specifically teach that each core comprises a cache in communication with a shared memory. Kumar teaches the apparatus of claim 1, further comprising:
a plurality of cores, each core comprising a cache in communications with a shared memory, wherein the first memory comprises one of the caches and the shared memory comprises the second memory (pars. 32-34, each processor core has a core cache 218, and the cluster cache 212 is the shared second memory); and
a cache controller of the first memory, the cache controller comprising logic configured to send, to the push-based prefetcher, throttling signals based on prefetcher statistics (par. 38, throttler 216 throttles prefetches in response to monitoring local congestion level).
It would have been obvious to one of ordinary skill in the art, having the teachings of Anantaraman and Kumar before him before the earliest effective filing date, to modify the multilevel cache memory apparatus of Anantaraman with the multilevel cache memory apparatus of Kumar, in order to give each processing core a core cache, as the core cache has the fastest operational speed of all the levels of caches in the memory hierarchy, as taught by Kumar in par. 34.
With respect to claim 20, Anantaraman and Kumar teach the limitations of the parent claims. Kumar teaches the apparatus of claim 19, wherein the push-based prefetcher further comprises logic to throttle the sending of resource acquisition requests based on the throttling signals (par. 38, throttling the prefetch requests).
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anantaraman, as applied to claims 1 and 5 above, in view of Moyer, US PGPub 2021/0182214.
With respect to claim 6, Anantaraman teaches all limitations of the parent claims, but fails to teach wherein the push-based prefetcher further comprises logic to send, as part of the push, the prefetch of data acquired from the second memory to the first memory in response to an acknowledgement received from the first memory.
Moyer further teaches the apparatus of claim 5, wherein the push-based prefetcher further comprises logic to send, as part of the push, the prefetch of data acquired from the second memory to the first memory in response to an acknowledgement received from the first memory (pars. 50-51, the prefetched data is stored in step 615 in response to the determination that the prefetch priority is higher than the cache threshold, the acknowledgement of the claim).
It would have been obvious to one of ordinary skill in the art, having the teachings of Anantaraman and Moyer before him before the earliest effective filing date, to modify the memory prefetch system of Anantaraman with the memory prefetch system of Moyer, in order to retain cache lines in memory that are more likely to be access frequently or demanded by higher priority operations, as taught by Moyer in par. 28.
With respect to claim 7, Anantaraman and Moyer teach all limitations of the parent claims. Moyer further teaches the apparatus of claim 6, wherein:
the second memory comprises logic to send a resource acquisition request to the first memory requesting to send the prefetch of data to the first memory (par. 47, the prefetch request is sent from another cache to the cache 300); and
the first memory comprises logic to send the acknowledgment to the second memory in response to the resource acquisition request, wherein the acknowledgement indicates that the first memory comprises available resources for receiving the prefetch of data (par. 50, the cache 300 acknowledges that the data can be accepted).
With respect to claim 8, Anantaraman and Moyer teach all limitations of the parent claims. Moyer further teaches the apparatus of claim 6, wherein the push-based prefetcher further comprises logic to:
send a resource acquisition request to the first memory (par. 47, the prefetch request is sent from another cache to the cache 300);
receive, based on the resource acquisition request, an acknowledgement of resource acquisition (par. 50, the cache 300 acknowledges that the data can be accepted);
acquire data from a data source in the memory hierarchy; and only after receiving the acknowledgement, send the acquired data to a data target in the first memory (par. 50-51, storing the prefetch data in the cache, which occurs after the determination in step 611 that the prefetch priority is higher than the cache threshold).
With respect to claim 9, Anantaraman and Moyer teach all limitations of the parent claims. Anantaraman further teaches the apparatus of claim 8, wherein sending the resource acquisition request occurs in parallel with acquiring the data from the data source (par. 57, the requests are interleaved).
Response to Arguments
Applicant's arguments filed 07/23/2025 have been fully considered but they are not persuasive. With respect to Applicant’s arguments on pages 8-10 regarding what constitutes lower level and higher level memory, while it is true that in the art, sometimes low level caches close to the processor such as L1/L2/L3 caches are sometimes are described as “higher in the memory hierarchy” than main memory and secondary storage, the issue at hand is A) how the Anantaraman reference defines a higher and lower level memory and B) how Applicant defines a higher level and lower level memory. Anantaraman, in par. 24, defines lower level memory as closer to the processing core and higher level memory as further from the processing core: “Memory hierarchy 120 represents multiple levels of a memory or cache system associated with processing core 110. Memory hierarchy 120 includes lower level cache devices that are close to processing core 110, and higher level cache devices that are further from processing core 110.” Applicant, on the other hand, defines higher level as close to the processor, and lower level as farther, as disclosed in par. 10 of the reply “In conventional computer architecture, higher levels of the memory hierarchy are closer to the processor, smaller, and faster, while lower levels are farther, larger and slower.” Thus, when applying Anantaraman to Applicant’s claims, it is only appropriate to map a memory Anantaraman describes as “lower level” to what Applicant describes as “higher level.” On page 11, Applicant points out that Anantaraman states in par. 16 “after fetching the prefetch data, the higher level memory device can push the prefetched data line(s) back to the lower level memory.” As discussed above, given how Applicant has defined higher level as closer to the processor and lower level as farther from the processor, this section of Anantarman discloses pushing data lines to higher level from lower level, using Applicant’s definition. With respect to Applicant’s new limitations of claim 5 and corresponding arguments on pages 12-13, the examiner has clarified how the prefetch servicing engine is the push-based prefetcher of the claims, given the new definition. Applicant argues on pages 14-15, with respect to dependent claim 16, that Moyer discloses an internal decision and not an acknowledgement received from the first memory that is sent back to the push-based prefetcher. However, Moyer in the cited pars. 50-51 discloses monitoring circuity for monitoring utilization of system resources that count occurrences of various events. While the decision may be internal, the monitoring of factors indicates that it receives information, the received information may be considered the acknowledgement of the claim. Applicant argues on pages 15-16, with respect to dependent claim 7, similarly that Moyer only teaches an internal decision. These arguments are unpersuasive for the same reasons as claim 6. Applicant argues on pages 16-17, with respect to dependent claim 8, that Moyer fails to teach “wherein the indication further specifies a threshold of available resources at the first memory.” Claim 8 does not contain this limitation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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/RYAN DARE/Examiner, Art Unit 2136
/KENNETH M LO/Supervisory Patent Examiner, Art Unit 2136