DETAILED ACTION
Claims 1-11 and 21-26 are present for examination.
Claims 1-2, 5-7 and 11 have been amended.
Claims 25-26 have been added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group I (claims 1-11) in the reply filed on 09/22/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/07/2026 and 01/21/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 6-7, 9-11, 21-22 and 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) in view Chaudhuri et al. (US7,007,039).
With respect claim 1, Balachandran et al. teaches a memory interface (see paragraph 23; memory interface) comprising circuitry to:
provide a number of pages with access counts within one or more buckets of a histogram (see Fig. 1 and paragraphs 21 and 32; an access count 206 indicating a number of read accesses to the data unit 202 while the data 202 is in the memory 116 and/or one of the buckets 118.sub.1 . . . 118.sub.n), wherein at least one of the one or more buckets of the histogram is associated with a configured access count range and a number of pages is associated with the access count range (see Fig. 3 and paragraphs 21 and 33; access counts are maintained for the data in the bucket memories so that the bucket memories cache “hotter” data that is more frequently accessed and has higher access counts. In this way, the buckets are associated with threshold access count ranges to store data having access counts maintained by that bucket. Buckets storing hotter, or more frequently accessed data, would have a higher threshold access count range than buckets storing less frequently accessed data); and
adjust the configured access count range of the one or more buckets based on a received command (see Fig. 6, steps 600-614 and paragraphs 21 and 41; wherein threshold access count 308 may comprise an average of the access counts 206 of the data 202 in the bucket 302 (see paragraph 33); and threshold access count 308 for the bucket 400.sub.i may be recalculated (at block 614) as the average of the access counts 206 of the data in the bucket 400.sub.i. (i.e., an operation to recalculate/adjust threshold access count is performed/triggered when an operation to move data from one bucket buffer to another bucket is received/initiated)); and
migrate data associated with the pages associated with the hot bucket of the one or more buckets of the histogram from a first memory device to a second memory device (see paragraph 22; one of multiple buckets 118.sub.1 . . . 118.sub.n comprising distinct regions of physical memory devices. The buckets 118.sub.1 . . . 118.sub.n may each have a bucket buffer 120.sub.1 . . . 120.sub.n to buffer data to aggregate into larger data objects before writing to the associated bucket 118.sub.1 . . . 118.sub.n. Also, in paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308).
Balachandran et al. does not teach adjust the configured access count range of the one or more buckets based on a received command, wherein the adjusted configured access count range is to adjust a range of a hot bucket of the one or more buckets of the histogram.
However, Chaudhuri et al. teaches progressively refining the layout and frequency of the existing buckets. This way, the regions that are more heavily queried will benefit from having more buckets with finer granularity… In step 415 an initial histogram is identified to be updated by the method 400. The initial histogram is a single empty "root bucket" that is expanded based on the results to queries (i.e., a range/size of buckets that are heavily queried are adjusted/expanded) (see column 6, lines 34-41).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. to include to improve to allow buckets to be nested and tunes the histogram to the specific query workload (see Chaudhuri, column 9, lines 49-55).
With respect claim 3, Balachandran et al. teaches wherein the adjusted configured access count range comprises an adjusted access count range size corresponding to a hot access count range (see paragraphs 21 and 41; threshold access count 308 for the bucket 400.sub.i may be recalculated (at block 614) as the average of the access counts 206 of the data in the bucket 400.sub.i. (i.e., threshold access count is recalculated based on access counts)).
With respect claim 4, Balachandran et al. teaches wherein the adjusted configured access count range comprises a decreased access count range corresponding to a hot access count range (see paragraphs 21 and 41; threshold access count 308 for the bucket 400.sub.i may be recalculated (i.e., increased or decreased) as the average of the access counts 206 of the data in the bucket 400.sub.i. (i.e., threshold access count is recalculated based on access counts)).
With respect claim 6, Balachandran et al. teaches wherein the circuitry is to: report merely pages associated with the hot bucket of the one or more buckets of the histogram to a memory manager and count of pages associated with monitored accesses (see paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308 (i.e., hot data is reported/moved)).
With respect claim 7, Balachandran et al. teaches circuitry to: migrate data associated with the pages associated with the hot bucket of the one or more buckets of the histogram to the second memory device with lower access latency and/or bandwidth than the first memory device that stores the data (see paragraph 24; first level memory 116 may comprise a high cost and very low latency device such as a Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), and the buckets 118.sub.1 . . . 118.sub.n may comprise lower level memory devices that are less expensive and have higher latency and higher storage capacity than DRAM. Also, in paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308 (i.e., data is moved from a bucket to the first level memory, the first memory level having a lower latency than the buckets)).
With respect claim 9, Balachandran et al. teaches comprising at least one memory device coupled to the memory interface (see paragraph 23; a local memory interface may be used to communicate with the first level memory device 116, such as for a DRAM, and a storage device interface may be used to communicate with the buckets comprising lower level memory devices, such as Non-Volatile Memory Express (NVME) to communicate with flash memory and SSDs).
With respect claim 10, Balachandran et al. teaches comprising a server coupled to the memory interface (see paragraph 31; cache controller 104 and storage controller 105 implemented in a host node 102 may comprise rack servers or server boxes that communicate over a local network or are implemented on a PCI card and communicate over a bus interface), wherein the server is to access the at least one memory device by the memory interface (see paragraphs 22 and 31; host 102 further includes a storage controller 105 to perform read and write requests with respect to the volumes 108 in the storage 110… storage controller 105 implemented in a host node 102 may comprise rack servers or server boxes that communicate over a local network or are implemented on a PCI card and communicate over a bus interface).
With respect claim 11, Balachandran et al. teaches wherein the memory interface comprises circuitry that is to migrate data associated with the pages associated with the hot bucket of the one or more buckets of the histogram from the first memory device to the second memory device (see paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308 (i.e., data is moved from a bucket to the first level memory)) and wherein the second memory device has a higher bandwidth and/or lower access latency than the memory device that stores the data (see paragraph 24; first level memory 116 may comprise a high cost and very low latency device such as a Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), and the buckets 118.sub.1 . . . 118.sub.n may comprise lower level memory devices that are less expensive and have higher latency and higher storage capacity than DRAM. Also, in paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308 (i.e., data is moved from a bucket to the first level memory, the first memory level having a lower latency than the buckets)).
With respect claim 21, Balachandran et al. teaches wherein: the first memory device comprises one or more of: a network attached memory device, a storage device, a memory device accessed by a device interface, or a far memory device (see paragraph 23; a storage device interface may be used to communicate with the buckets comprising lower level memory devices, such as Non-Volatile Memory Express (NVME) to communicate with flash memory and SSDs. Also, in paragraph 24, buckets 118.sub.1 . . . 118.sub.n may comprise lower level memory devices that are less expensive and have higher latency and higher storage capacity than DRAM, such as non-volatile random access memory (NVRAM)), and
the second memory device comprises one or more of: a cache or a near memory device (see paragraph 24 and 35; first level memory 116 may comprise a high cost and very low latency device such as Static Random Access Memory (SRAM)).
With respect claim 22, Balachandran et al. teaches wherein: the circuitry is to receive a configuration of a threshold level at which a bucket is identified as hot (see paragraphs 21 and 41; buckets are associated with threshold access count ranges to store data having access counts maintained by that bucket…threshold access count 308 for the buckets may be recalculated (at block 614) as the average of the access counts 206 of the data in the buckets (i.e., a new highest/hot threshold value is determined)).
With respect claim 25, Balachandran et al. does not teach wherein the adjust the hot bucket of the one or more buckets of the histogram comprises increase a range of access counts in the hot bucket.
However, Chaudhuri et al. teaches progressively refining the layout and frequency of the existing buckets. This way, the regions that are more heavily queried will benefit from having more buckets with finer granularity… In step 415 an initial histogram is identified to be updated by the method 400. The initial histogram is a single empty "root bucket" that is expanded based on the results to queries (i.e., a range/size of buckets that are heavily queried are adjusted/expanded) (see column 6, lines 34-41).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. to include to improve to allow buckets to be nested and tunes the histogram to the specific query workload (see Chaudhuri, column 9, lines 49-55).
With respect claim 26, Balachandran et al. does not teach wherein the adjust the hot bucket of the one or more buckets of the histogram comprises reduce a range of access counts in the hot bucket.
However, Chaudhuri et al. teaches wherein buckets are allocated where needed the most as indicated by the workload (see column 9, lines 52-55)… shrinking the boundaries of a new bucket (see claim 6).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. to include to improve to allow buckets to be nested and tunes the histogram to the specific query workload (see Chaudhuri, column 9, lines 49-55).
Claim(s) 2 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) and Chaudhuri et al. (US7,007,039) as applied to claim 1 above, and further in view of Jayasena (US2021/0182262).
With respect claim 2, Balachandran et al. and Chaudhuri et al. do not teach wherein a processor-executed driver or state machine circuitry is to provide the command.
However, Jayasena et al. teaches hash table logic further includes a slot access counter structure that produces tracking data that represents a number of times each slot in a bucket within the first set of frequently-accessed buckets of the hash table and the second set of less frequently-accessed buckets of the hash table have been accessed. In certain implementations, the hash table logic moves an entry from the second set of less frequently-accessed buckets to the first set of frequently-accessed buckets and vice versa based on the tracking data (see paragraph 25) … the hash table logic is implemented as discrete logic, one or more state machines (see paragraph 31).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to can improve latency (see Jayasena, paragraph 45).
With respect claim 24, Balachandran et al. and Chaudhuri et al. do not teach wherein: the circuitry is to access entries in counters based on a hash of device physical address (DPA).
However, Jayasena et al. teaches a subset of mapping hash functions which can be referred to as frequently-accessed (FA) mapping functions, are biased to map primarily to the frequently-accessed set of buckets in the hash table and the remaining hash functions are a subset of mapping hash functions which are biased to map primarily to the less frequently-accessed set of buckets in the hash table (see paragraphs 16-18).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to improve latency (see Jayasena, paragraph 45).
Claim(s) 5 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) and Chaudhuri et al. (US7,007,039) as applied to claim 1 above, and further in view of Wei et al. (US2022/0382477).
With respect claim 5, Balachandran et al. and Chaudhuri et al. do not teach wherein the circuitry is to: adjust a duration of time of determination of the number of pages with access counts within the one or more buckets of a histogram.
However, Wei et al. teaches wherein records 42 include metrics such as a bucket or container name, an access date, and an access counter. Access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a given period, e.g., in a sequential period such as on consecutive days. In particular cases, access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a period (e.g., in a day). In these cases, for a given record 42, the access activity monitor 30 can update the access counter (FIG. 5) for individual access activities for the data object 38 within the period (see paragraph 73) … In some cases, the given period is a daily period such as an approximately 24-hour period (i.e., given period may be adjusted) (see paragraph 39).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to significantly reduce latency in data object retrieval, as well as reduce consumption of storage resources (see Wei, paragraph 29).
With respect claim 23, Balachandran et al. and Chaudhuri et al. do not teach wherein: the circuitry is to receive a configuration of a time interval of access count range.
However, Wei et al. teaches wherein records 42 include metrics such as a bucket or container name, an access date, and an access counter. Access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a given period, e.g., in a sequential period such as on consecutive days. In particular cases, access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a period (e.g., in a day). In these cases, for a given record 42, the access activity monitor 30 can update the access counter (FIG. 5) for individual access activities for the data object 38 within the period (see paragraph 73) … In some cases, the given period is a daily period such as an approximately 24-hour period (i.e., given period may be adjusted) (see paragraph 39).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to significantly reduce latency in data object retrieval, as well as reduce consumption of storage resources (see Wei, paragraph 29).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) and Chaudhuri et al. (US7,007,039) as applied to claim 1 above, and further in view of Hsu et al. (US2022/0164118).
With respect claim 8, Balachandran et al. and Chaudhuri et al. do not teach wherein the memory interface is to provide access to a memory device in a manner consistent at least with Compute Express Link (CXL).
However, Hsu et al. teaches wherein the pooled memory devices may be limited based on a number of upstream ports or a CXL bus interface between the memory controller systems and the corresponding computing nodes (see paragraphs 105 and 125).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to improve performance of the apparatus (see Hsu, paragraphs 44 and 106).
Response to Arguments
Applicant's arguments with respect to claims 1-11 and 21-26 have been considered but are moot in view of the new ground(s) of rejection, necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139
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