CTNF 17/958,223 CTNF 90435 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim s 1 and 18 is objected to because of the following informalities: line 16 of claim 1, “… the result of the probabilistic data structure ,”, has an extra space before a comma. Regrading claim 18, the limitation recited “ return the common data pattern to the particular device ” appears to have a typographical error as “ a particular device ” has not been introduced yet . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3, 5-8, 15-17, and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Doshi et al. (US2021/0117249), hereinafter Doshi in view of Seningen et al. (US 2019/0095339), hereinafter Seningen, and further in view of Gheith et al. (US 2015/0127767), hereinafter Gheith and Susairaj et al. (US 2023/0021672), hereinafter Susairaj . Regarding claim 1 , Doshi teaches an apparatus comprising: a set of first ports to couple to a set of devices in a first computing node (Doshi, [0061], A pod can include a set of rows 200, 210, 220, 230 of racks 240. Each rack 240 may house multiple nodes … The pod switch 250 includes a set of ports 252 to which the nodes of the racks of the pod 110 are connected; [0077]); a second port to couple to a second computing node (Doshi, [0061]; [0063], node 400 … is configured to be mounted in a corresponding rack 240 of the data center 100; [0063]; [0065], node 400 is embodied as a storage node; [0077], NIC; [0085], the storage node 700 may also include … interconnect) , wherein the second computing node hosts a memory resource and the memory resource is to be included in a memory pool (Doshi, [0086], The memory node 800 is configured to provide other nodes 400 … with access to a pool of memory (e.g., in two or more sets 830, 832 of memory devices 420) local to the storage node 700) , wherein the memory pool allows access to the memory resource by remote computing nodes (Doshi, [0086], a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800 ) ; circuitry to: identify a first request by a particular device in the set of devices to access a first line of memory in the memory resource, wherein the first line is associated with a first address (Doshi, [0077]; [0084], The storage controllers 420 may be … controlling the storage and retrieval of data into the data storage 750 based on requests received via the communication circuit 530; [0086], a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800 using a logical address space that maps to physical addresses in the memory sets 830, 832); determine that the first address corresponds to a particular memory region in the memory pool; provide the first address as an input to a probabilistic data structure based on the first request directed to the particular memory region, wherein the probabilistic data structure is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the probabilistic data structure, wherein the result of the probabilistic data structure indicates that the first line of memory comprises the common data pattern . Doshi does not explicitly teach determine that the first address corresponds to a particular memory region in the memory pool; provide the first address as an input to a probabilistic data structure based on the first request directed to the particular memory region, wherein the probabilistic data structure is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the probabilistic data structure, wherein the result of the probabilistic data structure indicates that the first line of memory comprises the common data pattern, as claimed. However, Doshi in view of Seningen teaches determine that the first address corresponds to a particular memory region in the memory pool (Seningen, [0046], If the memory access operation is a read operation, sparse array circuit may determine if the received address corresponds to a storage location in memory circuit 101 that is storing sparse data; Doshi, [0086], a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have been modified Doshi to incorporate teachings of Seningen to determine if a storage location corresponding to a memory address of a read command is a region storing sparse data. A person of ordinary skill in the art would have been motivated to combine the teachings of Doshi with Seningen because it improves efficiency and performance of the storage system disclosed in Doshi by halting completion of a complete read operation in response to determining the read operation is directed to a sparse data, which reducing power dissipated by the storage system (Seningen, [0046]). The combination of Doshi does not explicitly teach provide the first address as an input to a probabilistic data structure based on the first request directed to the particular memory region, wherein the probabilistic data structure is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the probabilistic data structure, wherein the result of the probabilistic data structure indicates that the first line of memory comprises the common data pattern, as claimed. However, the combination of Doshi in view of Gheith teaches provide the first address as an input to a probabilistic data structure based on the first request directed to the particular memory region (Seningen, [0046], If the memory access operation is a read operation, sparse array circuit may determine if the received address corresponds to a storage location in memory circuit 101 that is storing sparse data; Gheith, [0082], If the virtual address has a matching large page address in the TLB ("Yes" path of block 608), the architecture further determines a Bloom filter response as to the requested part of the large page;). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Gheith to provide a memory address as an input to a bloom filter after determining the memory address is directed to a particular memory region (such as a sparse data region in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Gheith because it improves reliability of the storage system disclosed in the combination of Doshi by using different techniques to perform multiple related determination operations for a more reliable result. The combination of Doshi does not explicitly teach wherein the probabilistic data structure is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the probabilistic data structure, wherein the result of the probabilistic data structure indicates that the first line of memory comprises the common data pattern, as claimed. However, the combination of Doshi in view of Susairaj teaches wherein the probabilistic data structure is to generate a result to identify whether the first line of memory comprises a common data pattern (Seningen, [0037], a particular memory, or portion of a memory may store values that have a particular default value. Such data, which is often a logical-0 or null, is commonly referred to as sparse data; Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse) ; and return the common data pattern to the particular device as a response to the first request based on the result of the probabilistic data structure (Seningen [0006], in response to determining that the address matches a particular entry, generate first and second control signals. The memory circuit may disable the read operation based on the first control signal, and a data control circuit may be configured to transmit the sparse data pattern on a bus coupled to the memory based on the second control signal; [0044], During read operations, data control circuit 103 may be configured to transmit the sparse data pattern to a destination via data bus 105) , wherein the result of the probabilistic data structure indicates that the first line of memory comprises the common data pattern (Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Susairaj to generate a signal in response to determining that a first memory block contains a sparse data by using a bloom filter, as the sparse data exhibits a particular data pattern (as indicated in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Susairaj because it improves efficiency and performance of the storage system disclosed in the combination of Doshi by identifying sparse data blocks using a bloom filter. Regarding claim 14 , Doshi teaches a method comprising: receiving a request, at a first network processing device of a first platform (Doshi, [0077], The compute node 500 also includes a communication circuit 530. The illustrative communication circuit 530 includes a network interface controller (NIC) 532, which may also be referred to as a host fabric interface (HFI). The NIC 532 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by the compute node 500 to connect with another compute device (e.g., with other nodes 400); [0139], platform; Fig.2) , wherein the request is received from a first process executed on the first platform and is directed to a particular address (Doshi, [0077]; [0084], The storage controllers 420 may be … controlling the storage and retrieval of data into the data storage 750 based on requests received via the communication circuit 530; [0086], a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800 using a logical address space that maps to physical addresses in the memory sets 830, 832) ; determining that the particular address references a line of memory associated with a sparse memory region defined in a memory pool, wherein the sparse memory region is physically hosted on a second platform; providing the particular address as an input to a Bloom filter corresponding to the sparse memory region based on determining that the particular address references the sparse memory region; determining from the output of the Bloom filter that the line of memory pool comprises a common data pattern; and returning the common data pattern, from the first network processing device to the first process, as a response to the request, without forwarding the request to the second platform. Doshi does not explicitly teach determining that the particular address references a line of memory associated with a sparse memory region defined in a memory pool, wherein the sparse memory region is physically hosted on a second platform; providing the particular address as an input to a Bloom filter corresponding to the sparse memory region based on determining that the particular address references the sparse memory region; determining from the output of the Bloom filter that the line of memory pool comprises a common data pattern; and returning the common data pattern, from the first network processing device to the first process, as a response to the request, without forwarding the request to the second platform, as claimed. However, Doshi in view of Seningen teaches determine that the particular address references a line of memory associated with a sparse memory region defined in a memory (Seningen, [0046], If the memory access operation is a read operation, sparse array circuit may determine if the received address corresponds to a storage location in memory circuit 101 that is storing sparse data; [0060]; Doshi, [0086], The memory node 800 is configured to provide other nodes 400 … with access to a pool of memory (e.g., in two or more sets 830, 832 of memory devices 420) local to the storage node 700); wherein the sparse memory region is physically hosted on a second platform (Doshi, [0061]; [0063], node 400 … is configured to be mounted in a corresponding rack 240 of the data center 100; [0065], node 400 is embodied as a storage node; Fig.2); returning the common data pattern, from the first network processing device to the first process, as a response to the request, without forwarding the request to the second platform (Seningen [0006], in response to determining that the address matches a particular entry, generate first and second control signals. The memory circuit may disable the read operation based on the first control signal, and a data control circuit may be configured to transmit the sparse data pattern on a bus coupled to the memory based on the second control signal; [0044], During read operations, data control circuit 103 may be configured to transmit the sparse data pattern to a destination via data bus 105) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have been modified Doshi to incorporate teachings of Seningen to determine if a storage location corresponding to a memory address is storing sparse data and returning sparse data pattern to a requestor without completing the read operation received from the requestor. A person of ordinary skill in the art would have been motivated to combine the teachings of Doshi with Seningen because it improves efficiency and performance of the storage system disclosed in Doshi by halting completion of a complete read operation in response to determining the read operation is directed to a sparse data, which reducing power dissipated by the storage system (Seningen, [0046]). The combination of Doshi does not explicitly teach providing the particular address as an input to a Bloom filter corresponding to the sparse memory region based on determining that the particular address references the sparse memory region; determining from the output of the Bloom filter that the line of memory pool comprises a common data pattern, as claimed. However, the combination of Doshi in view of Gheith teaches providing the particular address as an input to a Bloom filter corresponding to the sparse memory region based on determining that the particular address references the sparse memory region (Seningen, [0046], If the memory access operation is a read operation, sparse array circuit may determine if the received address corresponds to a storage location in memory circuit 101 that is storing sparse data; Gheith, [0082], If the virtual address has a matching large page address in the TLB ("Yes" path of block 608), the architecture further determines a Bloom filter response as to the requested part of the large page). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Gheith to provide a memory address as an input to a bloom filter after determining the memory address is directed to a particular memory region (such as a sparse data region in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Gheith because it improves reliability of the storage system disclosed in the combination of Doshi by using different techniques to perform multiple related determination operations for a more reliable result. The combination of Doshi does not explicitly teach determining from the output of the Bloom filter that the line of memory pool comprises a common data pattern, as claimed. However, the combination of Doshi in view of Susairaj teaches determining from the output of the Bloom filter that the line of memory pool comprises a common data pattern (Seningen, [0037], a particular memory, or portion of a memory may store values that have a particular default value. Such data, which is often a logical-0 or null, is commonly referred to as sparse data; Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Susairaj to generate a signal in response to determining that a first memory block contains a sparse data by using a bloom filter, as the sparse data exhibits a particular data pattern (as indicated in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Susairaj because it improves efficiency and performance of the storage system disclosed in the combination of Doshi by identifying sparse data blocks using a bloom filter. Regarding claim 18 , Doshi teaches a system comprising: a first node (Doshi, [0063], the node 400 may be embodied as a compute node 500 as discussed below in regard to FIG. 5, an accelerator node 600 as discussed below in regard to FIG. 6, a storage node 700 as discussed below in regard to FIG. 7, or as a node optimized or otherwise configured to perform other specialized tasks, such as a memory node 800,) comprising: a memory (Doshi, [0086], Fig.8, memory set 830, 832) ; a memory controller (Doshi, Fig.8, memory controller 820) ; and a first network processing device (Doshi, [0077], The compute node 500 also includes a communication circuit 530. The illustrative communication circuit 530 includes a network interface controller (NIC) 532; Fig.7, 530) coupled to the memory controller by a first interconnect (Doshi, [0067], I/O sub system 322; Fig.8, I/O Subsystem 622) ; a second node comprising: computing circuitry to execute a process (Doshi, Fig.7, storage controller 720) ; a second network processing device (Doshi, Fig.7, NIC 532) coupled to the first network processing device by a second interconnect (Doshi, [0173], [0174], Media interface 1960 can provide connectivity to a remote smartNIC or another IPU or service via a network medium or fabric.) and coupled to the computing circuitry by a third interconnect (Doshi, Fig.5, I/O subsystem 622) , the second network processing device comprising: a Bloom filter; and circuitry (Doshi, [0077], 532; [0393]; Fig.7, NIC 532) to: identify a first request by the process to access a first line of memory in the memory, wherein the first request references the first line of memory by a first address (Doshi, [0077]; [0084], The storage controllers 420 may be … controlling the storage and retrieval of data into the data storage 750 based on requests received via the communication circuit 530; [0086], a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800 using a logical address space that maps to physical addresses in the memory sets 830, 832) ; determine that the first address corresponds to a sparse memory region in a memory pool; provide the first address as an input to the Bloom filter based on the determination that the first address references the sparse memory region, wherein the Bloom filter is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the Bloom filter, wherein the result of the Bloom filter indicates that the first line of memory comprises the common data pattern . Doshi does not explicitly teach a Bloom filter; determine that the first address corresponds to a sparse memory region in a memory pool; provide the first address as an input to the Bloom filter based on the determination that the first address references the sparse memory region, wherein the Bloom filter is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the Bloom filter, wherein the result of the Bloom filter indicates that the first line of memory comprises the common data pattern, as claimed. However, Doshi in view of Seningen teaches determine that the first address corresponds to a sparse memory region in a memory pool (Seningen, [0046], If the memory access operation is a read operation, sparse array circuit may determine if the received address corresponds to a storage location in memory circuit 101 that is storing sparse data; Doshi, [0086], The memory node 800 is configured to provide other nodes 400 … with access to a pool of memory (e.g., in two or more sets 830, 832 of memory devices 420) local to the storage node 700 … during operation, a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800 using a logical address space that maps to physical addresses in the memory sets 830, 832). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have been modified Doshi to incorporate teachings of Seningen to determine if a storage location corresponding to a memory address is storing sparse data. A person of ordinary skill in the art would have been motivated to combine the teachings of Doshi with Seningen because it improves efficiency and performance of the storage system disclosed in Doshi by halting completion of a complete read operation in response to determining the read operation is directed to a sparse data, which reducing power dissipated by the storage system (Seningen, [0046]). The combination of Doshi does not explicitly teach provide the first address as an input to the Bloom filter based on the determination that the first address references the sparse memory region, wherein the Bloom filter is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the Bloom filter, wherein the result of the Bloom filter indicates that the first line of memory comprises the common data pattern, as claimed. However, the combination of Doshi in view of Gheith teaches a Bloom filter (Gheith, [0033], bloom filter); provide the first address as an input to the Bloom filter based on the determination that the first address references the sparse memory region, (Seningen, [0046], If the memory access operation is a read operation, sparse array circuit may determine if the received address corresponds to a storage location in memory circuit 101 that is storing sparse data; Gheith, [0082], If the virtual address has a matching large page address in the TLB ("Yes" path of block 608), the architecture further determines a Bloom filter response as to the requested part of the large page). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Gheith to provide a memory address as an input to a bloom filter after determining the memory address is directed to a particular memory region (such as a sparse data region in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Gheith because it improves reliability of the storage system disclosed in the combination of Doshi by using different techniques to perform multiple related determination operations for a more reliable result. The combination of Doshi does not explicitly teach wherein the Bloom filter is to generate a result to identify whether the first line of memory comprises a common data pattern; and return the common data pattern to the particular device as a response to the first request based on the result of the Bloom filter, wherein the result of the Bloom filter indicates that the first line of memory comprises the common data pattern, as claimed. However, the combination of Doshi in view of Susairaj teaches a second network processing device comprising: a Bloom filter (Doshi, [0393], Network interface 3700 can include … memory 3710; Susairaj, [0041], the bloom filter is maintained in memory); wherein the Bloom filter is to generate a result to identify whether the first line of memory comprises a common data pattern (Seningen, [0037], a particular memory, or portion of a memory may store values that have a particular default value. Such data, which is often a logical-0 or null, is commonly referred to as sparse data; Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse) ; and return the common data pattern to the particular device as a response to the first request based on the result of the Bloom filter (Seningen [0006], in response to determining that the address matches a particular entry, generate first and second control signals. The memory circuit may disable the read operation based on the first control signal, and a data control circuit may be configured to transmit the sparse data pattern on a bus coupled to the memory based on the second control signal; [0044], During read operations, data control circuit 103 may be configured to transmit the sparse data pattern to a destination via data bus 105) , wherein the result of the Bloom filter indicates that the first line of memory comprises the common data pattern (Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Susairaj to generate a signal in response to determining that a first memory block contains a sparse data by using a bloom filter, as the sparse data exhibits a particular data pattern (as indicated in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Susairaj because it improves efficiency and performance of the storage system disclosed in the combination of Doshi by identifying sparse data blocks using a bloom filter. Regarding claim 2 , the combination of Doshi teaches all the features with respect to claim 1 as outlined above. The combination of Doshi further teaches the apparatus of Claim 1, wherein the probabilistic data structure comprises a Bloom filter (Gheith, [0033], bloom filter; Susairaj, [0034], a bloom filter). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Susairaj to include a bloom filter and to generate a signal in response to determining that a first memory block contains a sparse data by using a bloom filter, as the sparse data exhibits a particular data pattern (as indicated in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Susairaj because it improves efficiency and performance of the storage system disclosed in the combination of Doshi by identifying sparse data blocks using a bloom filter. Regarding claim 3 , the combination of Doshi teaches all the features with respect to claim 1 as outlined above. The combination of Doshi further teaches the apparatus of Claim 1, wherein the first request is not forwarded to the second computing node based on the result of the probabilistic data structure (Seningen, [0006], The sparse array circuit may, in response to determining that the address matches a particular entry, generate first and second control signals. The memory circuit may disable the read operation based on the first control signal, and a data control circuit may be configured to transmit the sparse data pattern on a bus coupled to the memory based on the second control signal). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have been modified Doshi to incorporate teachings of Seningen to determine if a storage location corresponding to a memory address is storing sparse data. A person of ordinary skill in the art would have been motivated to combine the teachings of Doshi with Seningen because it improves efficiency and performance of the storage system disclosed in Doshi by halting completion of a complete read operation in response to determining the read operation is directed to a sparse data, which reducing power dissipated by the storage system (Seningen, [0046]). Regarding claim 5 , the combination of Doshi teaches all the features with respect to claim 1 as outlined above. The combination of Doshi further teaches the apparatus of Claim 1, wherein the particular memory region comprises memory designated as a sparse memory region (Seningen, [0046], If the memory access operation is a read operation, sparse array circuit may determine if the received address corresponds to a storage location in memory circuit 101 that is storing sparse data;) , wherein the probabilistic data structure is used to determine whether the first line of memory comprises the common data pattern based on the association of the first address with the sparse memory region (Seningen, [0037], a particular memory, or portion of a memory may store values that have a particular default value. Such data, which is often a logical-0 or null, is commonly referred to as sparse data; Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse; Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse; Gheith, [0082], If the virtual address has a matching large page address in the TLB ("Yes" path of block 608), the architecture further determines a Bloom filter response as to the requested part of the large page). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Gheith to provide a memory address as an input to a bloom filter after determining the memory address is directed to a particular memory region such as a sparse data region. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Gheith because it improves reliability of the storage system disclosed in the combination of Doshi by using different techniques to perform multiple related determination operations for a more reliable result. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Susairaj to generate a signal in response to determining that a first memory block contains a sparse data by using a bloom filter, as the sparse data exhibits a particular data pattern (as indicated in Seningen). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Susairaj because it improves efficiency and performance of the storage system disclosed in the combination of Doshi by identifying sparse data blocks using a bloom filter. Regarding claim 6 , the combination of Doshi teaches all the features with respect to claim 1 as outlined above. The combination of Doshi further teaches the apparatus of Claim 1, wherein the probabilistic data structure is associated with the particular memory region and the particular memory region is shared by a plurality of devices in the plurality of computing nodes (Doshi, [0086], The memory node 800 is configured to provide other nodes 400 … with access to a pool of memory (e.g., in two or more sets 830, 832 of memory devices 420) local to the storage node 700. For example, during operation, a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800; Seningen, [0046]; Susairaj, [0034]). Regarding claim 7 , the combination of Doshi teaches all the features with respect to claim 6 as outlined above. The combination of Doshi further teaches the apparatus of Claim 6, wherein the circuitry is further to: identify data written to a particular line of memory in the particular memory region; and update the probabilistic data structure based on the data written to the particular line of memory (Susairaj, [0058]; [0059], However, in contrast to the FIG. 7C example, here it is determined that the DBA range does include sparse data at 754. In response to the determination at 754, a lock on the DBA range is implemented at 755 of FIG. 7E. Once the lock has been applied the corresponding blocks are fetched from the data file copies 131 and stored in the corresponding locations in 621a as illustrated at 756 in FIG. 7F. Finally, the bloom filter is updated to indicate that the blocks in the DBA range are not sparse at 757). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Susairaj to identify data written in a region and update a bloom filter with information associated with the region. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Susairaj because it improves efficiency and performance of the storage system disclosed in the combination of Doshi by identifying sparse data blocks using a bloom filter. Regarding claim 8, the combination of Doshi teaches all the features with respect to claim 1 as outlined above. The combination of Doshi further teaches the apparatus of Claim 1, further comprising: a network processing device comprising: a processor (Doshi, [0077], processor; [0393], processors) ; the set of first ports; the second port (Doshi, [0077], Note – network interface card, bus adapter, and switches all comprise ports) ; and the circuitry (Doshi, [0077], The illustrative communication circuit 530 includes a network interface controller (NIC) 532, which may also be referred to as a host fabric interface (HFI). The NIC 532 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by the compute node 500 to connect with another compute device (e.g., with other nodes 400)). Regarding claim 15 , the combination of Doshi teaches all the features with respect to claim 14 as outlined above. The combination of Doshi further teaches the method of Claim 14, further comprising: identifying data written to the sparse memory region; modifying the Bloom filter based on the data written to the sparse memory region (Susairaj, [0058]; [0059], However, in contrast to the FIG. 7C example, here it is determined that the DBA range does include sparse data at 754. In response to the determination at 754, a lock on the DBA range is implemented at 755 of FIG. 7E. Once the lock has been applied the corresponding blocks are fetched from the data file copies 131 and stored in the corresponding locations in 621a as illustrated at 756 in FIG. 7F. Finally, the bloom filter is updated to indicate that the blocks in the DBA range are not sparse at 757). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Susairaj to identify data written in a region and update a bloom filter with information associated with the region. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Susairaj because it improves efficiency and performance of the storage system disclosed in the combination of Doshi by identifying sparse data blocks using a bloom filter. Regarding claim 16, the combination of Doshi teaches all the features with respect to claim 15 as outlined above. The combination of Doshi further teaches the method of Claim 15, wherein the data is written to the sparse memory region by a second process executed on a third platform, and the sparse memory region comprises shared memory (Doshi, [0086], during operation, a compute node 500 or an accelerator node 600 may remotely write to and/or read from one or more of the memory sets 830, 832 of the memory node 800). Regarding claim 17 , the combination of Doshi teaches all the features with respect to claim 14 as outlined above. The combination of Doshi further teaches the method of Claim 14, wherein the memory pool comprises a CXL memory pool (Doshi, [0076], CXL; [0082]; [0086], The memory node 800 is configured to provide other nodes 400 (e.g., compute nodes 500, accelerator nodes 600, etc.) with access to a pool of memory (e.g., in two or more sets 830, 832 of memory devices 420) local to the storage node 700; [0148], network and IO fabrics (PCIe, CXL)). Regarding claim 20 , the combination of Doshi teaches all the features with respect to claim 18 as outlined above. The combination of Doshi further teaches the system of Claim 18, wherein the memory pool is implemented to include memory of a plurality of nodes including the first node, and the second node is permitted access to the memory pool (Doshi, [0076], CXL; [0082]; [0086], The memory node 800 is configured to provide other nodes 400 (e.g., compute nodes 500, accelerator nodes 600, etc.) with access to a pool of memory (e.g., in two or more sets 830, 832 of memory devices 420) local to the storage node 700; [0148], network and IO fabrics (PCIe, CXL)). Regarding claim 21 , the combination of Doshi teaches all the features with respect to claim 18 as outlined above. The combination of Doshi further teaches the system of Claim 18, wherein the first interconnect and the third interconnect are compliant with a CXL-based protocol (Doshi, [0076], the processor-to-processor interconnect 542 may be embodied as … or other high-speed point-to-point interconnect dedicated to processor-to-processor communications (e.g., PCIe or CXL); [0392]). Regarding claim 22 , the combination of Doshi teaches all the features with respect to claim 21 as outlined above. The combination of Doshi further teaches the system of Claim 21, wherein the second interconnect is compliant with a different, non-CXL protocol (Doshi, [0393], Network interface 3700 can include … and bus interface 3712, [0398], Bus interface 3712 can provide an interface with host device (not depicted). For example, bus interface 3712 can be compatible with PCI, PCI Express, PCI-x, Serial ATA, and/or USB compatible interface (although other interconnection standards may be used).) . 07-22-aia AIA Claim (s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Doshi, Seningen, Gheith, and Susairaj as applied to claim 1 above, and further in view of Roberts (US 2017/0364262), hereinafter Roberts . Regarding claim 4 , the combination of Doshi teaches all the features with respect to claim 1 as outlined above. The combination of Doshi further teaches the apparatus of Claim 1, wherein the circuitry is further to: identify a second request to access a second line of memory in the memory resource, wherein the second line is associated with a second address (Doshi, [0077]; [0084], The storage controllers 420 may be … controlling the storage and retrieval of data into the data storage 750 based on requests received via the communication circuit 530; [0086],) ; provide the second address as an input to the probabilistic data structure to generate a second result (Susairaj, [0034], a bloom filter or other index like structure could be maintained to capture an association with a sparse data characteristic and accessed to determine whether a corresponding data file or block is or might be sparse;) ; send the second request to the second computing node based on the second result, wherein the second result does not indicate that the second line of memory comprises the common data pattern (Seningen, [0113], Alternatively, the received address fails to may any entries in sparse array circuit 102, memory circuit 101 may be powered up (block 1108); Once memory circuit 101 has been powered up, the memory read operation may be performed (block 1109).). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have been modified Doshi to incorporate teachings of Seningen to determine if a storage location corresponding to a memory address is storing sparse data and continue performing the read operation is the memory address is not directed to a sparse data region. A person of ordinary skill in the art would have been motivated to combine the teachings of Doshi with Seningen because it improves efficiency and performance of the storage system disclosed in Doshi by halting completion of a complete read operation in response to determining the read operation is directed to a sparse data, which reducing power dissipated by the storage system (Seningen, [0046]). The combination of Doshi does not explicitly teach send the second request to the second computing node based on the second result, as claimed. However, the combination of Doshi in view of Roberts teaches send the second request to the second computing node based on the second result (Roberts, [0049], the memory controller 202 determines whether the Bloom filter 203 returns a match for the read address specified in the read request … If no match is returned by the Bloom filter, then no write entry exists in the write buffer 210 for the requested read address. The memory controller 202 thus issues the read request to the main memory,). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of Roberts to forward a memory access request to a second storage node when it’s determined that a Bloom filter does not include the address of the memory access request. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with Roberts because it improves efficiency and performance of the storage system disclosed in the combination of Doshi to reduce network traffic by filtering out a portion of memory access requests . 07-22-aia AIA Claim (s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Doshi, Seningen, Gheith, and Susairaj as applied to claim 1 above, and further in view of Compute Express Link (CXL) Specification Revision 1.0 (March 2019), hereinafter CXL 1.0 . Regarding claim 9 , the combination of Doshi teaches all the features with respect to claim 1 as outlined above. The combination of Doshi does not explicitly teach the apparatus of Claim 1, wherein the set of first ports are each compatible with a particular interconnect protocol, the particular interconnect protocol comprises a plurality of sub- protocols, and the plurality of sub-protocols may be multiplexed on each of the set of first ports, and the plurality of sub-protocols comprises an 1/0 protocol, a memory protocol, and a cache coherent protocol, as claimed. However, the combination of Doshi in view of CXL 1.0 teaches the apparatus of Claim 1, wherein the set of first ports are each compatible with a particular interconnect protocol (Doshi, [0076], the compute node 500 may also include a processor-to-processor interconnect 542 … the processor-to-processor interconnect 542 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 322). For example, the processor-to-processor interconnect 542 may be embodied as … CLX; [0077], a network interface can include one or more of a network interface controller (NIC) 532, a host fabric interface (HFI), a host bus adapter (HBA), network interface connected to a bus or connection (e.g., PCIe, CXL, DDR, and so forth); [0173]) , the particular interconnect protocol comprises a plurality of sub- protocols, and the plurality of sub-protocols may be multiplexed on each of the set of first ports, and the plurality of sub-protocols comprises an I/O protocol (cxl.io) , a memory protocol (cxl.mem) , and a cache coherent protocol (cxl.cache) (CXL 1.0, page 17, section 1.6, The CXL transaction (protocol) layer is subdivided into logic that handles CXL.io and logic that handles CXL.mem and CXL.cache; page 124, section 5.3, The ARB/MUX is responsible for arbitrating between requests from the CXL link layers and multiplexing the data based on the arbitration results.). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Doshi to incorporate teachings of CXL 1.0 to define sub-protocols in a CXL protocol such as cxl.io, cxl.mem, and cxl.cache. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Doshi with CXL 1.0 because it improves performance of the storage system disclosed in the combination of Doshi by following CXL protocol when the storage system is implemented. Regarding claim 10 , the combination of Doshi teaches all the features with respect to claim 9 as outlined above. The combination of Doshi further teaches the apparatus of Claim 9, wherein the particular interconnect protocol comprises a Compute Express Link (CXL) protocol (Doshi, [0076]; [0077], a network interface can include one or more of a network interface controller (NIC) 532, a host fabric interface (HFI), a host bus adapter (HBA), network interface connected to a bus or connection (e.g., PCIe, CXL, DDR, and so forth); [0173]). Regarding claim 11, the combination of Doshi teaches all the features with respect to claim 10 as outlined above. The combination of Doshi further teaches the apparatus of Claim 10, further comprising: a CXL switch (Doshi, [0061], the s