DETAILED ACTION
This Office Action is in response to the application filed on 30 September 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim(s) 12 is/are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
In regards to claim 12, claim 12 recites the limitations “wherein the wall electrically isolates the first gate metal and the second gate metal from each other.” This appears to be verbatim, the last clause of claim 11, from which claim 11 depends. Therefore, claim 12 does not appear to further limit claim 11.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 11-14, 17, 18, 22, and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guler et al. (US 2022/0093592 A1; hereinafter Guler).
In regards to claim 1, Guler teaches, e.g. in figs. 2, an apparatus comprising:
a first plurality of nanoribbons (annotated fig. 2G: e.g. nanoribbons in first nanoribbon stack), wherein each of the first plurality of nanoribbons are parallel with another of the first plurality of nanoribbons, and wherein the each of the first plurality of nanoribbons are in a first vertical stack (see annotated fig. 2G);
a second plurality of nanoribbons (annotated fig. 2G: e.g. nanoribbons in second nanoribbon stack), wherein each of the second plurality of nanoribbons are parallel with another of the second plurality of nanoribbons, and wherein the each of the second plurality of nanoribbons are in a second vertical stack (see annotated fig. 2G);
a first gate metal (annotated fig. 2G: first gate metal) coupled with the first plurality of nanoribbons, wherein the first gate metal extends at least partially between the each of the first plurality of nanoribbons (see annotated fig. 2G: e.g. first gate metal above nanoribbon stack and in-between nanoribbons in the nanoribbon stack);
a second gate metal (annotated fig. 2G: first gate metal) coupled with the second plurality of nanoribbons, wherein the second gate metal extends at least partially between the each of the second plurality of nanoribbons (see annotated fig. 2G: e.g. first gate metal above nanoribbon stack and in-between nanoribbons in the nanoribbon stack); and
a wall (annotated fig. 2G: wall) with a first side (e.g. the side of wall contacting first nanoribbon stack) and a second side opposite (e.g. the side of wall contacting second nanoribbon stack) the first side, wherein the first side of the wall is physically coupled with the first plurality of nanoribbons and the second side of the wall is physically coupled with the second plurality of nanoribbons, and wherein the wall separates the first gate metal from the second gate metal (see annotated fig. 2G: wall separates both nanoribbon stacks, including their respective intervening gate metals).
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Annotated Fig. 2G
In regards to claim 2, Guler teaches the limitations discussed above in addressing claim 1. Guler further teaches the limitations wherein the first gate metal extends below a bottom nanoribbon of the first plurality of nanoribbons and wherein the first gate metal extends above a top nanoribbon of the first plurality of nanoribbons (see annotated fig. 2G: e.g. the first gate metal extends well above the first nanoribbon stack and the first gate metal is the lowest layer of the stack with the first nanoribbons).
In regards to claim 3, Guler teaches the limitations discussed above in addressing claim 1. Guler further teaches the limitations wherein the second gate metal extends below a bottom nanoribbon of the second plurality of nanoribbons and wherein the second gate metal extends above a top nanoribbon of the second plurality of nanoribbons (see annotated fig. 2G: e.g. the first gate metal extends well above the first nanoribbon stack and the first gate metal is the lowest layer of the stack with the first nanoribbons).
In regards to claim 4, Guler teaches the limitations discussed above in addressing claim 1. Guler further teaches the limitations wherein the wall has a first edge and a second edge opposite the first edge, and wherein the first edge of the wall is below a bottom nanoribbon of the first plurality of nanoribbons and below a bottom nanoribbon of the second plurality of nanoribbons, and wherein the second edge of the wall is at or above a top of the first gate metal and at or above a top of the second gate metal (see annotated fig. 2G: e.g. the top edge of the wall is at a level above the top nanoribbons of the nanoribbon stacks and the bottom of the wall is about parallel with the bottom surface of the bottom gate metal layers, which is below the bottom nanoribbons of the nanoribbon stacks).
In regards to claim 5, Guler teaches the limitations discussed above in addressing claim 1. Guler further teaches the limitations further comprising a layer of insulation above the first gate metal and above the second gate metal, wherein second edge of the wall extends through the layer of insulation (figs. 2F and 2G: (222) is over portions, i.e. partial over, the first and second gate metals and (228) is exposed in an opening of, i.e. extends through, (222)).
In regards to claim 6, Guler teaches the limitations discussed above in addressing claim 1. Guler further teaches the limitations wherein the wall electrically isolates the first gate metal and the second gate metal from each other ([0038]; see annotated fig. 2G: the wall is dielectric and separates the first gate metal from the second gate metal).
In regards to claim 7, Guler teaches the limitations discussed above in addressing claim 1. Guler further teaches the limitations wherein the wall includes a layer, wherein the layer includes a dielectric [0038].
In regards to claim 11, Guler teaches, e.g. in figs. 2, a semiconductor device comprising:
a first stack of a first plurality of nanoribbons (annotated fig. 2G: e.g. nanoribbons in first nanoribbon stack);
a second stack of a second plurality of nanoribbons (annotated fig. 2G: e.g. nanoribbons in second nanoribbon stack);
a third stack of a third plurality of nanoribbons (fig. 2G: e.g. nanoribbons in a third nanoribbon stack to the right or left of the stack depicted in annotated in fig. 2G);
a wall (annotated fig. 2G: wall) with a first side (e.g. the side of wall contacting first nanoribbon stack) and a second side opposite the first side (e.g. the side of wall contacting second nanoribbon stack), wherein the first side of the wall is physically coupled with the first stack of the first plurality of nanoribbons and the second side of the wall is physically coupled with the second stack of the second plurality of nanoribbons (see annotated fig. 2G: wall separates both nanoribbon stacks, including their respective intervening gate metals);
a first gate metal (annotated fig. 2G: first gate metal) coupled with the first stack of the first plurality of nanoribbons, wherein the first gate metal extends at least partially between each of the first plurality of nanoribbons (see annotated fig. 2G: e.g. first gate metal above nanoribbon stack and in-between nanoribbons in the nanoribbon stack);
a second gate metal coupled with the second stack of the second plurality of nanoribbons (annotated fig. 2G: first gate metal) and coupled with the third stack of the third plurality of nanoribbons (rear side stack in fig. 2F: fig. 2F depicts gate metal (212) connecting to a split nanoribbon stack in the "front" of a device (also depicted in fig. 2G), and also (212) connecting to a nanoribbon stack in the "rear" (off-axis) of the device), wherein the second gate metal extends at least partially between each of the second plurality of nanoribbons and extends at least partially between each of the third plurality of nanoribbons (figs. 2F-2G); and
wherein the wall electrically isolates the first gate metal and the second gate metal from each other ([0038]; see annotated fig. 2G: the wall is dielectric and separates the first gate metal from the second gate metal).
In regards to claim 12, Guler teaches the limitations discussed above in addressing claim 11. Guler further teaches the limitations wherein the wall electrically isolates the first gate metal and the second gate metal from each other ([0038]; see annotated fig. 2G: the wall is dielectric and separates the first gate metal from the second gate metal).
In regards to claim 13, Guler teaches the limitations discussed above in addressing claim 11. Guler further teaches the limitations further comprising:
a first epitaxial layer (223) [0037] coupled with a side of the first stack of the first plurality of nanoribbons (figs. 2E-2G);
a second epitaxial layer (223) [0037] coupled with a side of the second stack of the second plurality of nanoribbons (figs. 2E-2G); and
wherein the wall separates the first epitaxial layer from the second epitaxial layer (fig. 2E and annotated fig. 2G).
In regards to claim 14, Guler teaches the limitations discussed above in addressing claim 13. Guler further teaches the limitations wherein the first epitaxial layer or the second epitaxial layer is a selected one of: a source or a drain (fig. 2E: (223); [0037]).
In regards to claim 17, Guler teaches the limitations discussed above in addressing claim 11. Guler further teaches the limitations wherein the wall has a first edge and a second edge opposite the first edge, and wherein the first edge of the wall is below a bottom nanoribbon of the first stack of the first plurality of nanoribbons and below a bottom nanoribbon of the second stack of the second plurality of nanoribbons, and wherein the second edge of the wall is at or above a top of the first gate metal and at or above a top of the second gate metal (see annotated fig. 2G: e.g. the top edge of the wall is at a level above the top nanoribbons of the nanoribbon stacks and the bottom of the wall is about parallel with the bottom surface of the bottom gate metal layers, which is below the bottom nanoribbons of the nanoribbon stacks).
In regards to claim 18, Guler teaches the limitations discussed above in addressing claim 11. Guler further teaches the limitations wherein the wall includes a dielectric material [0038].
In regards to claim 22, Guler teaches, e.g. in figs. 2, a method comprising:
providing a first plurality of nanoribbons (annotated fig. 2G: e.g. nanoribbons in first nanoribbon stack) on a substrate (202) [0034], wherein each of the first plurality of nanoribbons are parallel with another of the first plurality of nanoribbons, and wherein the each of the first plurality of nanoribbons are in a first vertical stack (see annotated fig. 2G);
providing a second plurality of nanoribbons (annotated fig. 2G: e.g. nanoribbons in second nanoribbon stack) on the substrate, wherein each of the second plurality of nanoribbons are parallel with another of the second plurality of nanoribbons, and wherein the each of the second plurality of nanoribbons are in a second vertical stack (see annotated fig. 2G); and
forming a wall (annotated fig. 2G: wall) between the first plurality of nanoribbons and the second plurality of nanoribbons (see annotated fig. 2G: Wall separates both nanoribbon stacks, including their respective intervening gate metals), wherein a first side of the wall is coupled with the first plurality of nanoribbons (e.g. the side of wall contacting first nanoribbon stack), wherein a second side of the wall opposite the first side of the wall is coupled with the second plurality of nanoribbons (e.g. the side of wall contacting second nanoribbon stack), and wherein a bottom of the wall is below the first plurality of nanoribbons and below the second plurality of nanoribbons, and wherein a top of the wall is above the first plurality of nanoribbons and above the second plurality of nanoribbons (see annotated fig. 2G: e.g. the top edge of the wall is at a level above the top nanoribbons of the nanoribbon stacks and the bottom of the wall is about parallel with the bottom surface of the bottom gate metal layers, which is below the bottom nanoribbons of the nanoribbon stacks).
In regards to claim 23, Guler teaches the limitations discussed above in addressing claim 22. Guler further teaches the limitations further comprising:
coupling a first gate metal with the first plurality of nanoribbons, wherein the first gate metal extends at least partially between the each of the first plurality of nanoribbons (see annotated fig. 2G: e.g. first gate metal above nanoribbon stack and in-between nanoribbons in the nanoribbon stack); and
coupling a second gate metal with the second plurality of nanoribbons, wherein the second gate metal extends at least partially between the each of the second plurality of nanoribbons (see annotated fig. 2G: e.g. first gate metal above nanoribbon stack and in-between nanoribbons in the nanoribbon stack), and wherein the wall electrically isolates the first gate metal and the second gate metal from each other (see annotated fig. 2G: wall separates both nanoribbon stacks, including their respective intervening gate metals).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 19, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler as applied to claims 7, 18, and 22 above.
In regards to claim 10, Guler teaches the limitations discussed above in addressing claim 10. Guler appears to be silent as to the limitations wherein the layer of the wall includes a selected one or more of: Hafnium, Aluminum, Titanium, Silicon, Carbon, Nitrogen, or Oxygen; however, Guler teaches the limitations of having a high-k wall material [0100]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the high-k wall material to include elements such as hafnium since hafnium oxide is a high-k material.
In regards to claim 19, Guler teaches the limitations discussed above in addressing claim 18. Guler appears to be silent as to the limitations wherein the layer of the wall includes a selected one or more of: Hafnium, Aluminum, Titanium, Silicon, Carbon, Nitrogen, or Oxygen; however, Guler teaches the limitations of having a high-k wall material [0100]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the high-k wall material to include elements such as hafnium since hafnium oxide is a high-k material.
In regards to claim 25, Guler teaches the limitations discussed above in addressing claim 22. Guler appears to be silent as to the limitations wherein the layer of the wall includes a selected one or more of: Hafnium, Aluminum, Titanium, Silicon, Carbon, Nitrogen, or Oxygen; however, Guler teaches the limitations of having a high-k wall material [0100]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the high-k wall material to include elements such as hafnium since hafnium oxide is a high-k material.
Claim(s) 8, 9, 20, 21, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler as applied to claim(s) 7, 11, and 22 above, and further in view of Ng et al. (US 2022/0359506 A1; hereinafter Ng).
In regards to claim 8, Guler teaches the limitations discussed above in addressing claim 7. Guler appears to be silent as to, but does not preclude, the limitations wherein the layer is a first layer and the dielectric is a first dielectric; and wherein the wall further includes a second layer, and wherein the second layer includes a second dielectric. Ng teaches, e.g. in fig. 2G-5, the limitations wherein the layer is a first layer (150) and the dielectric is a first dielectric [0059]; and wherein the wall (146) further includes a second layer (148), and wherein the second layer includes a second dielectric [0059]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the wall taught by Guler includes the multiple layers taught by Ng to better electrically isolate neighboring segments of a device (Ng [0059]).
In regards to claim 9, the combination of Guler and Ng teaches the limitations discussed above in addressing claim 8. Ng further teaches the limitations wherein the second layer at least partially surrounds the first layer (fig. 2G-5). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the wall taught by Guler includes the multiple layers taught by Ng to better electrically isolate neighboring segments of a device (Ng [0059]).
In regards to claim 20, Guler teaches the limitations discussed above in addressing claim 11. Guler appears to be silent as to, but does not preclude, the limitations wherein the layer is a first layer and the dielectric is a first dielectric; and wherein the wall further includes a second layer, and wherein the second layer includes a second dielectric. Ng teaches, e.g. in fig. 2G-5, the limitations wherein the layer is a first layer (150) and the dielectric is a first dielectric [0059]; and wherein the wall (146) further includes a second layer (148), and wherein the second layer includes a second dielectric [0059]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the wall taught by Guler includes the multiple layers taught by Ng to better electrically isolate neighboring segments of a device (Ng [0059]).
In regards to claim 21, Guler teaches the limitations discussed above in addressing claim 11. Guler appears to be silent as to, but does not preclude, the limitations wherein the second layer at least partially surrounds the first layer. Ng teaches the limitations wherein the second layer at least partially surrounds the first layer (fig. 2G-5). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the wall taught by Guler includes the multiple layers taught by Ng to better electrically isolate neighboring segments of a device (Ng [0059]).
In regards to claim 24, Guler teaches the limitations discussed above in addressing claim 22. Guler appears to be silent as to, but does not preclude, the limitations wherein the layer is a first layer and the dielectric is a first dielectric; and wherein the wall further includes a second layer, and wherein the second layer includes a second dielectric. Ng teaches, e.g. in fig. 2G-5, the limitations wherein the layer is a first layer (150) and the dielectric is a first dielectric [0059]; and wherein the wall (146) further includes a second layer (148), and wherein the second layer includes a second dielectric [0059]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the wall taught by Guler includes the multiple layers taught by Ng to better electrically isolate neighboring segments of a device (Ng [0059]).
Allowable Subject Matter
Claims 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art does not appear to teach the limitations further comprising:
a third epitaxial layer coupled with a side of the third stack of the third plurality of nanoribbons;
a dielectric layer that extends through the second gate metal, the dielectric layer separating the second gate metal into a third gate metal and a fourth gate metal, wherein the third gate metal and the fourth gate metal are electrically isolated from each other; and
wherein the third gate metal extends at least partially between each of the second plurality of nanoribbons, and wherein the fourth gate metal extends at least partially between each of the third plurality of nanoribbons.
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812