DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to amendment filed on 02/23/2026. Claims 2-4 and 11-13 were canceled in this amendment. Claims 1, 5-10, and 14-20 have been examined and are pending in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1, 5-10, and 14-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
A new reference Accapadi et al. US 2012/0096240 is cited in this Office Action necessitated by the amendment.
In view of the new reference, independent claims 1, 10, and 19 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shwartsman et al. US 2016/0070651 (“Shwartsman”) in view of Cathrine et al. US 2023/0385199 (“Cathrine”) and in further view of Accapadi et al. US 2012/0096240 (“Accapadi”).
As per independent claim 1, Shwartsman teaches An apparatus (“Computer system 100” para 0035 and FIG. 1A) comprising:
execution circuitry to execute one or more instructions to access data at a memory address (“Computer system 100 may include a processor 102 that may include one or more execution units 108 to perform an algorithm to perform at least one instruction” para 0035 and FIG. 1A);
a plurality of cache memories (“one or more L1 caches 916 … one or more L2 caches 922 … and an L3 cache 928” para 0081 and FIG. 9), the plurality of cache memories including at least a first cache memory at a first level of a plurality of cache levels (“cache hierarchy may include one or more L1 caches 916 at a lowest level of cache hierarchy 930,” para 0081 and FIG. 9) and at least a second cache memory at a second level of the plurality of cache levels (“cache hierarchy may include … one or more L2 caches 922 at a middle level of cache hierarchy 930,” para 0081 and FIG. 9);
prefetcher circuitry (“cache prefetcher 924 may be implemented by hardware logic” para 0086 and FIG. 9), coupled to the execution circuit (See FIG. 9. “Although cache prefetcher 924 is illustrated within L2 cache 922, cache prefetcher 924 may be implemented in any suitable portion of processor 904.” Para 0085 and FIG. 9), the prefetcher circuitry to prefetch the data from a system memory to at least one of the plurality of cache memories (“Cache prefetcher 924 may initiate retrieval of information from higher levels of cache hierarchy 930 or … memory 934, or other processors 936 while a lower level of cache hierarchy 930 is waiting to add the miss to an LFB [Line Fill Buffer].” Para 0084 and FIG. 9), the prefetcher circuitry including:
a first-level prefetcher to prefetch the data to the first cache memory (“L1 cache 916 may issue a prefetch request to cache prefetcher 924” para 0115 and FIG. 12);
a second-level prefetcher to prefetch the data to the second cache memory (“L2 cache 922 may issue a prefetch request to a cache prefetcher of L3 cache 928” para 0115 and FIG. 12);
a plurality of prefetch filters (“L1 cache 916 may include prefetcher request filter 948. L2 cache 922 may include prefetcher request filter 950.” Para 0094 and FIG. 10), wherein at least a first prefetch filter of the plurality of prefetch filters is to filter exclusively for the first-level prefetcher (“As respective ones of L1 cache 916 and L2 cache 922 make prefetch requests of higher cache levels, an indicator of the request may be stored in prefetcher request filter 948 or prefetcher request filter 950 so that multiple such requests may be suppressed.” Para 0094 and FIG. 10. It is noted that since prefetch requests go to higher level caches or main memory, prefetcher request filter 948 is exclusive for the L1 cache 916).
Shwartsman discloses all of the claim limitations from above, but does not explicitly teach “and at least a second prefetch filter of the plurality of prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher” and “wherein the first-level prefetcher is an instruction pointer prefetcher to determine a stride between successive iterations of an instruction and to prefetch at least one iteration ahead”.
However, in an analogous art in the same field of endeavor, Cathrine teaches and at least a second prefetch filter of the plurality of prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher (“The training inputs can take a variety of forms, but in one example a training input is provided to the history prefetcher whenever processing of a demand access by the cache results in either a cache miss being detected, or a cache prefetch hit (pseudo miss) being detected for a cache line that has been prefetched due to the activities of the history prefetcher 35.” Para 0070).
Given the teaching of Cathrine, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shwartsman with “and at least a second prefetch filter of the plurality of prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher”. The motivation would be that history prefetch circuitry improves the performance of a cache, para 0049 of Cathrine.
Although Shwartsman teaches an “instruction prefetcher”, Shwartsman in combination with Cathrine does not explicitly teach “wherein the first-level prefetcher is an instruction pointer prefetcher to determine a stride between successive iterations of an instruction and to prefetch at least one iteration ahead”.
However, in an analogous art in the same field of endeavor, Accapadi teaches wherein the first-level prefetcher is an instruction pointer prefetcher to determine a stride between successive iterations of an instruction and to prefetch at least one iteration ahead (“compiled application code in a core 202 … signals the cache prefetch engine controller 222 to initiate an instruction prefetch stream request 204, starting with a particular address and stride. … Thereafter, requested stream cache lines are prefetched 234 from the system memory 232 and stored in cache 236.” Para 0032 and FIG. 2).
Given the teaching of Accapadi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shwartsman and Cathrine with “wherein the first-level prefetcher is an instruction pointer prefetcher to determine a stride between successive iterations of an instruction and to prefetch at least one iteration ahead”. The motivation would be that the disclosed invention improves the performance of superscalar architecture, para 0023 of Accapadi.
As per independent claim 10, this claim is rejected based on arguments provided above for similar rejected independent claim 1.
As per independent claim 19, this claim is rejected based on arguments provided above for similar rejected independent claim 1. “Processors 570 and 580 are shown including integrated memory controller units 572 and 582, respectively.” Para 0066 and FIG. 5 of Shwartsman.
As per dependent claim 20, Shwartsman in combination with Cathrine and Accapadi discloses the system of claim 19. Shwartsman teaches further comprising the system memory (“As shown in FIG. 5, IMCs [Integrated Memory Controllers] 572 and 582 may couple the processors to respective memories, namely a memory 532 and a memory 534, which in one embodiment may be portions of main memory locally attached to the respective processors.” Para 0066 and FIG. 5).
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shwartsman in view of Cathrine and in further view of Accapadi and in further view of Karve et al. US 2022/0129385 (“Karve”).
As per dependent claim 5, Shwartsman in combination with Cathrine and Accapadi discloses the apparatus of claim 1. Shwartsman, Cathrine, and Accapadi may not explicitly disclose, but in an analogous art in the same field of endeavor, Karve teaches wherein the first prefetch filter is to filter for the instruction pointer prefetcher based on stride magnitude (“when an address is read, prefetching a set of following addresses can result in a series of cache hits.” Para 0019. Here, the stride magnitude is 1).
Given the teaching of Karve, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shwartsman, Cathrine, and Accapadi with “wherein the first prefetch filter is to filter for the instruction pointer prefetcher based on stride magnitude”. The motivation would be that the disclosure improves performance of instruction and data prefetches, para 0015 of Karve.
As per dependent claim 14, this claim is rejected based on arguments provided above for similar rejected dependent claim 5.
Claims 6-8 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shwartsman in view of Cathrine and in further view of Accapadi and in further view of Meier et al. US 2021/0303471 (“Meier”).
As per dependent claim 6, Shwartsman in combination with Cathrine and Accapadi discloses the apparatus of claim 1. Shwartsman, Cathrine, and Accapadi may not explicitly disclose, but in an analogous art in the same field of endeavor, Meier teaches wherein the second-level prefetcher is an access map pattern matching prefetcher (“the prefetch circuit 20 may be an implementation of an access map/pattern match (AMPM) prefetcher with various enhancements.” Para 0035).
Given the teaching of Meier, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shwartsman, Cathrine, and Accapadi with “wherein the second-level prefetcher is an access map pattern matching prefetcher”. The motivation would be that prefetch traffic may be less bursty and the congestion in memory system may be lower which would make the memory system more efficient, para 0066 of Meier.
As per dependent claim 7, Shwartsman in combination with Cathrine, Accapadi, and Meier discloses the apparatus of claim 6. Shwartsman, Cathrine, and Accapadi may not explicitly disclose, but Meier teaches wherein the second prefetch filter is to provide maps to the access map pattern matching prefetcher (“The filter buffer 48 may transmit accesses to the map memory 40, and if an access is a miss, may retain the access in the filter buffer 48. If a subsequent access to the same access map as the retained access is detected by the filter buffer 48, the map may be allocated to the memory 40 at that point.” Para 0049).
The same motivation that was utilized for combining Shwartsman and Meier as set forth in claim 6 is equally applicable to claim 7.
As per dependent claim 8, Shwartsman in combination with Cathrine and Accapadi discloses the apparatus of claim 1. Shwartsman, Cathrine, and Accapadi may not explicitly disclose, but in an analogous art in the same field of endeavor, Meier teaches wherein the second-level prefetcher is a stream prefetcher (“the secondary prefetch circuits may include … a spatial memory streaming (SMS) prefetch circuit 20C.” Para 0042 and FIG. 2).
Given the teaching of Meier, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shwartsman, Cathrine, and Accapadi with “wherein the second-level prefetcher is a stream prefetcher”. The motivation would be that prefetch traffic may be less bursty and the congestion in memory system may be lower which would make the memory system more efficient, para 0066 of Meier.
As per dependent claims 15-17, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 6-8.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shwartsman in view of Cathrine and in further view of Accapadi and in further view of Meier and in further view of Dodson et al. US 2014/0310478 (“Dodson”).
As per dependent claim 9, Shwartsman in combination with Cathrine, Accapadi, and Meier discloses the apparatus of claim 8. Shwartsman, Cathrine, Accapadi, and Meier may not explicitly disclose, but in an analogous art in the same field of endeavor, Dodson teaches wherein the second prefetch filter is to provide information to the stream prefetcher to determine whether to operate in a full-page mode (“requests that fall within the same memory page so that all such prefetch requests can be made using a page mode access (i.e., while the DRAM page is "open").” Para 0041).
Given the teaching of Dodson, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Shwartsman, Cathrine, Accapadi, and Meier with “wherein the second prefetch filter is to provide information to the stream prefetcher to determine whether to operate in a full-page mode”. The motivation would be that by temporarily increasing a prefetch depth to include a high latency event, para 0054 of Dodson, processor performance is improved.
As per dependent claim 18, this claim is rejected based on arguments provided above for similar rejected dependent claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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