DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed 2/09/2026 in response to PTO Office Action mailed 11/07/2025. The applicant’s remarks and amendments to the claims and/or specification were considered with the results that follow.
In response to last Office Action, claims 1, 3, 8, 10, 17 and 19-27 have been amended. Claims 7 and 18 have been canceled. Claims 28 and 29 have been added. As a result, claims 1-6, 8-17 and 19-29 remain pending in this application.
The objection(s) and/or rejection(s) not repeated in this Office Action have been withdrawn due to the amendments and/or remarks filed by the Applicant on 2/9/26.
Response to Arguments
Applicant's arguments filed 2/09/2026 have been fully considered but they are not persuasive.
The Applicant argues that Rodgers does not teach the architecture which allows two different types of page tables performs page walk as claimed. However, Rogers claim 1 clearly teaches the claimed limitations with two different levels of page tables and page walk as claimed (Rodgers: claim 1: A processor comprising: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level). Thus, the applicant’s arguments are not persuasive and therefore the rejection of the claims are maintained and reiterated below.
Claim Objections
Claim 29 is objected to because of the following informalities:
Claim 29 recites the limitation “wherein the selection of the first or selection base address”; it should be “wherein the selection of the first or second base address”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-17 and 19-28 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Rodgers et al. (US 2020/0310978).
As per claims 1, 10, and 19, Rodgers teaches a processor (par. [0175])/a method (claim 11)/a machine-readable medium (claim 21) comprising:
a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels (par. [0169]: “a first control register is programmed with a first base address and translation mode… the translation mode comprises a 4-level or 5-level translation architecture”; par. [0159]: “control register CR3 1501 stores the base address of a page map level 4 (PML4) table 1502”);
a second control register to store a second base address of a second paging structure associated with a second type of paging having a second number of paging structure levels greater than the first number of paging structure levels (par. [0170]: “a second control register is programmed with a second base address and translation mode”; par. [0160]: “The 5-level paging implementation in FIG. 16 operates in substantially the same manner except that the value in control register CR3 points to a page map level 5 (PML5) table”); and
page walk circuitry to, responsive to an address translation request, select either the first base address from the first control register to perform a page walk over the first paging structure having the first number of paging structure levels or the second base address from the second control register to perform the page walk over the second paging structure having the second number of paging structure levels, the selection based on a characteristic of program code initiating the address translation request (par. [0161]: “the paging translation type may be switched between 4-level and 5-level paging (or any other group of paging types) by a single write to either control register 1310, control register 1320, or both”; pars. [0169] and [0170] teach that the translation mode is selected based on the program characteristic such as supervisor level or user level program; par. [0146]: “For program code executing with a user-level privilege, the address translation circuitry 1280 performs a page walk operation with the user base translation table 1361 identified by the UBTTP”; par. [0173]; claim 1: “a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level”).
As per claims 2, 11, 20, Rodgers teaches wherein the first number of paging structure levels comprises four levels and the second number of paging structure levels comprises five levels (pars. [0169, [0170]).
As per claims 3, 12, 21, Rodgers teaches wherein the page walker circuitry is to switch between using the first paging structure and the second paging structure without disabling paging (par. [0164]: “using these embodiments, paging does not need to be disabled when changing paging algorithms”).
As per claims 4, 13, 22, Rodgers teaches wherein the first paging structure comprises a first base translation table, the page walk circuitry to use a first portion of a first virtual address included in the first address translation request to identify a first entry in the first base translation table (abstract: “address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request”; par. [0176]).
As per claims 5, 14, 23, Rodgers teaches wherein the second paging structure comprises a second base translation table, the page walk circuitry to use a first portion of a second virtual address included in a second address translation request to identify a second entry in the second base translation table without disabling paging between identifying the first entry in the first base translation table and identifying the second entry in the second base translation table (par. [0178]).
As per claims 6, 15, 24, Rodgers teaches wherein the first base translation table comprises a page map level 4 (PML4) table and the second base translation table comprises a page map level 5 (PML5) table (pars. [0159, [0160], [0170]).
As per claims 16 and 25, Rodgers teaches wherein the first entry in the first base translation table comprises a pointer to a first second-level translation table and wherein the second entry in the second base translation table comprises a pointer to a second second-level translation table (par. [0177]).
As per claims 8, 17, 26, Rodgers teaches wherein the page walk circuitry is to a perform a page walk over the first number of paging structure levels to determine a physical address associated with the first virtual address (par. [0146]: “the address translation circuitry 1280 performs a page walk operation”; par. [0147]: “The address translation circuitry 1280 parses the various linear address blocks (LABs) 1381-1385 of the virtual/linear address 1380 to walk the various levels of translation tables 1352-1354 to identify the associated physical address”).
As per claims 9 and 27, Rodgers teaches a translation lookaside buffer (TLB) to store a mapping between the first virtual address and the physical address in an entry of a plurality of TLB entries (par. [0181]).
As per claim 28, Rodgers teaches wherein the page walk circuitry is to perform the page walk over either the first or second paging structure upon execution of a single instruction (par. [0161]: “the paging translation type may be switched between 4-level and 5-level paging (or any other group of paging types) by a single write to either control register 1310, control register 1320, or both”; par. [0164]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Rodgers et al. (US 2020/0310978) as applied to claim 1 above, and further in view of Bryant (US 2021/406194).
As per claim 29, Rodgers fails to teach wherein the selection of the first or second base address corresponds to a setting in a third control register.
Bryant teaches two different types of page tables (four level and five level) and switching between the page tables based on the setting in the third control register (Bryant: par. [0035]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the bit for selecting the different base address to service two page handler to perform that number of walks contemporaneously (Bryant: par. [0026]).
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim T Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138