DETAILED ACTION
Claims 1-6, 22-33 are pending. Claims 7-21 are cancelled.
Priority: 10/1/2022
Assignee: Intel
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-6, 22-27, 28-33 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claims 1, 22, and 28 each recite that the load hit predictor predicts whether the data is stored in the L0 cache “based on a value associated with an instruction pointer of the data and a data structure indexed by values associated with instruction pointers.”
The specification does not describe the recited data as having an instruction pointer, nor does it describe the L0 load hit prediction as being made using an instruction pointer of the data. Instead, in the discussion of the L0 load hit predictor associated with FIG. 27, the specification states that the predictor makes the decision based on the “load’s CEIP” and expressly defines CEIP as a “16-bit compressed (hashed) effective instruction pointer of the load.” The specification further states that the L0 load hit predictor is indexed by bits 7:0 of the load’s CEIP and tagged with bits 11:8.
Thus, the originally filed disclosure describes an instruction-pointer value associated with the load (i.e., the load instruction), rather than an instruction pointer of the data being loaded. No disclosure has been identified that reasonably conveys to one of ordinary skill in the art that the inventors possessed a load hit predictor that predicts L0 residency based on an instruction pointer belonging to, or otherwise being “of,” the data itself.
Accordingly, the limitation “an instruction pointer of the data,” as presently recited in independent claims 1, 22, and 28, is not adequately supported by the originally filed disclosure. Claims 2-6 depend from claim 1, claims 23-27 depend from claim 22, and claims 29-33 depend from claim 28 and therefore include the same unsupported limitation.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-6, 22-27, 28-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claims 1, 22, and 28 recite prediction based on “a value associated with an instruction pointer of the data.” The phrase “instruction pointer of the data” renders the scope of the claims unclear.
In the context of the claims, the “data” is the data indicated by a load operation and potentially stored in the L0 cache. The claims do not define how such data possesses an instruction pointer or what relationship is required for an instruction pointer to be “of” the data. It is therefore unclear whether the limitation refers to: (i) the instruction pointer of the load instruction requesting the data; (ii) an instruction pointer associated with an instruction that generated, stored, or previously accessed the data; or (iii) some other instruction-pointer value associated with the data.
The specification does not resolve this ambiguity. Rather, the relevant disclosure consistently associates the instruction pointer with the load. In particular, the specification states that the L0 load hit predictor makes its prediction based on the “load’s CEIP,” defines CEIP as a compressed effective instruction pointer “of the load,” and indexes the prediction table using bits of the load’s CEIP. This disclosure identifies a technically coherent instruction-pointer value associated with the load instruction, but does not establish what constitutes an “instruction pointer of the data” as presently claimed.
Because the claims recite a relationship between an instruction pointer and the data without defining that relationship, one of ordinary skill in the art cannot determine with reasonable clarity what instruction-pointer value satisfies the limitation or where the boundary of the claimed subject matter lies. Claims 2-6, 23-27, and 29-33 inherit the indefinite limitation through their dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 5-6, 22, 23, 26-27, 28, 29, 32-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataramanan et al.(2014/0025933), and further in view of Wang et al.(20190155750).
As per claim 1, Venkataramanan discloses:
A processor(Venkataramanan, [0032 -- It is noted that the processor 300 may be implemented as the processor 102 shown in FIG. 1.], [0039 -- FIG. 4 is a block diagram of a portion of a processor 400 implementing replay suppression using an early data cache miss indication]) comprising:
a cache subsystem comprising a Level-0 (L0) cache(Venkataramanan, [0039 -- The processor 400 includes a Uop scheduler (SC) block 402, a register file (RF) 404, an address generation unit (AGU) 406, a load/store scheduler 408, a way predictor (WP) 410, and a data cache (DC) 412; i.e cache within processor]);
a scheduler to schedule a load operation indicating data to be loaded(Venkataramanan, [0040 -- Read operands 422 of the Uop 420 are passed to the register file 404 and load/store commands 426 of the Uop 420 are passed to the load/store scheduler 408]);
and a load hit predictor to predict whether the data indicated by the load operation is stored in the L0 cache(Venkataramanan, [0041 -- If the way predictor 410 determines that the desired data is in the data cache 412 (based on the load/store address 428), the way predictor 410 provides a read way signal 432 to the data cache 412; If the way predictor 410 determines that the desired data is not in the data cache]) and to generate a wakeup signal to the scheduler in response to predicting that the data is stored in the L0 cache,(Venkataramanan, [0040 -- The load/store scheduler 408 sends a wakeup dependent operations signal 436 to the Uop scheduler 402 to wake up the operations that are dependent on the Uop 420]);
Venkataramanan does not explicitly disclose the following, however Wang discloses:
wherein the load hit predictor is to predict whether the data is stored in the L0 cache based on a value associated with an instruction pointer of the data and a data structure indexed by values associated with instruction pointers(Wang, [0041 -- An entry in the predictor table may include a prediction result for each of the caches… the update logic is configured to update a prediction result of an entry dependent upon values of the reuse counters], [0049 -- An entry in the prediction table may include a prediction result for each cache of the multi-tier cache], [0080 -- . In the event of a cache miss, the instruction triggering the event is searched in the predictor table and the result 1138 is used to select which cache (if any) the data 1146 should be inserted into.], [0052 -- Predictor table 500 is indexed by an identifier 502 of an instruction, such as instruction pointer (IP); Threshold counter values may be designated to infer cache allocation and determine, for example, when to bypass the cache, insert into the cache with low priority, or insert into the cache with high priority.]).
Therefore it would have been obvious to a person of ordinary skill in the art at the time of filing, to incorporate the features of Wang into the system of Venkataramanan for the benefit of The performance of a central processing unit (CPU) that is enhanced when often used data is available in the cache, and avoiding latency associated with reading data from the backing storage device(Wang, 0001).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Venkataramanan discloses:
wherein, responsive to the wakeup signal, the scheduler is to schedule one or more operations which are dependent on the data(Venkataramanan, [0034 -- When executing a load instruction, if the load data 334 is successfully returned to the LS unit 310, the LS unit 310 sends a wakeup dependent operations signal 340 to the SC block 306 to wake up any operations that are dependent on the load data 334.]).
As per claim 5, the rejection of claim 1 is incorporated, in addition, Venkataramanan discloses:
wherein the load hit predictor to transmit a prediction result to the cache subsystem, the cache subsystem to attempt to read the data from the L0 cache if the prediction is a hit(Venkataramanan, [0041 -- If the way predictor 410 determines that the desired data is in the data cache 412 (based on the load/store address 428), the way predictor 410 provides a read way signal 432 to the data cache 412; The way predictor 410 predicts the way in a given set, where the data is likely to be found in the data cache 412]).
As per claim 6, the rejection of claim 5 is incorporated, in addition, Venkataramanan discloses:
cache subsystem, L0 cache;
Venkataramanan does not explicitly disclose the following, however Wang discloses:
wherein if the data is not stored in the L0 cache, then the data is to be serviced from an L1 cache of the cache subsystem, wherein an indication that the data was not stored in the L0 cache is to be returned(Wang, [0056 -- Following receipt of a read instruction from a cache client at block 702 for a data at a given address, the associated address tag is searched in the highest level (L1) cache at block 704. If the tag is not found (‘misses’) in the cache, as depicted by the negative branch from decision block 706, the entry in predictor table corresponding to the pointer of the read instruction is found and the counter associated with the cache and the instruction pointer is decremented]), the data to be used to train the load hit predictor(Wang, [0057 -- The method shown in FIG. 7, may be performed during a learning or training phase, to update reuse counters for each cache. The counters may then be used in an inference phase to guide cache placement.]).
Therefore it would have been obvious to a person of ordinary skill in the art at the time of filing, to incorporate the features of Wang into the system of Venkataramanan for the benefit of The performance of a central processing unit (CPU) that is enhanced when often used data is available in the cache, and avoiding latency associated with reading data from the backing storage device(Wang, 0001).
Claim 22 recites method limitations corresponding to the processor limitations of claim 1, and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claim 1 likewise teach the corresponding limitations of claim 22.
Claim(s) 23, 26-27 recite method limitations corresponding to the processor limitations of claims 2, 5-6, respectively and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claims 2, 5-6 likewise apply to the corresponding limitations of claims 23, 26-27.
Claim 28 recites CRM limitations corresponding to the processor limitations of claim 1, and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claim 1 likewise teach the corresponding limitations of claim 28.
Claim(s) 29, 32-33 recite method limitations corresponding to the processor limitations of claims 2, 5-6, respectively and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claims 2, 5-6 likewise apply to the corresponding limitations of claims 29, 32-33.
Claims 3, 24, 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataramanan et al.(2014/0025933), in view of Wang et al.(20190155750) and further in view of Chong et al.(2016/0034403).
As per claim 3, the rejection of claim 2 is incorporated, in addition, Venkataramanan discloses:
a load hit predictor, L0 cache;
Venkataramanan, Wang does not explicitly disclose the following, however Chong discloses:
wherein the load hit predictor is to transmit a prediction result to the cache subsystem, the cache subsystem to prevent completion of the load in the L0 cache if the prediction is a miss(Chong, [0019 -- where the memory device is a multi-way set-associative cache, the access control circuitry is configured to receive, as the access kill signal, a way prediction signal indicating a subset of the ways, and the access control circuitry is configured to initiate the access suppression to suppress the access procedure in the subset of was indicated by the way prediction signal], [0038 -- The way prediction generated by way prediction 32 and determining the late kill signal may be an explicit indication of the way in which the requested data item is expected to be stored, in which case the access control circuitry 22 is configured to cause the access procedure already initiated in all the other ways to be suppressed, or the way prediction may be an indication of at least one way in which it is predicted that the requested data item is not stored, in which case the access control circuitry 22 is configured to suppress the access procedure already initiated in those ways.]).
Therefore it would have been obvious to a person of ordinary skill in the art at the time of filing, to incorporate the features of Chong into the system of Venkataramanan, Wang for the benefit of a device that allows a sense amplifier circuitry to require an enable signal to be asserted and to be active, thus coupling the enable signal to fixed voltage to effectively disable the sense amplifier circuitry and prevent dynamic power being expended by operation of the sense amplifier circuitry(Chong, 0011).
Claim 24 recites method limitations corresponding to the processor limitations of claim 3, and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claim 3 likewise teach the corresponding limitations of claim 24.
Claim 30 recites method limitations corresponding to the processor limitations of claim 1, and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claim 1 likewise teach the corresponding limitations of claim 30.
Claim(s) 4, 25, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataramanan et al.(2014/0025933), in view of Wang et al.(20190155750), and further in view of Chong et al.(2016/0034403), and further in view of Yin et al.(10719441)
As per claim 4, the rejection of claim 3 is incorporated, in addition, Venkataramanan discloses:
cache subsystem, L0 cache;
Venkataramanan, Wang in view of Chong does not explicitly disclose the following, however Yin discloses:
wherein if the prediction result is a miss, the cache subsystem is to determine whether the data is stored in the L0 cache and to return an indication that the data was stored in the L0 cache(Yin, [Col. 16 lines 38-42 -- it is assumed that the likelihood of the cache memory access request hitting in the last-level cache memory is low, which in turn indicates that the likelihood is relatively high that the cache memory access request will miss in the cache memory.], [Col. 17 lines 29-33 -- . On the other hand, when a hit occurs while resolving the cache memory access request in the last-level cache memory (step 312), the cache controller responds to the cache memory access request with data from the last-level cache memory (step 318)]), the indication to be used to train the load hit predictor(Yin, [Claim 8 -- wherein the predictor: receives indications of outcomes of a plurality of completed cache memory access requests for data at corresponding addresses in the last-level cache memory; and based on indications of the outcomes, trains a prediction mechanism to determine likelihoods that subsequent cache memory accesses for data at the corresponding addresses will hit in the last-level cache memory.]).
Therefore it would have been obvious to a person of ordinary skill in the art at the time of filing, to incorporate the features of Yin into the system of Venkataramanan, Wang in view of Chong for the benefit of a device that allows a sense amplifier circuitry to require an enable signal to be asserted and to be active, thus coupling the enable signal to fixed voltage to effectively disable the sense amplifier circuitry and prevent dynamic power being expended by operation of the sense amplifier circuitry(Chong, 0011).
Claim 25 recites method limitations corresponding to the processor limitations of claim 4, and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claim 4 likewise teach the corresponding limitations of claim 25.
Claim 31 recites method limitations corresponding to the processor limitations of claim 4, and therefore the teachings of Venkataramanan in view of Wang discussed above with respect to claim 4 likewise teach the corresponding limitations of claim 31.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, 22-33 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Crum et al. US 2014/0181407
The cache accessing method involves storing access information for a first memory access indicating a subset of several ways. One of the subset is accessed by the first memory access. The subset of several ways is determined based on the access information, in response to a second memory access to several of ways. The subset of several ways is prepared for access concurrent with determining a memory address based on the second memory access. The subset of several ways is prepared by pre-charging access lines of bit cells of the subset of several ways(Crum, 0048).
Peir et al. US 2003/0208665
A cache hit/miss prediction value that is associated with identified entry corresponding to memory address, is read from a cache hit/miss prediction table. A dependent instruction is canceled if the prediction value indicates cache miss, and is allowed to proceed if the prediction value indicates cache hit(Peir, 0016).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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