DETAILED ACTION
Claims 1-21 are pending. Claims 7-21 are withdrawn from consideration. Claims 1-6 are elected.
Priority: 10/1/2022
Assignee: Intel
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Venkataramanan et al.(2014/0025933).
As per claim 1, Venkataramanan discloses:
A processor(Venkataramanan, [0032 -- It is noted that the processor 300 may be implemented as the processor 102 shown in FIG. 1.], [0039 -- FIG. 4 is a block diagram of a portion of a processor 400 implementing replay suppression using an early data cache miss indication]) comprising:
a cache subsystem comprising a Level-0(L0) cache(Venkataramanan, [0039 -- The processor 400 includes a Uop scheduler (SC) block 402, a register file (RF) 404, an address generation unit (AGU) 406, a load/store scheduler 408, a way predictor (WP) 410, and a data cache (DC) 412; i.e cache within processor]);
a scheduler to schedule a load operation indicating data to be loaded(Venkataramanan, [0040 -- Read operands 422 of the Uop 420 are passed to the register file 404 and load/store commands 426 of the Uop 420 are passed to the load/store scheduler 408]);
and a load hit predictor to predict whether the data indicated by the load operation is stored in the L0 cache(Venkataramanan, [0041 -- If the way predictor 410 determines that the desired data is in the data cache 412 (based on the load/store address 428), the way predictor 410 provides a read way signal 432 to the data cache 412; If the way predictor 410 determines that the desired data is not in the data cache]) and to generate a wakeup signal to the scheduler in response to predicting that the data is stored in the L0 cache(Venkataramanan, [0040 -- The load/store scheduler 408 sends a wakeup dependent operations signal 436 to the Uop scheduler 402 to wake up the operations that are dependent on the Uop 420]).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Venkataramanan discloses:
wherein, responsive to the wakeup signal, the scheduler is to schedule one or more operations which are dependent on the data(Venkataramanan, [0034 -- When executing a load instruction, if the load data 334 is successfully returned to the LS unit 310, the LS unit 310 sends a wakeup dependent operations signal 340 to the SC block 306 to wake up any operations that are dependent on the load data 334.]).
As per claim 5, the rejection of claim 1 is incorporated, in addition, Venkataramanan discloses:
wherein the load hit predictor to transmit a prediction result to the cache subsystem, the cache subsystem to attempt to read the data from the L0 cache if the prediction is a hit(Venkataramanan, [0041 -- If the way predictor 410 determines that the desired data is in the data cache 412 (based on the load/store address 428), the way predictor 410 provides a read way signal 432 to the data cache 412; The way predictor 410 predicts the way in a given set, where the data is likely to be found in the data cache 412]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataramanan et al.(2014/0025933), and further in view of Chong et al.(2016/0034403).
As per claim 3, the rejection of claim 2 is incorporated, in addition, Venkataramanan discloses:
a load hit predictor, L0 cache;
Venkataramanan does not explicitly disclose the following, however Chong discloses:
wherein the load hit predictor is to transmit a prediction result to the cache subsystem, the cache subsystem to prevent completion of the load in the L0 cache if the prediction is a miss(Chong, [0019 -- where the memory device is a multi-way set-associative cache, the access control circuitry is configured to receive, as the access kill signal, a way prediction signal indicating a subset of the ways, and the access control circuitry is configured to initiate the access suppression to suppress the access procedure in the subset of was indicated by the way prediction signal], [0038 -- The way prediction generated by way prediction 32 and determining the late kill signal may be an explicit indication of the way in which the requested data item is expected to be stored, in which case the access control circuitry 22 is configured to cause the access procedure already initiated in all the other ways to be suppressed, or the way prediction may be an indication of at least one way in which it is predicted that the requested data item is not stored, in which case the access control circuitry 22 is configured to suppress the access procedure already initiated in those ways.]).
Therefore it would have been obvious to a person of ordinary skill in the art at the time of filing, to incorporate the features of Chong into the system of Venkataramanan for the benefit of a device that allows a sense amplifier circuitry to require an enable signal to be asserted and to be active, thus coupling the enable signal to fixed voltage to effectively disable the sense amplifier circuitry and prevent dynamic power being expended by operation of the sense amplifier circuitry(Chong, 0011).
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataramanan et al.(2014/0025933), further in view of Chong et al.(2016/0034403), and further in view of Yin et al.(10719441)
As per claim 4, the rejection of claim 3 is incorporated, in addition, Venkataramanan discloses:
cache subsystem, L0 cache;
Venkataramanan in view of Chong does not explicitly disclose the following, however Yin discloses:
wherein if the prediction result is a miss, the cache subsystem is to determine whether the data is stored in the L0 cache and to return an indication that the data was stored in the L0 cache(Yin, [Col. 16 lines 38-42 -- it is assumed that the likelihood of the cache memory access request hitting in the last-level cache memory is low, which in turn indicates that the likelihood is relatively high that the cache memory access request will miss in the cache memory.], [Col. 17 lines 29-33 -- . On the other hand, when a hit occurs while resolving the cache memory access request in the last-level cache memory (step 312), the cache controller responds to the cache memory access request with data from the last-level cache memory (step 318)]), the indication to be used to train the load hit predictor(Yin, [Claim 8 -- wherein the predictor: receives indications of outcomes of a plurality of completed cache memory access requests for data at corresponding addresses in the last-level cache memory; and based on indications of the outcomes, trains a prediction mechanism to determine likelihoods that subsequent cache memory accesses for data at the corresponding addresses will hit in the last-level cache memory.]).
Therefore it would have been obvious to a person of ordinary skill in the art at the time of filing, to incorporate the features of Yin into the system of Venkataramanan in view of Chong for the benefit of a device that allows a sense amplifier circuitry to require an enable signal to be asserted and to be active, thus coupling the enable signal to fixed voltage to effectively disable the sense amplifier circuitry and prevent dynamic power being expended by operation of the sense amplifier circuitry(Chong, 0011).
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataramanan et al.(20140025933), and further in view of Wang et al.(20190155750).
As per claim 6, the rejection of claim 5 is incorporated, in addition, Venkataramanan discloses:
cache subsystem, L0 cache;
Venkataramanan does not explicitly disclose the following, however Wang discloses:
wherein if the data is not stored in the L0 cache, then the data is to be serviced from an L1 cache of the cache subsystem, wherein an indication that the data was not stored in the L0 cache is to be returned(Wang, [0056 -- Following receipt of a read instruction from a cache client at block 702 for a data at a given address, the associated address tag is searched in the highest level (L1) cache at block 704. If the tag is not found (‘misses’) in the cache, as depicted by the negative branch from decision block 706, the entry in predictor table corresponding to the pointer of the read instruction is found and the counter associated with the cache and the instruction pointer is decremented]), the data to be used to train the load hit predictor(Wang, [0057 -- The method shown in FIG. 7, may be performed during a learning or training phase, to update reuse counters for each cache. The counters may then be used in an inference phase to guide cache placement.]).
Therefore it would have been obvious to a person of ordinary skill in the art at the time of filing, to incorporate the features of Wang into the system of Venkataramanan in view of Chong for the benefit of The performance of a central processing unit (CPU) that is enhanced when often used data is available in the cache, and avoiding latency associated with reading data from the backing storage device(Wang, 0001).
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Crum et al. US 2014/0181407
The cache accessing method involves storing access information for a first memory access indicating a subset of several ways. One of the subset is accessed by the first memory access. The subset of several ways is determined based on the access information, in response to a second memory access to several of ways. The subset of several ways is prepared for access concurrent with determining a memory address based on the second memory access. The subset of several ways is prepared by pre-charging access lines of bit cells of the subset of several ways(Crum, 0048).
Peir et al. US 2003/0208665
A cache hit/miss prediction value that is associated with identified entry corresponding to memory address, is read from a cache hit/miss prediction table. A dependent instruction is canceled if the prediction value indicates cache miss, and is allowed to proceed if the prediction value indicates cache hit(Peir, 0016).
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132