DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/2/2026 has been entered.
This communication is responsive to the request for continued examination filed on 6/2/2026. Claims 1-20 and 22-23 are pending and have been examined. Claim 21 has been canceled. Claim 23 has been added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
4. Claims 1-20 and 22-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
5. Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “An apparatus” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…perform, for a particular data element position of the… data source operands, a comparison of an 8-bit floating point data element at that position…based on the comparison, wherein the 8-bit floating point data element is to utilize a variable exponential bias” which describe a process that under its broadest reasonable interpretation encompasses mathematical calculations/relationships and/or mental processes. That is other than reciting generic computing components (e.g. decoder circuitry to decode instructions, execution circuitry to execute instructions, registers) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses comparing 8-bit floating point operands to obtain a comparison result (see disclosure corresponding to Fig. 14 of applicant’s specification), thus the limitation encompasses mathematical relationship/calculations and mental processes (MPEP 2106.04(a)(2)(I)(A and C) and (III)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation and/or mental process in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within both the “Mathematical concepts” and “Mental processes” groupings of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand, wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands…a flags register…and execution circuitry to execute the decoded instruction according to the opcode.
and update a flags register
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)); the use of packed data operands can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector processing) (MPEP 2106.05(h)) and (b) recites insignificant extra-solution activity (i.e. data outputting) (See MPEP 2106.05 (g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); the use of packed data operands can also be viewed as an attempt to tie the abstract idea to a particular field of use (e.g. vector processing) (MPEP 2106.05(h)). While, (b) recites insignificant extra-solution activity of data outputting (see MPEP 2106.05(g)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
6. Claim 2, dependent upon claim 1, further recites “…wherein the field for the identification of the first source operand is to identify a vector register”, which discloses a particular data source used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data (vector data), e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
7. Claim 3, dependent upon claim 1, further recites “…wherein the field for the identification of the first source operand is to identify a memory location”, which discloses a particular data source used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
8. Claim 4, dependent upon claim 1 further recites “…wherein when the comparison indicates an unordered result, a zero flag, a parity flag, and a carry flag of the flags register are set to 1” which discloses the insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
9. Claim 5, dependent upon claim 1 further recites “…wherein when the comparison indicates the data element of the first source is greater than the data element of the second source, a zero flag, a parity flag, and a carry flag of the flags register are set to 0” which discloses the insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
10. Claim 6, dependent upon claim 1 further recites “…wherein when the comparison indicates the data element of the first source is less than the data element of the second source, a zero flag of the flags register is set to 0, a parity flag of the flags register is set to 0, and a carry flag of the flags register is set to 1” which discloses the insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
11. Claim 7, dependent upon claim 1 further recites “…wherein when the comparison indicates the data element of the first source is equal to the data element of the second source, a carry flag of the flags register is set to 0, a parity flag of the flags register is set to 0, and a zero flag of the flags register is set to 1” which discloses the insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
12. Claim 22, dependent upon claim 15, further recites “…wherein further comprising: translating the single instruction into one or more instructions of a different instruction set architecture, wherein the executing the decoded instruction according to the opcode is the execution of the one or more instructions of the different instruction set architecture”, which ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
13. Claim 23, dependent upon claim 1, further recites “…wherein the variable exponential bias is to be provided by a general-purpose register identified by one or more fields of the single instruction”, which discloses a particular data source used in the abstract idea of in claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data (GPR register data), e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
14. Claims 8 and 15 are similarly rejected on the same basis as claim 1 above.
15. Claims 9-14 and 16-20 are similarly rejected on the same basis as claims 2-7 above.
Claim Rejections - 35 USC § 103
16. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
17. Claim(s) 1-20 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Intel Architecture Instruction Set Extensions Programming Reference (February 2016) (cited on 892 filed on 10/9/2025), hereby referred to as Intel and further in view of Das Sarma, PGPUB No, 2020/0349216.
In regards to claim 1, Intel discloses An apparatus comprising (page 1-1: the described instructions are for execution on an Intel processor) decode circuitry to decode an instance of a single instruction (page 5-970: wherein a UCOMISS instruction contains fields for decoding by circuitry of the processor. Wherein all instructions to be executed in a processor are necessarily decoded by decode circuitry of the processor. note page 3-2 as well, which refers to “instructions to be decoded”) the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand (page 5-970: the instruction includes fields for an opcode and identification of two packed source operands (xmm1, xmm2 or mem32) wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands, a comparison of a floating-point data element at that position, and update a flags register based on the comparison (page 5-970: wherein opcode indicates that an execution circuit of processor is to perform a comparison of the low floating point values of operand 1 and operand 2 and update EFLAGS register based on comparison. Note an opcode necessarily controls execution circuitry of a processor to perform the indicated operation of the instruction. Note pages 2-6 and 2-12, as well which refer to “execute the following instruction” and “fetch and execute of a next instruction”) and the execution circuitry to execute the decoded instruction according to the opcode (page 5-970: the instruction is executed according to the UCOMISS opcode to perform a comparison of data and update a flags register).
Intel does not disclose “an 8-bit floating point data element” nor “wherein the 8-bit floating point data element is to utilize a variable exponential bias”. Intel does disclose performing a comparison instruction as claimed using 32-bit single precision floating-point elements, however the reference does not disclose using 8-bit floating point elements with variable exponential bias.
Das Sarma discloses an 8-bit floating point data element ([0016 and 0048])
wherein the 8-bit floating point data element is to utilize a variable exponential bias ([0015, 0036 and 0048)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the instructions of Intel to use 8-bit floating point operands as the instructions of Das Sarma. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using 8-bit FP values in an instruction) for another (using 32-bit FP values in an instruction) to yield predictable results (an UCOMISS instruction which compares 8-bit FP data) for the benefit of reduced memory usage (e.g. storing values with less bits), increased computational speed and improved energy efficiency (MPEP 2143 Example B). Furthermore, the courts have deemed changes in size/proportion as obvious (e.g. changing a data size of the operand is obvious) (See MPEP 2144.04(IV)(A) (In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955)) (In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984))). Additionally, using 8-bit floating point values with configurable biases can increase data bandwidth and improve precision and accuracy (e.g. by improving range of exponents) of data (Das Sarma [0013, 0015-0016 and 0048]).
Claim 8 is similarly rejected on the same basis as claim 1 above as claim 8 is the system claim corresponding to the apparatus of claim 1 above. (Note: claim 8 includes an additional limitation stating “a memory to store an instance of a single instruction”. Note Intel pages 2-13 and 2-31 to 2-32 discloses an instruction cache and thus a memory for storing instructions is disclosed)
Claim 15 is similarly rejected on the same basis as claim 1 above as claim 15 is the method claim corresponding to the apparatus of claim 1 above.
In regards to claim 2, the combination of Intel and Das Sarma discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the field for the identification of the first source operand is to identify a vector register. (Intel: pages 1-2 and 5-970: wherein XMM1 or XMM2 is a SIMD register)
Claim 9 is similarly rejected on the same basis as claim 2 above as claim 9 is the system claim corresponding to the apparatus of claim 2 above.
Claim 16 is similarly rejected on the same basis as claim 2 above as claim 16 is the method claim corresponding to the apparatus of claim 2 above.
In regards to claim 3, the combination of Intel and Das Sarma discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein the field for the identification of the first source operand is to identify a memory location. (Intel: pages 1-2 and 5-970: wherein XMM2 is a memory location)
Claim 10 is similarly rejected on the same basis as claim 3 above as claim 10 is the system claim corresponding to the apparatus of claim 3 above.
Claim 17 is similarly rejected on the same basis as claim 3 above as claim 17 is the method claim corresponding to the apparatus of claim 3 above.
In regards to claim 4, the combination of Intel and Das Sarma discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein when the comparison indicates an unordered result, a zero flag, a parity flag, and a carry flag of the flags register are set to 1. (Intel: page 5-970: wherein for an unordered result ZF, PF and CF are all set to 1)
Claim 11 is similarly rejected on the same basis as claim 4 above as claim 11 is the system claim corresponding to the apparatus of claim 4 above.
Claim 18 is similarly rejected on the same basis as claim 4 above as claim 18 is the method claim corresponding to the apparatus of claim 4 above.
In regards to claim 5, the combination of Intel and Das Sarma discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein when the comparison indicates the data element of the first source is greater than the data element of the second source, a zero flag, a parity flag, and a carry flag of the flags register are set to 0. (Intel: page 5-970: wherein for a greater than result ZF, PF and CF are all set to 0)
Claim 12 is similarly rejected on the same basis as claim 5 above as claim 12 is the system claim corresponding to the apparatus of claim 5 above.
Claim 19 is similarly rejected on the same basis as claim 5 above as claim 19 is the method claim corresponding to the apparatus of claim 5 above.
In regards to claim 6, the combination of Intel and Das Sarma discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein when the comparison indicates the data element of the first source is less than the data element of the second source, a zero flag of the flags register is set to 0, a parity flag of the flags register is set to 0, and a carry flag of the flags register is set to 1. (Intel: page 5-970: wherein for a less than result ZF, PF and CF are all set to 001 respectively)
Claim 13 is similarly rejected on the same basis as claim 6 above as claim 13 is the system claim corresponding to the apparatus of claim 6 above.
Claim 20 is similarly rejected on the same basis as claim 6 above as claim 20 is the method claim corresponding to the apparatus of claim 6 above.
In regards to claim 7, the combination of Intel and Das Sarma discloses The apparatus of claim 1 (see rejection of claim 1 above) wherein when the comparison indicates the data element of the first source is equal to the data element of the second source, a carry flag of the flags register is set to 0, a parity flag of the flags register is set to 0, and a zero flag of the flags register is set to 1. (Intel: page 5-970: wherein for an equal to result ZF, PF and CF are all set to 100 respectively)
Claim 14 is similarly rejected on the same basis as claim 7 above as claim 14 is the system claim corresponding to the apparatus of claim 7 above.
In regards to claim 23, the combination of Intel and Das Sarma thus far discloses The apparatus of claim 1 (see rejection of claim 1 above).
The combination of Intel and Das Sarma thus far does not disclose wherein the variable exponential bias is to be provided by a general-purpose register identified by one or more fields of the single instruction.
Das Sarma discloses wherein the variable exponential bias is to be provided by a register identified by a single instruction. ([0051, 0060-0064 and 0073]: wherein an instruction specifies a configurable exponential bias in a register)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the instruction of Intel and Das Sarma to include an identifier that specifies a register storing the configurable exponential bias as the instruction in Das Sarma. It would have been obvious to one of ordinary skill in the art because allowing an instruction to specify a register operand (configurable bias register) allows the use of register addressing which improves processor performance and program efficiency by eliminating slower memory access operands. Furthermore, it would allow for more compact instruction address fields and thus reduce instruction size (e.g. using less bits to address register space than memory space).
The combination of Intel and Das Sarma thus far does not explicitly disclose the register being a general-purpose register.
However, Intel discloses general purpose registers (pages 4-2 to 4-3 and 5-48).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the register storing the configurable bias to be a general-purpose register as taught in Intel. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a general-purpose register to store data) for another (using a generic register to store data) to yield predictable results (using a general-purpose register to store a configurable bias) (MPEP 2143 Example B). Furthermore, using general purpose registers to store data can be used for added storage flexibility.
18. Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Intel Das Sarma and further in view of Coleman, PGPUB No, 2017/0286118.
In regards to claim 22, the combination of Intel and Das Sarma discloses The method of claim 15 (see rejection of claim 15 above).
The combination of Intel and Das Sarma does not disclose further comprising: translating the single instruction into one or more instructions of a different instruction set architecture, wherein the executing the decoded instruction according to the opcode is the execution of the one or more instructions of the different instruction set architecture.
Coleman discloses translating a single instruction into one or more instructions of a different instruction set architecture, wherein the executing a decoded instruction according to the opcode is the execution of the one or more instructions of the different instruction set architecture. ([0045 and 0120-0121])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor including the single instruction of Intel and Das Sarma to include an instruction converter to translate instructions into a different architecture as the processor of Coleman. It would have been obvious to one of ordinary skill in the art because such translation allows for software written in a first language to be executed by a system built for a second language without the software needing to be rewritten, resulting in improved operational performance with added flexibility.
Response to Arguments
19. Applicant’s arguments, see pages 6-8 of the remarks filed on 6/2/2026, with respect to previous 35 USC 103 in view of Intel and Park have been fully considered and are partially persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 USC 103 in view of Intel and Das Sarma and 35 USC 101.
Claims 2-7, 9-14, 16-22 and 23 are argued at least based on their respective dependencies and thus remain rejected at least based on dependency.
Conclusion
20. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
NPL reference “Intel AVX512-FP16” for teaching a VCOMISH instruction which compares FP16 values in a low order of first operand and second operand and sets flags in EFLAG register
21. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183
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