DETAILED ACTION
This office action is in response to the reply filed on 01/09/2026.
Claims 1-22 are pending in the application and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-22 are rejected under 35 U.S.C. 103 as being unpatentable over Intel (Intel Architecture Instruction Set Extensions Programming Reference – February 2016) in view of Official Notice and Park (A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees).
Regarding claim 1, Intel discloses an apparatus comprising [page 1-1; the described instructions are for execution on a processor]: decode circuitry to decode an instance of a single instruction [page 5-970; a UCOMISS instruction contains fields for decoding by the processor], the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand [page 5-970; the instruction includes fields for an opcode and two packed source operands], wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands, a comparison of a data element at that position, and update a flags register based on the comparison; and the execution circuitry to execute the decoded instruction according to the opcode [page 5-970; the instruction is executed in order to perform a comparison of data and update a flags register]. Intel does not explicitly disclose that the compared data is FP8 format data. However, the examiner takes official notice that the use of FP8 data was notoriously well known at the time of the effective filing data of the application. Furthermore, Park explicitly discloses [page 967, first column] the use of 8-bit floating point data using variable exponential bias. Advantages of using such FP8 data include reduced memory usage, increased computational speed, and improved energy efficiency. The modification of an existing instruction to operate on a different type of data represents an obvious change in light of these advantages, and the claimed invention would therefore have been obvious to a person having skill in the art.
Regarding dependent claims 2-7, the claimed subject matter is clearly anticipated by the disclosure of Intel on page 5-970.
Regarding claims 8-21, the claimed subject matter is rejected for the same reasons as those outlined above with respect to claims 1-7
Regarding claim 22, Intel does not explicitly disclose translating the single instruction into one or more instructions of a different instruction set architecture, wherein the executing the decoded instruction according to the opcode is the execution of the one or more instructions of the different instruction set architecture. However, the examiner takes official notice that the translation of a single instruction into one or more instructions of a different ISA for execution was notoriously well known at the time of the effective filing date of the application. Such translation allows for software written in a first language to be executed by a system built for a second language without the software needing to be re-written, resulting in improved operational performance. Such operation would therefore have been obvious in the system of Intel.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corey Faherty whose telephone number is (571)270-1319. The examiner can normally be reached weekdays between 7:30 and 4:00 ET, with every other Friday off.
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/COREY S FAHERTY/Primary Examiner, Art Unit 2183