DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections - Formality Claims 1-35 are objected to for using the well-known term, FP8 (Floating Point 8) in a confusing manner. Sometimes it seems to be refereed to simply as “FP8”, sometime it seemed to be referred to as “FP8 formats”, sometime it seems to be refereed to as “FP8 elements”. For the purpose of the examination, examiner will construe the “FP8” or “FP8 elements” as any 8 bits wide floating-point data. Furthermore, u se of the acronym in the claims is confusing. At least, it should be spelled out first time it appears in the claims. Appropriate correction is required. Obvious-type Double Patenting (ODP) Rejections The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 1-35 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-35 of U.S. Patent 12/379,927 hereinafter ‘927 . Although the conflicting claims are not identical, they are not patentably distinct from each other. For example, Claims 1-35 of instant Application, respectively contain elements of claims 1-35 of the ‘927 as follows: Claims Instant Claims ‘927 1 , 8, 15, 22, 29 decode circuitry an instance of a single instruction includes fields for an opcode an identification of a location of a 1 st pack. data src operand an identification of a location of a 2 nd pack. data src operand an identification of a pack data dest. Operand execution circuitry is to perform for each data element position of the pack. data src operand a floating point scale op. a FP8 data element of the first pack. data src by multiplying the data element by a power of 2 value a value of exponent of the power if 2 value is a floor value of a FP8 data element of the 2 nd pack. data source store a result of the floating point scale op. a corresponding data elem. to execute according to the opcode 1 decode circuitry an instance of a single instruction includes fields for an opcode an identification of a location of a 1 st pack. data src operand an identification of a location of a 2 nd pack. data src operand an identification of a pack data dest. Operand execution circuitry is to perform for each data element position of the pack. data src operand a floating point scale op. a BF16 data element of* the first pack. data src by multiplying the data element by a power of 2 value a value of exponent of the power if 2 value is a floor value of a BF16 data element of * the 2 nd pack. data source store a result of the floating point scale op. a corresponding data elem. to execute according to the opcode 2 , 9, 16, 23, 30 a vector register 2 a vector register 3, 10, 17, 24, 31 a memory location 3 a memory location 4, 11, 18, 25, 32 a round to nearest even rounding mode 4 a round to nearest even rounding mode 5, 12. 19, 26, 33 the floor value is a zero a denormal 5 the floor value is a zero a denormal 6, 13, 20, 27, 34 the 1 st pack. data src a zero a denormal 6 the 1 st pack. data src a zero a denormal 7, 14, 21, 28, 35 one or more fields for a writemask register 7 one or more fields for a writemask register Claims 1-35 of ‘927 does not expressly disclose FP8 data element (instead they disclose * BF16 data elements) . However, an applicant submitted prior art, a non-patent publication, Lee et al., “ISSCC 2019/Session 7/ Machine Learning /7.7” hereinafter Lee does disclose a FP8 data element (see Lee Column 1, Paragraph 2) . At the time of the invention it would have been obvious to a person of ordinary skill in the art to in terchange FP8 with BF16 data element or vice versa . The suggestion/motivation for doing so would have been to reduces external memory accesses and enhances throughput (see Lee Column 1, Paragraph 2) . Claim Rejections - 35 USC § 112 2nd The following is a quotation of the second paragraph of 35 U.S.C. 112: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-35 are rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. Claim 1 recites the limitation "the data element " in line 8 . There is insufficient antecedent basis for this limitation in the claim. Similar problems exists for claims 8, 15, 22, and 29. Claim s 30-35 recites the limitation " T he non-transitory machine-readable medium " in line 1 . There is insufficient antecedent basis for this limitation in the claim. These appears to be typographical error, for the purpose of examination, the limitation will be construed as, ‘The method.’ Use of a phrase, “include fields for an having fields”, in claims 1, 8, 15, 22, and 29 fails to particularly point out and distinctly claim the subject matter because the phrase is grammatically nonsensical. Applicant is required to review the claim and correct all language which does not comply with 35 U.S.C. § 112, second paragraph. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anderson et al. (U.S. Publication 20 15/0088946 ), hereinafter Anderson. Referring to claim 1, Anderson teaches, as claimed, an apparatus (see Fig. 1) comprising: decode circuitry (see Fig. 2, Decoder 214) to decode an instance of a single instruction (see Fig. 2, Floating Point Scaling Instruction 203), the single instruction to include fields for an having fields for an opcode (see Fig. 14, Opcode 1433), an identification (see Fig. 14, First Source Specifier 1434) of a location (each represent an on-die location, see Paragraph 54) of a first packed data source operand (see Fig. 2, Packed Data Register 205 and First Source 216), an identification (see Fig. 14, Second Source Specifier 1435) of a location (each represent an on-die location, see Paragraph 54) of a second packed data source operand (see Fig. 2, Packed Data Register 205 and Second Source 218), and an identification (see Fig. 14, Destination Specifier 1436) of a packed data destination operand (see Fig. 2, Packed Data Register 205 and Destination 220), wherein the opcode is to indicate that execution circuitry (see Fig. 2, Floating Point Execution Unit 208) is to perform, for each data element position of the packed data source operands, a floating point scale operation (see Fig. 3, Floating Point Scaling Operation 324 ; and scalar floating point data may also be stored in the packed data registers, Paragraph 110 ) of a FP8 data (Different data element sizes are supported including at least 8-bit byte data, see Paragraph 110) element of the first packed data source (representative … of the first source, see Paragraph 58) by multiplying the data element by a power of 2 value (multiplied by a base … e.g., commonly base 2, see Paragraph 58), wherein a value of the exponent of the power of 2 value is a floor value (the floor, see Paragraph 63) of a FP8 data element (Different data element sizes are supported including at least 8-bit byte data, see Paragraph 110) of the second packed data source (Floor(zmm), see Paragraphs 115-116), and store a result (store a result, see Paragraph 112) of the floating point scale operation into a corresponding data element position (DEST represents a destination, see Paragraph 116) of the packed data destination operand; and the execution circuitry to execute the decoded instruction according to the opcode (pseudocode … operation, see Paragraph 116-117). As to claim 2, Anderson teaches the apparatus of claim 1, wherein the field for the identification of the first source operand is to identify a vector register (vector register, see Paragraph 110) . As to claim 3 , Anderson teaches the apparatus of claim 1, wherein the field for the identification of the first source operand is to identify a memory location (memory location, see Paragraph 54) . As to claim 4, Anderson teaches the apparatus of claim 1, wherein the execution circuitry is to use a round to nearest even rounding mode (round to nearest even digit, see Paragraph 108) during execution of the decoded instruction. As to claim 5, Anderson teaches the apparatus of claim 1, wherein the floor value is a zero (0 (for negative scaling operand), see Paragraph 116) when the data element of the second packed data source is a denormal (Denorm/Norm, see Paragraph 118, Table 3; Note, denormal is construed a value approaching zero) . As to claim 6, Anderson teaches the apparatus of claim 1, wherein the data element of the first packed data source is a zero (round toward zero, see Paragraph 108; Note, since data source is round toward zero, it is implicitly a denormal) when the data element of the first packed data source is a denormal (a denormal number, see Paragraph 64) . As to claim 7 , Anderson teaches the apparatus of claim 1, wherein the instruction is to further include one or more fields for a writemask register (register … used as a writemask, see Paragraph 114) . As to claims 8-21 , they are directed to a system/program to implement the device as set forth in claims 1-7 respectively. Therefore, they are rejected on the same basis as set forth hereinabove. Referring to claim 22 , Anderson teaches, as claimed, a non-transitory machine-readable medium storing at least an instance of a particular single instruction (received instruction, see Paragraph 56) , wherein the instance of the particular single instruction is to be processed by a processor (instruction processing apparatus, see Paragraph 56) by performing a method comprising: translating (translate, see Paragraph 56) the particular single instruction from a first instruction set architecture (instruction set architecture, see Paragraph 44) to one or more instruction of second, different instruction set architecture (not being tied to any specific instruction set, see Paragraph 123 and Fig. 27, Alternative Instruction Set) , the particular single instruction to include fields for an having fields for an opcode (see Fig. 14, Opcode 1433), an identification (see Fig. 14, First Source Specifier 1434) of a location (each represent an on-die location, see Paragraph 54) of a first packed data source operand (see Fig. 2, Packed Data Register 205 and First Source 216), an identification (see Fig. 14, Second Source Specifier 1435) of a location (each represent an on-die location, see Paragraph 54) of a second packed data source operand (see Fig. 2, Packed Data Register 205 and Second Source 218), and an identification (see Fig. 14, Destination Specifier 1436) of a packed data destination operand (see Fig. 2, Packed Data Register 205 and Destination 220), wherein the opcode is to indicate that execution circuitry (see Fig. 2, Floating Point Execution Unit 208) is to perform, for each data element position of the packed data source operands, a floating point scale operation (see Fig. 3, Floating Point Scaling Operation 324; and scalar floating point data may also be stored in the packed data registers, Paragraph 110) of a FP8 data (Different data element sizes are supported including at least 8-bit byte data, see Paragraph 110) element of the first packed data source (representative … of the first source, see Paragraph 58) by multiplying the data element by a power of 2 value (multiplied by a base … e.g., commonly base 2, see Paragraph 58), wherein a value of the exponent of the power of 2 value is a floor value (the floor, see Paragraph 63) of a FP8 data element (Different data element sizes are supported including at least 8-bit byte data, see Paragraph 110) of the second packed data source (Floor(zmm), see Paragraphs 115-116), and store a result (store a result, see Paragraph 112) of the floating point scale operation into a corresponding data element position (DEST represents a destination, see Paragraph 116) of the packed data destination operand; and decoding (a decoder, see Paragraph 56) the one or more instruction of a second (decode the one or more intermediate instruction, see Paragraph 56) , different instruction set architecture; execut ing (executable by native hardware, see Paragraph 56) the decoded ore or more instruction s of second, different instruction set architecture . As to claims 23-28 , they are directed to a program (with translation given in claim 22) to implement the device as set forth in claims 2-7 respectively. Therefore, they are rejected on the same basis as set forth hereinabove. As to claims 29-35 , they are directed to a method to implement the program as set forth in claims 22-28 respectively. Therefore, they are rejected on the same basis as set forth hereinabove. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HYUN NAM/ Primary Examiner, Art Unit 2183