Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Objections. The objections to the claims are withdrawn based on amendment to claims.
Double Patenting. Applicant states that the double patenting rejections will be addressed once claims are allowable, if deemed necessary by a future office action.
Examiner is maintaining the nonstatutory double patenting rejections.
35 USC 112(b). The rejections of claims 1-20 under 35 USC 112(b) are withdrawn based on amendment to claims.
35 USC 102. Applicant asserts that Appu does not teach or suggest a single instruction including fields for an opcode that indicates an arithmetic operation is to be performed, for each data element position of identified packed data source operands, on 8-bit floating point data elements in that data element position in 8-bit floating point format (Remarks p. 7-8). Specifically, Applicant asserts:
Regarding the generic graphics SIMD instruction format, Appu's paragraph [0247] merely discloses that the execution unit operates on vectors as "thirty-two separate 8-bit data elements (byte (B) size data elements)." Appu does not explicitly or inherently disclose that these 8-bit data elements are 8-bit floating point data elements. Furthermore, Appu's paragraph [0154] refers to sorting threads having FP8 operations to different floating point units. Appu, as cited, completely fails to explicitly link this thread sorting mechanism with the packed data SIMD instruction formats of paragraphs [0247] and [0253]. Thus, Appu fails to disclose a single instruction having an opcode that dictates performing an arithmetic operation on packed 8-bit floating point data elements for each data element position.
Notably, when Appu explicitly details mixed precision operations and converting operands to a common format in a single instruction context, paragraph [0157] states that the operands "may include, but not be limited to, any of FP64, FP32, FP16, INT32, INT16, INT8 or INT16." Appu omits FP8 from this list of supported formats for arithmetic logic unit (ALU) operations. Therefore, the four corners of Appu fail to disclose a single packed data instruction that indicates an arithmetic operation on 8-bit floating point data elements.
Examiner is persuaded by Applicant arguments. The rejection of claims 1-3, 5-6, 8-10, 12-13, 15 and 18-20 under 35 USC 102 is withdrawn. For the same reasons, the rejection of claims 4, 7, 11, 14, and 19 under 35 USC 103 is withdrawn.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application IN 202241044441 filed on 08/03/22. It is noted, however, that applicant has not filed a certified copy of the foreign priority application as required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 8-10, and 15 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 8-10, and 15 of copending Application No. 17958370 (reference application).
Although the claims at issue are not identical, they are not patentably distinct from each other. Claims 1-3, 8-10, and 15 of the reference application would anticipate claims 1-3, 8-10, and 15 of the present application. The floating point scale operation of the reference application is an anticipatory arithmetic operation of the present application. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
See representative claim comparison below.
17958373
17958370
1. An apparatus comprising:
1. An apparatus comprising:
decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on 8-bit floating point data elements in that data element position in 8-bit floating point format and store a result of each arithmetic operation into a corresponding data element position of the identified packed data destination operand; and
decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a FP8 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a FP8 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand; and
the execution circuitry to execute the decoded instruction according to the opcode.
the execution circuitry to execute the decoded instruction according to the opcode.
Claims 1 and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 16 of the Reference Application above (17958469).
Although the claims at issue are not identical, they are not patentably distinct from each other. Claims 1 and 16 of the reference application would anticipate claims 1 and 15 of the present application. The fused multiply-accumulate operation of the reference application is an anticipatory arithmetic operation of the present application.
See representative claim mapping below with respect to the Reference Application.
17958373
17958369
1. An apparatus comprising:
1. An apparatus comprising:
decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on 8-bit floating point data elements in that data element position in 8-bit floating point format and store a result of each arithmetic operation into a corresponding data element position of the identified packed data destination operand; and
decoder circuitry to decode a single instruction, the single instruction to include fields for an opcode, an identification of location of a packed data source/destination operand (a first packed data source operand), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a FP8 value fused multiply-accumulate operation using the first, second, and third packed data source operands and store a result in a corresponding data element position of the source/destination operand, wherein the FP8 value has an 8-bit floating point format that comprises one bit for a sign, 4 bits for an exponent, and three bits for a fraction; and
the execution circuitry to execute the decoded instruction according to the opcode.
execution circuitry to execute the decoded single instruction according to the opcode.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 1-4, 15, and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-4, 17, and 25 respectively of U.S. Patent No. 12517728 (reference Patent). Although the claims at issue are not identical, they are not patentably distinct from each other.
Claims 1 and 16 of the reference patent would anticipate claims 1 and 15 of the present application. The prefix sum operation of the reference application is an anticipatory arithmetic operation of the present application.
See representative claim mapping below with respect to the Reference Patent.
17958373
12517728
1. An apparatus comprising:
1. An apparatus comprising:
decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on 8-bit floating point data elements in that data element position in 8-bit floating point format and store a result of each arithmetic operation into a corresponding data element position of the identified packed data destination operand; and
decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and
the execution circuitry to execute the decoded instruction according to the opcode.
execution circuitry configured to execute the decoded instruction according to the opcode.
Allowable Subject Matter
Claims 5-7, 11-14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 1-4, 8-10, and 15 would be allowable if rewritten to overcome the nonstatutory double patenting rejections.
The following is a statement of reasons for the indication of allowable subject matter. Examiner adopts reasons set forth by applicant in the arguments filed 07/24/26 p. 7-8 as reasons for indication of allowable subject matter. See also response to arguments above at p. 2-3.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at 571 272 3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
Prosecution Insights