DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 8, 2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on application IN 202241044453, filed on August 3 2022.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “APPARATUSES, METHODS, AND SYSTEMS FOR EXECUTING AN INSTRUCTION THAT CONVERTS 8-BIT FLOATING-POINT ELEMENTS TO SINGLE-PRECISION ELEMENTS PRIOR TO PERFORMING MATRIX DOT PRODUCT OPERATIONS”.
Claim Objections
Claims 2, 10, and 18 are objected to because of the following informalities:
Claim 2: For flow/readability, Examiner recommends that the claim instead reads as “an 8-bit floating-point format is specified by the opcode of the single instruction as either including a 1-bit sign, 5-bit exponent, and 2-bit fraction or including a 1-bit sign, 4-bit exponent, and 3-bit fraction.”
Claim 10: For flow/readability, Examiner recommends that the claim instead reads as “an 8-bit floating-point format is specified by the opcode of the single instruction as either including a 1-bit sign, 5-bit exponent, and 2-bit fraction or including a 1-bit sign, 4-bit exponent, and 3-bit fraction.”
Claim 18: For flow/readability, Examiner recommends that the claim instead reads as “an 8-bit floating-point format is specified by the opcode of the single instruction as either including a 1-bit sign, 5-bit exponent, and 2-bit fraction or including a 1-bit sign, 4-bit exponent, and 3-bit fraction.”
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7, 9-15, and 17-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1, 9, and 17 recite an apparatus, a method, and a non-transitory
machine-readable medium, respectively. Thus, each of the claims fall under one of the four statutory categories.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), claim 1 recites “locations of an M by N destination matrix having single-precision elements, an M by K first source matrix, and a K by N second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values” and “for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values using a configurable bias value per element, a multiplication of converted single-precision values from first values of the quadruples together to generate a first result, a multiplication of converted single-precision values from second values of the quadruples together to generate a second result, a multiplication of converted single-precision values from third values of the quadruples together to generate a third result, a multiplication of converted single- precision values from fourth values of the quadruples together to generate a fourth result, and an accumulation of the first, second, third, and fourth results with previous contents of a corresponding element of the destination matrix.” Such limitations cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. Therefore the claim includes limitations that fall within the “mental processes” and “mathematical concepts” groupings of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The elements “fetch circuitry to fetch a single instruction having fields to specify an opcode”, “the opcode to indicate execution circuitry”, “decode circuitry to decode the fetched instruction”, and “execution circuitry to respond to the decoded instruction as specified by the opcode” are recited at a high level of generality, i.e., generic computer elements performing generic computer operations. Such elements amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)), which do not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). Thus, the elements fails to integrate the judicial exception into a practical application.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to Step 2A Prong Two, the additional elements in the claim amount to no more than mere instructions to apply the exception (see MPEP 2106.05(f)) and does not amount to significantly more than the judicial exception. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 recites “an 8-bit floating-point format is specified by the opcode of the single instruction as either a 1-bit sign, 5-bit exponent, and 2-bit fraction or 1- bit sign, 4-bit exponent, and 3-bit fraction”. Such limitations further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 recites “M, N, and K are specified by the single instruction.” Such element amount to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 recites “the execution circuitry is to cause a matrix operations accelerator to perform at least the multiplications and the accumulation.” Such element amount to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 recites “M, N, and K are specified by a configuration of the matrix operations accelerator to be programmed by execution of a matrix accelerator configuration instruction before executing the single instruction.” Such element amount to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 recites “saturation of execution results, as necessary.” Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. Additionally, the claim recites “the execution circuitry”. Such element amounts to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 recites “a writemask comprising M x N bits, each bit to control whether to mask a corresponding element of the destination matrix.” Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim additionally recites “the single instruction” Such element amount to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 is mostly rejected for the same reasons as claim 1. The claim additionally recites “the execution circuitry is to cause, in parallel”. The element is doing no more than generally linking the exception to a particular technological environment or field of use (e.g., field of parallel computation), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). Additionally, the claim recites “a packed data register”. Such element amounts to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 10-15 recite a method similar to the apparatus of claims 2-7, respectively. Therefore, claims 10-15 are rejected on the same premises.
Claim 17 is mostly rejected for similar reasoning as the apparatus of claim 1. The claim additionally recites “a non-transitory machine readable medium that stores program code that when executed by a machine causes the machine to perform a method.” Such element amounts to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), which does not integrate the judicial exception into a practical application (see MPEP 2106.04(d)(I)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to significantly more than the judicial exception under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 18-23, the claims recite a non-transitory machine-readable medium similar to the apparatus of claims 2-7, respectively. Therefore, claims 18-23 are rejected on the same premises.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 17-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Patent No. 12,020,028 (hereinafter ‘028) in view of Alexander et al. (US 12399717 B2) and Das Sarma (US 20200349216 A1).
Regarding claim 1, ‘028 teaches an apparatus comprising:
fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a M by N destination matrix having single-precision elements, an M by K first source matrix, and a K by N second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values
decode circuitry to decode the fetched instruction; and
the execution circuitry to respond to the decoded instruction as specified by the opcode (see claim 1).
‘028 does not teach that the conversion of the 8-bit floating-point values to single-precision values using a configurable bias per element.
Alexander teaches the use of a bias when converting to FP32, in which the conversion uses a bias per element (Fig. 3 and Col. 13, lines 17-45: The exponent of the single-precision floating-point data is calculated using the bias of the input data (e.g., the FP8 data) and the FP32 bias. This bias is then applied for each intermediate value received from the arithmetic processing circuitry 310 for each vector pair going through the processing circuitry (i.e., the bias is applied per element)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of ‘028 with the teachings of Alexander to have converted 8-bit floating point values to single-precision floating point values using a bias per element of the matrix operands. Using biases when converting between floating-point types allows the proper scaling of the exponent of the end-resulting floating-point type so that the resulting data is still represented, in which one of ordinary skill would appreciate.
‘028, in view of Alexander, still does not teach that the bias is a configurable bias.
Das Sarma teaches to use a configurable bias for data formats such as floating-point formats ([0013, 0015]: “Each matrix operand element uses a configurable exponent bias”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of ‘028, in view of Alexander, to have used a configurable bias when converting 8-bit floating point values to single-precision floating point values. One of ordinary skill would recognize that by using a configurable bias instead of a fixed bias for biasing the exponents, the exponent range is improved and a larger exponent range can be utilized (see Das Sarma, [0013]).
Regarding claims 2-8, the claims are taught by claims 2-8 of ‘028, in view of Alexander and Das Sarma. Therefore, the claims are rejected for this reason.
Regarding claim 17, the claim is rejected for the same reasons as claim 1, using claim 17 of ‘028.
Regarding claims 18-24, the claims are taught by claims 18-24 of ‘028, in view of Alexander and Das Sarma. Therefore, the claims are rejected for this reason.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 17, and 19-24 are rejected under 35 U.S.C. 103 as being unpatentable over Heinecke et al. (US 10963246 B2) in view of Das Sarma et al. (hereinafter Das Sarma 1) (US 20200348909 A1), Mach et al. (“A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing”), Alexander et al. (US 12399717 B2), and Das Sarma (hereinafter Das Sarma 2) (US 20200349216 A1).
Regarding claim 1, Heinecke teaches an apparatus (Fig. 13: Core 1390) comprising:
fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a M by N destination matrix having single-precision elements (Figs. 13 and 21, Col. 12, lines 61-65 and Col. 20, lines 1-12 and Col. 14, lines 9-12: Core 1390 to include an instruction fetch circuit, where the instruction fetch is that of instruction 2101 with opcode 2102. Instruction 2101 to specify a destination matrix having size M by N having single precision elements), an M by K first source matrix (see Col. 20, lines 1-12), and a K by N second source matrix (see Col. 20, lines 1-12), the source matrices having elements that each comprise a pair of 16-bit floating-point values (see Col. 19, lines 45-67), the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 16-bit floating-point values to single-precision values using bias (Fig. 21 and Col. 20, lines 19-32), a multiplication of converted single-precision values from first values of the pair together to generate a first result (Fig. 21 and Col 20. lines 19-48), a multiplication of converted single-precision values from second values of the pair together to generate a second result (Fig. 21 and Col. 20, lines 19-48), and an accumulation of the first and second results with previous contents of a corresponding element of the destination matrix (Fig. 21 and Col. 20 lines 32-48);
decode circuitry to decode the fetched instruction (Fig. 13: branch/decode circuitry 1303); and
the execution circuitry to respond to the decoded instruction as specified by the opcode (Fig. 13: Execution circuitry 1311).
However, Heinecke does not teach that the source matrices have elements that each comprise a quadruple of 8-bit floating-point values, a conversion of the 8-bit floating-point values to single-precision values using bias, a multiplication of converted single-precision values from third values of the quadruples together to generate a third result, a multiplication of converted single-precision values from fourth values of the quadruples together to generate a fourth result, and an accumulation of the first, second, third, and fourth results with previous contents of a corresponding element of the destination matrix
Das Sarma 1 teaches the use of 8-bit floating-point matrices (see [0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the teachings of Heinecke and combined the teachings of Heinecke with the teachings of Das Sarma to have created a quadruple of 8-bit floating point matrices as source inputs for matrix multiplication. One of ordinary skill would have realized that using 8-bit floating point as the data element of matrices for matrix multiplication would improve memory bandwidth and power consumption (see Das Sarma, [0049]). Given that Heinecke teaches pairs of 16-bit float-point data values, one of ordinary skill would have realized that changing the data value type from 16-bit to 8-bit would mean that two more 8-bit values could be added to the submatrix, resulting in additional calculations that can be done at a time. Additionally, changing the size/proportion of a part, i.e., increasing the number of data elements from a pair of elements to a quadruple of elements, is deemed a routine expedient, not a patentable distinction (MPEP 2144.04(IV)(A)).
However, Heinecke, as modified and in view of Das Sarma 1, still does not teach a conversion of the 8-bit floating-point values to single-precision values using bias, a multiplication of converted single-precision values from third values of the quadruples together to generate a third result, a multiplication of converted single-precision values from fourth values of the quadruples together to generate a fourth result, and an accumulation of the first, second, third, and fourth results with previous contents of a corresponding element of the destination matrix.
Mach teaches converting between 8-bit floating-point (Section II, 2nd paragraph: “Binary8 is an 8-bit format featuring 3 bit of mantissa, and 5 bit of exponent”) and single-precision floating-point data (Fig. 3 and Section I, 3rd paragraph: binary32 is single-precision floating point data. Fig. 3 shows a Slice32 convert unit between 8-bit floating point and single-precision floating point) and Alexander teaches the use of a bias when converting to FP32 (Col. 13, lines 17-36: The exponent of the single-precision floating-point data is calculated using the bias of the input data (e.g., the FP8 data) and the FP32 bias).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Heinecke, as modified and in view of Das Sarma 1, with the teachings of Mach and Alexander to have converted from 8-bit floating point to single-precision floating point using bias. 8-bit floating point data have many benefits compared to other floating-point types such as saving space in memory. However, keeping the 8-bit floating point format during operations such as matrix multiplication may lose vital precision of data, therefore converting the 8-bit floating-point data to a higher precision would prevent the loss of data, which one of ordinary skill would appreciate. Using biases when converting between floating-point types allows the proper scaling of the exponent of the end-resulting floating-point type so that the resulting floating-point type is still represented with a biased exponent, which one of ordinary skill would appreciate.
However, Heinecke, as modified and in view of Das Sarma 1, Mach, and Alexander, still does not teach using a configurable bias, a multiplication of converted single-precision values from third values of the quadruples together to generate a third result, a multiplication of converted single- precision values from fourth values of the quadruples together to generate a fourth result, and an accumulation of the first, second, third, and fourth results with previous contents of a corresponding element of the destination matrix.
Das Sarma 2 teaches to use a configurable bias for data formats such as floating-point formats ([0013, 0015]: “Each matrix operand element uses a configurable exponent bias”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Heinecke, as modified and in view of Das Sarma 1, Mach, and Alexander, to have used a configurable bias when converting 8-bit floating point values to single-precision floating point values. One of ordinary skill would recognize that by using a configurable bias instead of a fixed bias for biasing the exponents, the exponent range is improved and a larger exponent range can be utilized (see Das Sarma 2, [0013]).
However, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, still does not teach a multiplication of converted single-precision values from third values of the quadruples together to generate a third result, a multiplication of converted single- precision values from fourth values of the quadruples together to generate a fourth result, and an accumulation of the first, second, third, and fourth results with previous contents of a corresponding element of the destination matrix.
It would have been obvious to one of ordinary skill in the art before the effective filing date to have further modified the teachings of Heinecke, in view of Das Sarma 1, Mach, and Alexander, to have performed a multiplication of converted single-precision values from third values of the quadruples together to generate a third result, a multiplication of converted single-precision values from fourth values of the quadruples together to generate a fourth result, and an accumulation of the first, second, third, and fourth results with previous contents of a corresponding element of the destination matrix. Given the circuitry of Heinecke, one of ordinary skill would have recognized that to generate a third and fourth result from the multiplication of the third and fourth values of the quadruple, they would need to duplicate the circuitry to accommodate the additional inputs. Hence, duplication of parts, i.e., duplicating the multiply and accumulate circuitry, is deemed a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(B)).
Regarding claim 3, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches the apparatus of claim 1, wherein M, N, and K are specified by the single instruction (Heinecke, Col. 21 lines 29-40).
Regarding claim 4, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches the apparatus of claim 1, where the execution circuitry is to cause a matrix operations accelerator to perform at least the multiplications and the accumulation (Heinecke, Fig. 3 and Col. 22, lines 64-66: Execution circuitry 1311 can be the accelerator 307 that performs matrix operations, including multiplication and accumulation).
Regarding claim 5, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches the apparatus of claim 4, wherein M, N, and K are specified by a configuration of the matrix operations accelerator to be programmed by execution of a matrix accelerator configuration instruction before executing the single instruction (Heinecke, Col. 21, lines 29-40: TILECFG instruction is to specify M, N, and K, which is to be executed prior to executing a matrix multiplication instruction that doesn’t specify M, N, and K).
Regarding claim 6, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches the apparatus of claim 1, wherein the execution circuitry is further to cause saturation of execution results, as necessary (Heinecke, Fig. 8 and Col. 9, lines 43-48: Figure 8 shows a diagram of the execution circuitry, where it includes an adder/saturate circuit, which saturates when an overflow or underflow occurs).
Regarding claim 7, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches the apparatus of claim 1, wherein the single instruction is further to specify a writemask comprising M x N bits, each bit to control whether to mask a corresponding element of the destination matrix (Heinecke, Col. 44, lines 23-28).
Regarding claim 8, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches the apparatus of claim 1, wherein the execution circuitry is further to generate a fault when a fault condition occurs (Heinecke, Col. 44, lines 35-36), the fault condition selectable from:
the destination matrix having a fewer number of rows than a number of rows of the first source matrix (Heinecke, Col. 44, lines 39-41: Different number of rows includes having less rows of the destination matrix than the number of rows of the first source matrix); and
the destination matrix having a fewer number of columns than a number of columns of the first source matrix (Heinecke, Col. 44, lines 41-43: Different number of columns includes having less columns of the destination matrix than the number of columns of the first source matrix).
Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, does not teach that the destination matrix having a fewer number of columns than a number of columns of the second source matrix generates a fault.
It would have been obvious to one of ordinary skill in the art before the effective filing date to have further modified Heinecke, in view of Das Sarma 1, Mach, and Alexander, to have generated a fault when the destination matrix has a fewer number of columns than the number of columns of the second source matrix. One of ordinary skill would be motivated to further failproof the processor seen in Heinecke by creating additional parameters to generate faults when the second source matrix also has a different number of columns than the number of columns of the destination matrix, so as to prevent further errors or total-failures.
Regarding claim 17, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches a non-transitory machine readable medium that stores program code that when executed by a machine causes the machine to perform a method (Heinecke, Col. 42, lines 39-60: Embodiments may be stored as non-transitory machine-readable media, which includes storing instructions to perform a method). The claim further recites a non-transitory machine readable medium similar to the apparatus of claim 1. Therefore, the claim is rejected on the same premises.
Regarding claims 19-24, the claims recite a non-transitory machine readable medium similar to the apparatus of claims 3-8, respectively. Therefore, the claims are rejected on the same premises.
Claim 2 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Heinecke et al. (US 10963246 B2) in view of Das Sarma 1 (US 20200348909 A1), Mach et al. (“A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing”), Alexander et al. (US 12399717 B2), Das Sarma 2 (US 20200349216 A1) and Agrawal et al. (US 20220075595 A1).
Regarding claim 2, Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, teaches the apparatus of claim 1.
Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, does not teach that the 8-bit floating-point format is specified by the opcode of the single instruction as either a 1-bit sign, 5-bit exponent, and 2-bit fraction or 1- bit sign, 4-bit exponent, and 3-bit fraction.
Agrawal teaches that the 8-bit floating-point format is specified by the opcode of a single instruction as either a 1-bit sign, 5-bit exponent, and 2-bit fraction or 1-bit sign, 4-bit exponent, and 3-bit fraction ([0090]: 1/5/2 format means 1-bit sign, 5-bit exponent, and 2-bit fraction. 1/4/3 format means 1-bit sign, 4-bit exponent, and 3-bit fraction).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Heinecke, as modified and in view of Das Sarma 1, Mach, Alexander, and Das Sarma 2, with the teachings of Agrawal to have the opcode specify the 8-bit floating-point format. One of ordinary skill may prefer using a certain 8-bit floating-point type over the other for certain applications, therefore the ability to specify the 8-bit floating point type to be used to perform matrix multiplication may be appreciated.
Claim 18 is rejected for the same reasons above.
Allowable Subject Matter
Claims 9-16 are allowed, over the prior art.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 9-16, the prior art of record has not taught, either individually or in combination, and together with all other claimed features, that a conversion of the 8-bit floating-point values to single-precision values using a per element variable bias provided by a packed data register.
Response to Arguments/Amendments
Examiner will maintain the title objection as the title does not include the conversion of data types as reflected in the claims.
Applicant's arguments, see page 8, filed August 27, 2026, with respect to the objections of claims 2, 10, and 18 have been fully considered but they are not persuasive. Applicant does not explain how it would be more confusing. The phrasing to have “including” would be correct since the 8-bit format would include the first combination of bits or second combination of bits. The objections of claims 2, 10, and 18 are being maintained.
Applicant's arguments, see pages 9-12, filed August 27, 2026, with respect to the rejections of claims 1-7, 9-15, and 17-23 under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding arguments on page 9, paragraph 2, Applicant argues that the claims are directed towards microprocessor circuitry, in which the circuitry cannot be performed in the human mind.
See MPEP 2106 regarding patent subject matter eligibility. Each of the independent claims recite mental/mathematical limitations with respect to converting 8-bit floating point to single-precision floating point and matrix multiplication (as stated in the 101 rejection analysis). The Applicant uses computer components, such as execution circuitry of a processor, as tools to perform the abstract idea, which doesn’t integrate the judicial exception into a practical application or provide an inventive concept (see 2106.05(f)(2), paragraphs 1-2, also see MPEP 2106.04(a)(2)(III)(C)). Therefore, Applicant’s remarks regarding that the circuitry cannot be performed in the human mind are considered not persuasive.
Regarding arguments on page 9, paragraph 2, Applicant argues that the human mind could not practically perform math in an unfamiliar (8-bit floating point) non-decimal format.
Examiner respectfully disagrees with this argument. See MPEP 2106(a)(2)(III) regarding subject matter reciting mental processes. A human mind alongside pen and paper could be used to perform math (see MPEP 2106.04(a)(2)(III)(B)). Furthermore, Applicant does not clarify or provide evidence on why a human mind with pen and paper cannot perform math with 8-bit floating-point data. Therefore, Applicant’s remarks regarding what the human mind cannot do are considered not persuasive.
Regarding arguments on page 9, paragraph 3 to page 10, paragraph 1, Applicant argues that the human mind cannot maintain active computational variable concurrently without immediate memory decay.
Examiner respectfully disagrees with this argument. See MPEP 2106(a)(2)(III) regarding subject matter reciting mental processes. A human mind could perform these operations using pen and paper as an aide (see MPEP 2106.04(a)(2)(III)(B)). A human does not need to rely on memory alone to remember the matrices and perform matrix multiplication. Therefore, Applicant’s remarks regarding that the human mind maintain active computational variable concurrently without immediate memory decay are considered not persuasive.
Regarding arguments on page 10, paragraph 2, Applicant argues that the processes of performing data manipulation and conversion would result a near 100% potential for errors.
Examiner respectfully disagrees with this argument. See MPEP 2106.04(a)(2)(III) regarding subject matter reciting mental processes. Applicant makes an assertion that a human mind with pen and paper has a near 100% potential for errors, while not providing evidence that this is the case. Therefore, Applicant’s remarks regarding that a human performing the operations results in near guaranteed errors are considered not persuasive.
Regarding arguments on page 10, paragraph 3 to page 11, paragraph 2, Applicant argues that the processes of unpacking 8-bit floating numbers or performing MAC operations would not be practical, both the human mind alone or with pen and paper.
Examiner respectfully disagrees with this argument. See MPEP 2106(a)(2)(III) regarding subject matter reciting mental processes. First, as previously stated, a human can perform these operations using their mind and with pen and paper to hold onto intermediate values, which wouldn’t result in a human to restart the process. Note, MPEP 2106.04(a)(2)(III)(B) states that “the use of a physical aid (e.g., pencil and paper or a slide rule) to help perform a mental step (e.g., a mathematical calculation) does not negate the mental nature of the limitation, but simply accounts for variations in memory capacity from one person to another”. Therefore, writing down intermediate values is allowed as part of the mental process. Therefore, Applicant’s remarks regarding that unpacking 8-bit floating numbers or performing MAC operations would not be practical, both the human mind alone or with pen and paper, are considered not persuasive.
Regarding arguments on page 11, paragraph 3, Applicant argues that the Examiner analyzed the claims at an impermissibly high level of generality.
Examiner respectfully disagrees with this argument. See MPEP 2106 regarding subject matter eligibility. Examiner has explained in the 101 analysis how each of the limitations do not amount to anything significant more and do not integrate the judicial exception into a practical application. At a high level, the Applicant is using a computer as a tool to perform the judicial exception, which does not integrate the judicial exception into a practical application (See MPEP 2106.05(f)(2), also see MPEP 2106.04(a)(2)(III)(C)). See 101 analysis for a complete explanation. Therefore, Applicant’s remarks regarding that the Examiner analyzed the claims at an impermissibly high level of generality are considered not persuasive.
Regarding arguments on page 11, paragraph 4 to page 12, paragraph 1, Applicant argues that the claims are directed to an improvement.
Examiner respectfully disagrees. Examiner has addressed this argument on page 26 in the Final Office Action mailed April 27, 2026, and will not repeat those arguments for the sake of brevity.
The rejection of claims 1-7, 9-15, and 17-23 under 35 U.S.C. 101 are being maintained.
Applicant's arguments, see pages 13-14, filed August 27, 2026, with respect to the rejections of claims 1, 3-8, 17, and 19-24 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Regarding arguments on page 13, paragraph 3, Applicant argues that Heinecke does not teach the claimed requirement of multiplying the already converted and biased single-precision values.
Examiner respectfully disagrees. Examiner directs Applicant’s attention to Figures 21-22A and Col. 20, lines 19-31. The section in the specification and the drawings specifically show that the data elements are first converted into single-precision elements. Figure 21 shows that the conversion occurs first (steps 2116A and 2116B) before a multiplication that occurs after (step 2118) and Figure 22A is pseudocode that shows the conversion of elements from bfloat16 to single-precision, before those elements are multiplied. Therefore, the multiplication consists of multiplying single-precision elements. Therefore, Applicant’s remarks regarding that Heinecke does not teach the limitation are considered not persuasive.
Regarding arguments on page 13, paragraph 4 to page 14, paragraph 1, Applicant argues that the rejection relies on impermissible hindsight using Applicant’s own disclosure as a roadmap.
Examiner respectfully disagrees. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). In this instant case, the prior art only utilizes a pair of values, whereas Applicant’s specification utilizes a quadruple of values. If one of ordinary skill was tasked to create a processor to perform matrix multiplication and accumulation with each element of a matrix comprising a quadruple of values, using what was already known from Heinecke, one of ordinary skill would have increased the size of each matrix element to comprise of a quadruple of values and duplicated the circuitry of Heinecke to handle a quadruple of values rather than a pair of values. The knowledge to increase the size of the matrices and duplicating the circuitry would have been within the level of ordinary skill at the time of the claimed invention was made. Therefore, the application of MPEP 2144.04(IV)(A) and MPEP 2144.04(VI)(B) were properly applied. Furthermore, the claims do not recite a distinct multiplier circuit, a 4-input adder tree, or a decoder to handle new semantics. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, Applicant’s remarks regarding that the rejection relies on impermissible hindsight using Applicant’s own disclosure as a roadmap are considered not persuasive.
The rejection of claims 1, 3-8, 17, and 19-24 under 35 U.S.C. 103 are being maintained.
Conclusion
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
