Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Objections.
Applicant asserts that the claims have been amended to overcome the objections to claims (Remarks p. 6).
Examiner respectfully disagrees as to claims 4-5, 7, 11-12, 14, and 17-18. These claims have not been amended to overcome the claim objections. The objections to claims other than these claim objections have been withdrawn.
Double Patenting.
Applicant states that these rejections will be addressed upon confirmation of allowability of the claims and the office wanting to maintain these rejections (Remarks p. 6).
Examiner maintains the nonstatutory double patenting rejections as set forth below.
35 USC 112(b). The rejections of claim 1-20 are withdrawn based on amendment to claims.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application IN 202241044437 filed on 08/03/22. It is noted, however, that applicant has not filed a certified copy of the foreign priority application as required by 37 CFR 1.55.
Claim Objections
Claims 4-5, 7, 11-12, 14, and 17-18 objected to because of the following informalities.
Claim 1 recites the “packed FP8 data.” Claims 4-5, 7, 11-12, 14, and 17-18 recite “the FP8 data” or “the converted FP8 data”. This limitation lacks antecedent basis and should recite “the packed FP8 data” or “the converted FP8 data” appropriately.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 8-9, and 11-20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-9, and 11-20 of copending Application No. 17958380 (reference application).
Although the claims at issue are not identical, they are not patentably distinct from each other. Claims 8-9, and 11-20 of the reference application would anticipate claims 8-9, and 11-20 of the present application. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
See representative claim comparison below.
17958378
17958380
8. A method comprising:
8. A method comprising:
decoding a single instruction, the single instruction to include one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data or single-precision floating point data from the identified source to packed FP8 data and store the packed FP8 data into corresponding data element positions of the identified destination operand; and
decoding a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand,
wherein the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction; and
executing the decoded instruction according to the opcode to convert packed half- precision floating-point data or single-precision floating point data from the identified source to packed FP8 data and store the packed FP8 data into corresponding data element positions of the identified destination operand.
executing the decoded instruction according to the opcode to convert packed half- precision data from the identified first and second source operands to the packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand.
Claims 1-2, and 4-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-2, and 4-7 of the Reference Application above (17958380) in view of US 20240329991.
Although the claims at issue are not identical, they are not patentably distinct from each other. Claims 8-9, and 11-20 of the reference application would be obvious claims 1-2, and 4-7 of the present application. See representative claim mapping below with respect to the Reference Application.
The Reference Application does not explicitly disclose the opcode to indicate that the execution circuitry is to convert single-precision floating point data. However, US 20240329991 claims an apparatus comprising decoder circuitry to decode an instruction, and execution circuitry to perform operations according to the instruction to indicate at least one source floating-point vector, the source floating-point vector to have a plurality of floating-point data elements, the at least one value to indicate at least one of a) a number of significant bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating point data elements (claim 1), wherein the instruction is a floating-point conversion instruction wherein the source floating-point conversion instruction and conversion including double precision, single precision, half precision, bfloat16, and FP8. It would have been obvious to include single precision in addition to packed half-precision floating-point data as one of the source floating point vectors to be converted from as this is one of the floating point data formats considered for conversion.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
17958378
17958380
8. A method comprising:
8. A method comprising:
decoding a single instruction, the single instruction to include one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data or single-precision floating point data from the identified source to packed FP8 data and store the packed FP8 data into corresponding data element positions of the identified destination operand; and
decoding a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand,
wherein the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction; and
executing the decoded instruction according to the opcode to convert packed half- precision floating-point data or single-precision floating point data from the identified source to packed FP8 data and store the packed FP8 data into corresponding data element positions of the identified destination operand.
executing the decoded instruction according to the opcode to convert packed half- precision data from the identified first and second source operands to the packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand.
Allowable Subject Matter
For the reasons set forth in the office action dated 03/24/26, claims 3, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 1-2, 4-9, and 11-20 would be allowable if rewritten to overcome the provisional nonstatutory double patenting rejection, and the relevant claim objections.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached on 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Andrew Caldwell can be reached on 571-272-3701. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
Prosecution Insights