DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 6th, 2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on application IN 202241044392, filed on August 3, 2022. It is noted, however, that applicant has not filed a certified copy of the foreign application as required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “INSTRUCTIONS TO CONVERT FROM FP16 TO FP8 USING BIAS TERMS”
The abstract of the disclosure is objected to because of the following informalities:
The abstract exceeds 150 words in length and should be reduced (MPEP 608.01(b)(C)). Examiner recommends that Applicant deletes everything after “opcode” in line 9 since everything after is repeated language.
Lines 6-7 and 10-11: Remove both instances of “packed” prior to “FP8”. It is the examiner’s understanding that data elements are packed when they are in different fields of the same vector register. Prior to packing the data elements into a register, they are not yet packed (into a register), but simply multiple data items.
Line 6: Replace “first and second sources” to “first and second source operands”.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
[0036], line 8: Replace “is to provides” with “is to provide”.
[0040], line 5: Insert “to” after “important”.
[0086]: The descriptions of 515 and 517 do not match with Fig. 5A and should be changed to match with the figure.
[0091], lines 18-19: The descriptions of 525 and 527 do not match with Fig. 5B and should be changed to match with the figure.
[00116], line 6: Insert “computing” after “(throughput)”.
[00126], lines 18-19: “a register maps” is grammatically incorrect.
[00194]: In amendments filed May 5, 2026, a “16.” Is added at the beginning of the paragraph. Examiner believes this is an error and should be deleted.
[00194]: The example embodiments include language used in the claims. For similar reasoning set forth in current/previous claim objections/rejections, there paragraphs should be updated as the claims are updated, particularly where incorrect or unclear.
Appropriate correction is required.
The amended specification, filed on May 5, 2026, does not comply with 37 CFR 1.121(b)(1) as Applicant did not insert any markings to indicate what should be deleted/added. Applicant is advised to re-submit the amendment to include markings to indicate the changes made to the paragraph(s).
Drawings
The lengthy set of drawings has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings.
The drawings are objected to because of the following informalities:
Fig. 4, step 401: For similar reasoning given above for the abstract, Examiner questions whether both instances of “PACKED” prior to “FP8” should be removed.
Fig. 4, steps 403, 407, and 409: There may be more multiple instructions if the translation occurs in step 402. Examiner recommends that each step listed after should change all instances of “INSTRUCTION” to “INSTRUCTION(S)”.
Fig. 4, step 407: For similar reasoning given above for the abstract, Examiner questions whether both instances of “PACKED” prior to “FP8” should be removed.
Fig. 5A, 501: Insert “NO” at the right of the decision path.
Fig. 5A, 505: “INTIAL” is a misspelling and should be changed to “INITIAL”.
Fig. 5B, 519: Insert “NO” at the right of the decision path.
Fig. 6: The code passes “x” into the conversion function, but no instance of “x” was introduced prior to the function being called. Examiner believes that it should be “t” that gets passed into the function.
Fig. 7: The code passes “x” into the conversion function, but no instance of “x” was introduced prior to the function being called. Examiner believes that it should be “t” that gets passed into the function.
Fig. 9: The code passes “x” into the conversion function, but no instance of “x” was introduced prior to the function being called. Examiner believes that it should be “t” that gets passed into the function.
Fig. 10: The code passes “x” into the conversion function, but no instance of “x” was introduced prior to the function being called. Examiner believes that it should be “t” that gets passed into the function.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 831B.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1, lines 7, 9-10, and 16-17: Remove all instances of “packed” prior to “8-bit”. It is the examiner’s understanding that data elements are packed when they are in different fields of the same vector register. Prior to packing the data elements into a register, they are not yet packed (into a register), but simply multiple data items.
Claim 8, lines 7-8, 10, and 14-15: Remove all instances of “packed” prior to “8-bit floating point data”. It is the examiner’s understanding that data elements are packed when they are in different fields of the same vector register. Prior to packing the data elements into a register, they are not yet packed (into a register), but simply multiple data items.
Claim 14, line 3: For similar reasoning given above for claim 8, Examiner questions whether the instance of “packed” prior to “8-bit” should be removed.
Claim 16, lines 6-8 and 15-16: Remove all instances of “packed” prior to “8-bit floating point data”. It is the examiner’s understanding that data elements are packed when they are in different fields of the same vector register. Prior to packing the data elements into a register, they are not yet packed (into a register), but simply multiple data items.
Claims 2-3, 6-7, 9-10, 13-15, and 19-20 are objected to for inheriting the objections of the claims in which they depend on.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 6-7, 10, and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the bias terms" in line 1. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “bias terms” in claim 1, line 8, or “bias terms” in claim 1, line 16. For the sake of examination, Examiner will interpret both limitations in claim 1, line 8, and claim 1, line 16, to be the same limitation.
Claim 10 is rejected for the same reasons as claim 3.
Claim 6 recites the limitation "the execution circuitry" in line 1. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “execution circuitry” in claim 1, line 6, or “execution circuitry” in claim 1, line 13. For the sake of examination, Examiner will interpret both limitations in claim 1, line 8, and claim 1, line 16, to be the same limitation.
Claims 7 and 14 are indefinite because they are inconsistent with the disclosure. The clams set forth using a mask to indicate which of the FP8 data re written into the destination, which suggests that a half-precision value can be converted, but the result may not be written based on the mask. However, Figs. 6-7 and 9-10 show checking the mask first, and, only if the mask indicate to write to a destination element, converting an FP16 value. If the mask is ‘0’, for instance, then the conversion never takes place for that element. As such, there can never be a converted data element (result of conversion) that isn’t written to the destination based on the mask. It is unclear what the invention actually is and it will be interpreted according to the operation of Figs. 6-7 and 9-10 (see MPEP 2173.03). Applicant is advised to point to the relevant portion in the specification/drawings and provide any necessary explanation for how these claims are consistent with that described in the disclosure.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 15 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Parent claim 8 sets forth “decoding the single instruction”, but claim 15 sets forth “translating the single instruction into one or more different instructions prior to decoding”. Therefore, in claim 15, there is no decoding of the single instruction, and instead, there would only be “decoding of the one or more different instruction”. Additionally, the “wherein…” portion of claim 15 seems to be stating that the system is not executing the single instruction as claimed in claim 8. But instead executing the one or more different instruction. As such, Applicant appears to be substituting limitations in claim 15 for limitations in claim 8, Therefore, claim 15 is improper. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 6-10, 13-16, and 19-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1, 8, and 16 recite an apparatus, a method, and a non-transitory machine-readable medium, respectively. Thus, each of the claims fall under one of the four statutory categories.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), claim 1 recites “convert packed half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms” and “the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction.” Such limitations cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. Therefore the claim includes limitations that fall within the “mental processes” groupings of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The elements “decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to include one or more field to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode” and “execution circuitry, comprising dedicated conversion combinational logic, to execute the decoded instruction according to the opcode” are recited at a high level of generality, i.e., generic computer elements. Such elements amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). Alternatively, the elements amount to no more than generally linking the abstract idea to a technological environment/field of use (e.g., SIMD/vector/parallel computing areas) (MPEP 2106.05(h)). Additionally, the claim recites “store the packed 8-bit floating point data into corresponding data element positions”, which is considered to be an insignificant extra-solution activity of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory) and does not integrate the abstract idea into a practical application. Thus, the elements fails to integrate the judicial exception into a practical application.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to Step 2A Prong Two, the additional elements “decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to include one or more field to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode” and “execution circuitry, comprising dedicated conversion combinational logic, to execute the decoded instruction according to the opcode” amount to no more than mere instructions to apply the exception (see MPEP 2106.05(f)). The additional element “store the packed 8-bit floating point data into corresponding data element positions” is an insignificant step of storing data in memory and has been deemed to be well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 2, the claim recites “the first and second source operands are vector registers.” The element amounts to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)). Alternatively, the element amounts to no more than generally linking the abstract idea to a technological environment/field of use (e.g., SIMD/vector/parallel computing areas) (MPEP 2106.05(h)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 3, the claim recites “the bias terms are 8-bit values.” Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 6, the claim recites “to use a variable bias to convert.” Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim additionally recites “the execution circuitry”, which amounts to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)). Therefore, the claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 7, the claim recites “the single instruction is to further include one or more fields to identify a writemask operand” and “one or more bits of the writemask operand are to indicate… which of the converted 8-bit floating point data values are to be written in the source/destination operand.” The elements further cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 8, the claim is mostly rejected for the same reasons as claim 1. The claim also recites “dedicated conversion circuitry”. The element is recited at a high level of generality, i.e., generic computer elements, which amounts to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claims 9-10 and 13-14, the claims recite a method similar to the apparatus of claims 2-3 and 6-7, respectively. Therefore, claims 9-10 and 13-14 are rejected on the same premises.
Regarding claim 15, the claim recites “translating the single instruction into one or more instructions of a different instruction set architecture prior to decoding” and “the one or more instructions of the different instruction set architecture is to be functionally equivalent as the executing according to the opcode of the single instruction.” Such limitations further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 16, the claim is mostly rejected for the same reasons as claim 1. The claim also recites “dedicated conversion circuitry” and “non-transitory machine-readable medium storing an instance of a single instruction”. The elements are recited at a high level of generality, i.e., generic computer elements, which amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). Furthermore, the element “non-transitory machine-readable medium storing an instance of a single instruction” is considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory), and is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claims 19-20, the claims recite a method similar to the apparatus of claims 6 and 2, respectively. Therefore, claims 19-20 are rejected on the same premises.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 6-10, 13-16, and 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 1, 7-10, 8, 14-16, 16, and 20 of U.S. Patent No. 12,135,968 (hereinafter ‘968) in view of Sun et al. (“Hybrid 8-bit Floating Point (HFP8) Training and Inference for Deep Neural Networks”, see Non-Final Office Action mailed September 3 2025) and Henry et al. (US 20210089303 A1)
Regarding claim 1, ‘968 teaches an apparatus comprising:
decoder circuitry to decode an instance of a single instruction (Claim 1: A single instruction can be seen as an instance of an instruction), the instance of the single instruction to include one or more fields to identify a first source operand (see Claim 1), one or more fields to identify a second source operand (see Claim 1), one or more fields to identify a source/destination operand (see Claim 1), and one or more fields for an opcode (see Claim 1), wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand (Claim 1: bfloat8 is a type of 8-bit floating point data); and
execution circuitry to execute the decoded instance of the single instruction according to the opcode to convert packed half-precision data from the identified first and second source operands to the packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand (see Claim 1).
‘968 does not teach that the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction
Sun teaches that the 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction (Page 1, Section 1, Paragraph 1 and Page 3, Section 1.2, Paragraph 2: FP8 format with 1 bit for exponent, 4 bits for exponent, and 3 bits for mantissa).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combine the teachings of ‘968 with the teachings of Tatsumi to have made the packed 8-bit floating point data have one bit for a sign, four bits for an exponent, and three bits for a fraction. Using the 4-bit exponent and 3-bit mantissa 8-bit floating point format provides greater results for forward propagation in deep neural network training (see Sun, Page 5, Fig. 3) compared to using 32-bit floating point format, which one of ordinary skill would appreciate.
However, ‘968, in view of Sun, still does not explicitly teach that the execution circuitry comprises of dedicated conversion combinational logic.
Henry teaches execution circuitry comprising of dedicated conversion combinational logic (Claim 1: Execution circuitry comprises of conversion hardware logic, which is used to perform floating-point data format and used in combination with the execution circuitry to perform matrix data conversion and matrix multiplication. Therefore, the conversion hardware logic is dedicated conversion combinational logic).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of ‘968, in view of Sun, with the teachings of Henry to have the execution circuitry include dedicated conversion combinational logic to perform the FP16 to FP8 data format conversion. By having separate dedicated conversion logic, the logic may be easier to design because it only needs to perform the conversion function as opposed to the conversion function and any other functions one may want the logic to handle. Furthermore, making separable units, i.e., separating non-dedicated logic into multiple dedicated logic, is considered to be a routine expedient, not a patentable distinction (MPEP 2144.04(V)(C)).
Regarding claim 2, ‘968, in view of Sun and Henry, teaches the apparatus of claim 1, wherein the first and second source operands are vector registers (‘968, see Claim 2).
Regarding claim 3, ‘968, in view of Sun and Henry, teaches the apparatus of claim 1, wherein the bias terms are 8-bit values (‘968, see Claim 3).
Regarding claim 6, ‘968, in view of Sun and Henry, teaches the apparatus of claim 1, wherein the execution circuitry is to use a variable bias to convert (‘968, Claim 1: The claim recites using the source/destination operand to indicate the bias terms to be used for each data element when converting, hence the execution circuitry uses a bias that varies for each data element (i.e., a variable bias)).
Regarding claim 7, ‘968, in view of Sun and Henry, teaches the apparatus of claim 1, wherein the single instruction is further to include one or more fields to identify a writemask operand, wherein one or more bits of the writemask operand are to indicate to execution circuitry which of the converted 8-bit floating point data values are to be written in the source/destination operand (‘968, see Claim 7).
Regarding claims 8, ‘968 teaches a method comprising:
decoding a single instruction (see Claim 8), the single instruction to include one or more fields to identify a first source operand (see Claim 8), one or more fields to identify a second source operand (see Claim 8), one or more fields to identify a source/destination operand (see Claim 8), and one or more fields for an opcode (see Claim 8), wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand (Claim 8: Bfloat8 is a type of 8-bit floating point data); and
executing the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second source operands to the packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand.
‘968 does not teach that the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction
Sun teaches that the 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction (Page 1, Section 1, Paragraph 1 and Page 3, Section 1.2, Paragraph 2: FP8 format with 1 bit for exponent, 4 bits for exponent, and 3 bits for mantissa).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combine the teachings of ‘968 with the teachings of Tatsumi to have made the packed 8-bit floating point data have one bit for a sign, four bits for an exponent, and three bits for a fraction. Using the 4-bit exponent and 3-bit mantissa 8-bit floating point format provides greater results for forward propagation in deep neural network training (see Sun, Page 5, Fig. 3) compared to using 32-bit floating point format, which one of ordinary skill would appreciate.
However, ‘968, in view of Sun, still does not explicitly teach that the execution circuitry comprises of dedicated conversion circuitry.
Henry teaches execution circuitry comprising of dedicated conversion circuitry (Claim 1: Claim 1: Execution circuitry comprises of conversion hardware logic (in which hardware logic refers to a type of circuitry), which is used to perform floating-point data format and used in combination with the execution circuitry to perform matrix data conversion and matrix multiplication. Therefore, the conversion hardware logic is dedicated conversion circuitry).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of ‘968, in view of Sun, with the teachings of Henry to have the execution circuitry include dedicated conversion circuitry to perform the FP16 to FP8 data format conversion. By having separate dedicated conversion circuitry, the circuitry may be easier to design because it only needs to perform the conversion function as opposed to the conversion function and any other functions one may want the circuitry to handle. Furthermore, making separable units, i.e., separating non-dedicated circuitry into multiple dedicated circuitry, is considered to be a routine expedient, not a patentable distinction (MPEP 2144.04(V)(C)).
Regarding claim 9, ‘968, in view of Sun and Henry, teaches the method of claim 8, wherein the identifier of the first source operand is to identify a vector register (‘968, see Claim 9).
Regarding claim 10, ‘968, in view of Sun and Henry, teaches the method of claim 8, wherein the bias terms are 8-bit values (‘968, see Claim 10).
Regarding claim 13, ‘968, in view of Sun and Henry, teaches the method of claim 8, wherein the execution circuitry is to use a variable bias to convert (‘968, Claim 8: The claim recites using the source/destination operand to indicate the bias terms to be used for each data element when converting, hence the execution circuitry uses a bias that varies for each data element (i.e., a variable bias)).
Regarding claim 14, ‘968, in view of Sun and Henry, teaches the method of claim 8, wherein the single instruction is further to include one or more fields to identify a writemask operand, wherein one or more bits of the writemask operand are to indicate to execution circuitry which of the converted packed 8-bit floating point data values are to be written in the source/destination operand (‘968, see Claim 14).
Regarding claim 15, ‘968, in view of Sun and Henry, teaches the method of claim 8, further comprising translating the single instruction into one or more instructions of a different instruction set architecture prior to decoding, wherein executing of the one or more instructions of the different instruction set architecture is to be functionally equivalent as the executing according to the opcode of the single instruction (‘968, see Claim 15).
Regarding claim 16, the claim is rejected for the same reasons as claim 8, using claim 16 of ‘968.
Regarding claim 19, ‘968, in view of Sun and Henry, teaches the non-transitory machine-readable medium of claim 16, wherein the execution circuitry is to use a variable bias to convert (‘968, Claim 16: The claim recites using the source/destination operand to indicate the bias terms to be used for each data element when converting, therefore the execution circuitry uses a bias that varies for each data element (i.e., a variable bias)).
Regarding claim 20, ‘968, in view of Sun and Henry, teaches the non-transitory machine-readable medium of claim 16, wherein the identifier of the first source operand is to identify a vector register (‘968, see Claim 20).
Allowable Subject Matter
Claims 1-3, 6-10, 13-16 and 19-20 are allowed, over the prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1, 8, and 16 recite, among other things, convert half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms from the identified source/destination operand. The closest prior art, Heinecke et al. (US 20190079762 A1), teaches to convert single-precision data elements to half-precision data elements using a rounding bias. Heinecke does not teach to use bias terms from a source/destination operand to perform a conversion of half-precision data elements to 8-bit floating point data elements. Examiner has found no additional prior art that would motivate one of ordinary skill in the art before the effective filing date to modify Heinecke to use bias terms stored in a source/destination operand to perform the conversion.
.
Response to Arguments
Regarding Applicant’s amendments, filed July 6, 2026, with respect to the specification have been fully addressed. The specification objections have been withdrawn. However, new specification objections have been raised. See “Specification” section above.
Regarding Applicant’s amendments, filed July 6, 2026, with respect to the drawings have been mostly addressed. A drawing objection is maintained and multiple drawing objections have been raised. See “Drawings” section above.
Applicant’s arguments, see Pages 9-10, filed July 6, 2026, with respect to the rejections of claims 1-3, 5-10. 12-16, and 18-20 under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding arguments on Page 6, last paragraph, Applicant argues that the Examiner did not address the particular argument.
Examiner respectfully disagrees. Examiner has responded to this argument in the Advisory Action mailed May 19, 2026. Examiner believes the argument was “Because the claimed hardware circuitry and instruction execution cannot be practically performed in the human mind, the claims do not recite a mental process under MPEP 2106.04(a)(2).” If Applicant still believes a particular argument remains unaddressed, Examiner respectfully requests that Attorney identify the specific argument or clarify which portion of the response is believed to be insufficiently addressed.
Regarding arguments on page 7, paragraph 1, Applicant argues that the claims integrate any alleged abstract idea into a practical application.
Examiner respectfully disagrees. For reference, MPEP 2106.05(a) states that "it is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below [with respect to 2106.05(a)]" and "it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology. See MPEP § 2106.04(d) (discussing Finjan, Inc. v. Blue Coat Sys., Inc., 879 F.3d 1299, 1303-04, 125 USPQ2d 1282, 1285-87 (Fed. Cir. 2018))" The “improvement" mentioned is not provided by any additional elements as such additional elements, both alone and in combination, analyzed under Step 2A Prong Two and Step 2B does not improve on anything (or to clarify further, the additional elements do not provide the improvement that the Applicant claims). Instead, the additional elements are either recited at a high level of generality, amounting to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)), or are considered to be an insignificant extra-solution activity of data gathering (MPEP 2106.05(g)), which is deemed to be considered well-understood, conventional, and routine by the courts (MPEP 2106.05(d)). As it stands, only the abstract idea provides the "improvement" of the invention as a whole. Furthermore, the elements "a single instruction with defined field" and "decoder and execution circuitry" are recited at a high level and therefore do not integrate the exception into a practical application. Therefore, the argument regarding that the claims integrate any alleged abstract idea into a practical application is considered not persuasive.
Regarding arguments on page 7, paragraph 2, Applicant’s argument selectively addresses a portion of the Examiner’s response to Applicant’s arguments, but does not rebut the response as a whole. For clarity, Examiner has included court citations above that correspond to each quote that Examiner used from MPEP 2106.05(a).
Regarding arguments on page 7, paragraph 3, Applicant argues that the elements have to exist to be “well-understood, routine and conventional in the field”.
Examiner respectfully disagrees with this argument. First, Applicant’s specification does not describe, in detail, of storing the converted data into respective positions of an operand. This is an indication that both the element exists and is WURC (see MPEP 2106.05(d)(I)(2), paragraph two). Second, MPEP 2106.05(d)(I) states that “[a] factual determination is required to support a conclusion that an additional element (or combination of additional elements) is well-understood, routine, conventional activity. Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018).” In other words, to conclude that an element is well-understood, routine, and conventional, a factual determination, such as pointing to what the courts have recognized, is enough to indicate an element is WURC. Moving/storing data into operands is well-known in the art, evidenced by the courts (see MPEP 2106.05(d)(II)(iv); iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). Therefore, the argument regarding that the elements have to exist to be “well-understood, routine and conventional in the field” is considered not persuasive.
Regarding arguments on page 8, paragraph 1, Applicant argues that the claimed instructions and support thereof are not WURC.
Note that in Examiner’s analysis of the claims under 101, the claim limitation “store the packed 8-bit floating point data into corresponding data element positions” is the well-understood, routine and conventional element. Examiner did not indicate all elements of the instruction is WURC, but rather that most elements fall under being mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). See 101 analysis for complete details.
Regarding arguments on page 8, paragraph 2, Applicant argues that there is no “pre-“ or “post-“ solution in the claims.
Examiner respectfully disagrees with this argument. See MPEP 2105.05(g) regarding insignificant extra-solution activities. “store the packed 8-bit floating point data into corresponding data element positions” is a tangential (i.e., not the main focus of the claim), post-solution element in the claims. After performing an operation on data, the operated data should be stored back into the processor, which may be a register or a memory location. This is a common post-solution activity that’s, at least, insignificant extra-solution activity that’s WURC by the courts. Therefore, the argument regarding that there is no “pre-“ or “post-“ solution in the claims is considered not persuasive.
Regarding arguments on page 8, paragraph 2, Applicant argues that the claim elements are not generic computer elements that are well understood routine, and conventional.
As previously stated, Examiner did not indicate all elements as being WURC, only the limitation “store the packed-bit floating point data into corresponding data element positions” is WURC. Examiner has provided the evidence of the element being WURC in the 101 analysis above. As for the “generic computer elements” part, Examiner has explained their position in the Advisory Action mailed May 19, 2026, and will not repeat those arguments for the sake of brevity. Therefore, the argument regarding that the claim elements are not generic computer elements that are well understood routine, and conventional is considered not persuasive.
Applicant may have misunderstood Examiner’s 101 analysis based on Examiner indicating that one of the elements is WURC and may have assumed that Examiner indicated that all elements are WURC. Examiner makes the emphasis that only “store the packed 8-bit floating point data into corresponding data element positions” is WURC. All other elements that were indicated by Examiner in the independent claims falls under mere instructions to apply the exception (MPEP 2106.05(f)) or generally linking the abstract idea to a technological environment/field of use (MPEP 2106.05(h)). In the Advisory Action mailed May 19, 2026, Examiner indicated that Applicant pointed to a court case without explaining how it corresponded to their case. After recognizing Applicant’s potential misunderstanding and re-reviewed Applicant’s arguments, Examiner believes that the use of the court case does not validate Applicant’s arguments as it stems from Applicant’s potential misunderstanding of Examiner’s 101 analysis. If Applicant believes Examiner misunderstood their use of the court case, Applicant should point to the specifics of the court case and explain how it’s related to their case.
Regarding arguments on page 8, paragraph 4 to page 9, paragraph 1, Applicant argues that “the claims are not directed to “mere instructions” and could never be directed as such as these instructions of the specification have never existed”.
Examiner respectfully disagrees with this argument. See MPEP 2106.05(f) regarding mere instruction to apply an exception. The purpose of MPEP 2196.05(f) is to prevent Applicants from applying an exception to a computer without providing an improvement to the functioning of a computer/technological field (in which the improvement does not come from the abstract idea itself). In this instance, the claims are read to the extent that a processor is used to perform floating-point conversion, which falls under “mere instructions” to apply an exception. Therefore, the argument regarding that the claims are not directed to “mere instructions” is considered not persuasive.
With claims 5, 12, and 18 canceled, the rejections of claims 1-3, 6-10. 13-16, and 19-20 under 35 U.S.C. 101 are being maintained.
Conclusion
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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