DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on application IN 202241044392, filed on August 3, 2022. It is noted, however, that applicant has not filed a certified copy of the foreign application as required by 37 CFR 1.55.
Drawings
The lengthy set of drawings has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings.
Examiner makes the following recommendations:
Fig. 2: “Packed Data Source 1 (SRC2) 201” should be corrected to “Packed Data Source 1 (SRC1) 201” to improve clarity.
Fig. 4, 401: For better flow/readability, Examiner recommends that Applicant changes the phrase “fetch an instruction at least having” to “fetch an instruction having at least”.
Fig. 4, 401: Remove the extra space after “a source/destination operand” and before the comma.
Fig. 4, 401: Change the phrase “the first and second sources” to instead read “the first and second source operands” to improve clarity.
Fig. 4, 401: Change the phrase “the identified source/destination” to instead read “the identified source/destination operand” to improve clarity.
Fig. 4, 407: The word “onvert” is a mis-spelling and should be changed to “convert”.
Fig. 4, 407: Change the phrase “the first and second sources” to instead read as “the first and second source operands” to improve clarity.
Fig. 4, 407: Change the phrase “the identified source/destination” to instead read as “the identified source/destination operand” to improve clarity.
Fig. 8: The element “Packed Data Source 1 (SRC2)” at 201 should be changed to “Packed Data Source 1 (SRC1)” for clarity.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because of the following issues:
Reference character “201” has been used to designate both a vector of FP16 data values and FP32 data values.
Reference character “1203” has been used to designate both a vector of FP16 data values and FP32 data values.
Reference character “211” has been used to designate both a FP16 to FP8 combinational logic and FP32 to FP8 combinational logic.
The drawings are further objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 203, 801, 803, 809, 811, 831(A), 831, 1801.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because of the following informalities:
Line 1: For the sake of consistency with the disclosure, ”BF8” should be changed to “FP8”.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
[00194]: The example embodiments suffer the same issues as the claim rejections and should be fixed when appropriate.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 9, 11, 17, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “the identifier of the first source operand”. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of an “identifier of the first source operand” within the claim itself or the claim it depends on. For the sake of examination, Examiner is interpreting this limitation to be “an identifier of the first source operand”.
Claim 20 is rejected for the same reasons above.
Claims 4, 11, and 17 recite the limitation “the packed 8-bit floating point data has a format of 1-bit sign, 5-bit exponent, and 2-bit fraction”. It’s unclear of what the structure of the “the packed 8-bit floating point data” is as the structure defined in the independent claims is different than what’s recited in the dependent claims. For the sake of examination, Examiner will not examine the claims mentioned until the claims are amended in a way that clears up any confusion.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5, 12, and 18 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claims 5, 12, and 18, the dependent claims do not further limit the independent claim as they merely recite the structure of the “packed 8-bit floating point data”, which was already defined in their respective independent claims.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5-10, 12-16, and 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1, 8, and 16 recite an apparatus, a method, and a non-transitory machine-readable medium, respectively. Thus, each of the claims fall under one of the four statutory categories.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), claim 1 recites “convert packed half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms” and “the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction.” Such limitations cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. Therefore the claim includes limitations that fall within the “mental processes” groupings of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The elements “decoder circuitry to decode a single instruction, the single instruction to include one or more field to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode” and “execution circuitry to execute the decoded instruction according to the opcode” are recited at a high level of generality, i.e., generic computer elements performing generic computer operations. Such elements amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). Additionally, the claim recites “store the packed 8-bit floating point data into corresponding data element positions”, which is considered to be an insignificant extra-solution activity of data gathering (i.e., reading or loading data from memory) (MPEP 2106.05(g)) and does not integrate the abstract idea into a practical application. Thus, the elements fails to integrate the judicial exception into a practical application.
Under Step 2B, the claims to not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to Step 2A Prong Two, the additional elements in the claim amount to no more than mere instructions to apply the exception (see MPEP 2106.05(f)) and the additional elements that does not amount to significantly more as data gathering has been deemed to be well-understood, conventional, and routine by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim does not provide an inventive concept. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 recites “the first and second source operands are vector registers.” Such element amount to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), and fails to integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 recites “the bias terms are 8-bit values.” Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 recites “the packed 8-bit floating point data has a format of 1-bit sign, 4-bit exponent, and 3-bit fraction.” Such limitations further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 recites “to use a variable bias to convert.” Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim additionally recites “the execution circuitry”, which amounts to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)). Therefore, the claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 recites “the single instruction is to further include one or more fields to identify a writemask operand” and “one or more bits of the writemask operand are to indicate execution circuitry which of the converted 8-bit floating point data values are to be written in the source/destination operand.” Such elements further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). Such element amount to no more than mere instructions to apply the exception, i.e., generic computer elements performing generic computer operations (MPEP 2106.05(f)), and fails to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 8-10 and 12-14 recite a method similar to the apparatus of claims 1-3 and 5-7, respectively. Therefore, claims 8-10 and 12-14 are rejected on the same premises.
Claim 15 recites “translating the single instruction into one or more instructions of a different instruction set architecture prior to decoding” and “the one or more instructions of the different instruction set architecture is to be functionally equivalent as the executing according to the opcode of the single instruction.” Such limitations further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrate the judicial exception into a practical application under Step 2A Prong Two, and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 16 and 18-20, recite a method similar to the apparatus of claims 1, 5-6, and 2, respectively. Therefore, claims 16 and 18-20 are rejected on the same premises.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5-10, 12-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 1, 1, 7-10, 8, 8, 14-16, 16, 16, and 20 of U.S. Patent No. 12,135,968 (hereinafter ‘968) in view of Sun et al. (“Hybrid 8-bit Floating Point (HFP8) Training and Inference for Deep Neural Networks”, see Non-Final Office Action mailed September 3 2025)
Regarding claim 1, ‘968 teaches an apparatus comprising:
decoder circuitry to decode a single instruction (see Claim 1), the single instruction to include one or more fields to identify a first source operand (see Claim 1), one or more fields to identify a second source operand (see Claim 1), one or more fields to identify a source/destination operand (see Claim 1), and one or more fields for an opcode (see Claim 1), wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second source operands to packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand (Claim 1: bfloat8 is a type of 8-bit floating point data); and
execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second source operands to the packed 8-bit floating point data using bias terms from the identified source/destination operand and store the packed 8-bit floating point data into corresponding data element positions of the identified source/destination operand (see Claim 1).
‘968 does not teach that the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction
Sun teaches that the 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction (Page 1, Section 1, Paragraph 1 and Page 3, Section 1.2, Paragraph 2: FP8 format with 1 bit for exponent, 4 bits for exponent, and 3 bits for mantissa).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combine the teachings of ‘968 with the teachings of Tatsumi to have made the packed 8-bit floating point data have one bit for a sign, four bits for an exponent, and three bits for a fraction. Using the 4-bit exponent and 3-bit mantissa 8-bit floating point format provides greater results for forward propagation in deep neural network training (see Sun, Page 5, Fig. 3) compared to using 32-bit floating point format, which one of ordinary skill would appreciate.
Regarding claim 2, ‘968, in view of Sun, teaches the apparatus of claim 1, wherein the first and second source operands are vector registers (‘968, see Claim 2).
Regarding claim 3, ‘968, in view of Sun, teaches the apparatus of claim 1, wherein the bias terms are 8-bit values (‘968, see Claim 3).
Regarding claim 5, ‘968, in view of Sun, teaches the apparatus of claim 1, wherein the packed 8-bit floating point data has a format of 1-bit sign, 4-bit exponent, and 3-bit fraction (see Claim 1 rejection).
Regarding claim 6, ‘968, in view of Sun, teaches the apparatus of claim 1, wherein the execution circuitry is to use a variable bias to convert (‘968, Claim 1: The claim recites using the source/destination operand to indicate the bias terms to be used for each data element when converting, hence the execution circuitry uses a bias that varies for each data element (i.e., a variable bias)).
Regarding claim 7, ‘968, in view of Sun, teaches the apparatus of claim 1, wherein the single instruction is further to include one or more fields to identify a writemask operand, wherein one or more bits of the writemask operand are to indicate to execution circuitry which of the converted 8-bit floating point data values are to be written in the source/destination operand (‘968, see Claim 7).
Regarding claims 8, the claim is rejected for the same reasons as claim 1, using claim 8 of ‘968.
Regarding claim 9, ‘968, in view of Sun, teaches the method of claim 8, wherein the identifier of the first source operand is to identify a vector register (‘968, see Claim 9).
Regarding claim 10, ‘968, in view of Sun, teaches the method of claim 8, wherein the bias terms are 8-bit values (‘968, see Claim 10).
Regarding claim 12, ‘968, in view of Sun, teaches the method of claim 8, wherein the packed 8-bit floating point data has a format of 1-bit sign, 4-bit exponent, and 3-bit fraction (see Claim 8 rejection).
Regarding claim 13, ‘968, in view of Sun, teaches the method of claim 8, wherein the execution circuitry is to use a variable bias to convert (‘968, Claim 8: The claim recites using the source/destination operand to indicate the bias terms to be used for each data element when converting, hence the execution circuitry uses a bias that varies for each data element (i.e., a variable bias)).
Regarding claim 14, ‘968, in view of Sun, teaches the method of claim 8, wherein the single instruction is further to include one or more fields to identify a writemask operand, wherein one or more bits of the writemask operand are to indicate to execution circuitry which of the converted packed 8-bit floating point data values are to be written in the source/destination operand (‘968, see Claim 14).
Regarding claim 15, ‘968, in view of Sun, teaches the method of claim 8, further comprising translating the single instruction into one or more instructions of a different instruction set architecture prior to decoding, wherein executing of the one or more instructions of the different instruction set architecture is to be functionally equivalent as the executing according to the opcode of the single instruction (‘968, see Claim 15).
Regarding claim 16, the claim is rejected for the same reasons as claim 1, using claim 16 of ‘968.
Regarding claim 18, ‘968, in view of Sun, teaches the non-transitory machine-readable medium of claim 16, wherein the packed 8-bit floating point data has a format of 1-bit sign, 4-bit exponent, and 3-bit fraction (see Claim 16 rejection).
Regarding claim 19, ‘968, in view of Sun, teaches the non-transitory machine-readable medium of claim 16, wherein the execution circuitry is to use a variable bias to convert (‘968, Claim 16: The claim recites using the source/destination operand to indicate the bias terms to be used for each data element when converting, therefore the execution circuitry uses a bias that varies for each data element (i.e., a variable bias)).
Regarding claim 20, ‘968, in view of Sun, teaches the non-transitory machine-readable medium of claim 16, wherein the identifier of the first source operand is to identify a vector register (‘968, see Claim 20).
Response to Arguments
Regarding Applicant’s amendments, filed January 5 2026, with respect to the specification have not been fully addressed. Applicant indicates confusion regarding the terminology used for each objection. Therefore, Examiner has clarified the objections to be in-line with 37 CFR 1.71(a) such that the application uses “full, clear, concise, and exact terms.” The specification objections are being maintained.
Regarding Applicant’s amendments, filed January 5 2026, with respect to the drawings have not been fully addressed. The replacement drawings filed suffer the same issues as the original drawings filed October 1 2022. Applicant indicates confusion regarding the terminology used for some of the objections. Therefore, Examiner has withdrawn the informal objections and have turned them into recommendations to be considered for the drawings. Certain objections still stand in-line with 37 CFR 1.84 and are being maintained
Regarding Applicant’s amendments, filed January 5 2026, with respect to the claim objections have been addressed. The objections of claims 1-20 has been withdrawn.
Applicant’s arguments, see Pages 9-10, filed January 5 2026, with respect to the rejections of claims 1-3, 5-10. 12-16, and 18-20 under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding arguments on Page 9, last paragraph, Applicant argues that the claimed invention of converting 8-bit floating point values is an improvement to the function of a computer.
Examiner respectfully disagrees with this argument. For reference, MPEP 2106.05(a) states that "It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements." and "it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology". The “improvement” mentioned is not provided by any additional elements as such additional elements analyzed under Step 2A Prong Two and Step 2B does not “improve” on anything. Instead, the additional elements are either recited at a high level of generality, amounting to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)), or are considered to be an insignificant extra-solution activity of data gathering (MPEP 2106.05(g)), which is deemed to be considered well-understood, conventional, and routine by the courts (MPEP 2106.05(d)). As it stands, only the abstract idea provides the “improvement” of the invention as a whole. Therefore, the argument regarding that the claimed invention indicated the improvement to the function of a computer is considered not persuasive.
Regarding arguments on Page 10, second paragraph, Applicant argues that the Office did not perform the proper evaluation required by the MPEP, such as MPEP 2106.04(d)(1).
Examiner respectfully disagrees with this argument. Examiner has performed the proper analysis of all claims for patent subject matter eligibility by analyzing each claim under Step 1, Step 2A Prong One, Step 2A Prong Two, and Step 2B. MPEP 2106.04(d)(1) evaluation falls under Step 2A. Therefore, the remarks regarding that the Office did not perform the proper evaluation required by the MPEP is considered not persuasive.
The rejections of claims 1-3, 5-10. 12-16, and 18-20 under 35 U.S.C. 101 are being maintained.
Regarding Applicant’s amendments, filed January 5 2026, with respect to the 112(b) rejections raised by the Examiner have been mostly addressed. The 112(b) rejections of claims 4, 11, and 17 have not been properly addressed and the amendments in claims 9 and 20 has raised new 112(b) rejections. The 112(b) rejections of claims 1-3, 5-8, 10, 12-16, and 18-19 have been withdrawn and the 112(b) rejections of claims 4, 9, 11, 17, and 20 are being maintained.
Applicant’s arguments, see Page 10, filed January 5 2026, with respect to the rejections of claims 5, 12, and 18 under 35 U.S.C. 112(d) have been fully considered but they are not persuasive.
Regarding arguments on Page 10, fifth paragraph, Applicant argues that the amendments to the independent claims renders the rejections moot.
Examiner respectfully disagrees with this argument. Each of the independent claims state “the packed 8-bit floating point data has one bit for a sign, four bits for an exponent, and three bits for a fraction” and each of the dependent claims with the rejection state “the packed 8-bit floating point data has a format of 1-bit sign, 4-bit exponent, and 3-bit fraction”. The limitation of the dependent claims in question do not further limit their respective independent claims. Therefore, the argument regarding that the amendments to the independent claims make the 112(d) rejections moot is considered not persuasive.
The 112(d) rejections are being maintained until the issues have been addressed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/ Supervisory Patent Examiner, Art Unit 2183