Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed November 19th, 2025 does not place the application in condition for allowance.
The 112(b) rejection of claim 24 has been withdrawn due to Applicant’s amendment.
The rejections over Hekmatshoar-Tabari et al. are maintained.
New rejections follow.
Election/Restrictions
Newly submitted claim 44 is directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Invention I (claims 24-26, 28, 30-33, 35-43) and Invention II (claim 44) are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the product as claimed can be made by another and materially different process such as one that does not require using a source gay containing silicon to a high-temperature apparatus, or one that is utilizing heat treatments to diffuse dopants.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 44 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 24-26, 28, 30-33, and 35-43 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 24, Applicant recites, “a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%”. Applicant discloses in the instant specification that the first layer 201 and the second layer 202, which have similar doping concentrations (e.g. doping concentrations having a difference within 30%, Instant Specification – Paragraph 0097). Applicant has not disclosed that its specifically greater than 0, or less than 30, e.g., excluding the values of 0% and 30%, specifically. Accordingly, the claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Appropriate action is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 24-26, 28, 30-33, and 35-43 are rejected under 35 U.S.C. 103 as being unpatentable over Hekmatshoar-Tabari et al. (US 2012/0318336 A1) in view of Chang et al. (US 2014/0299187 A1) in view of Yano (US 2015/0059839 A1) in view of Graff (US 2012/0322199 A1).
In view of Claim 24, Hekmatshoar-Tabari et al. discloses a solar cell (Figure 3) comprising:
a single crystalline semiconductor substrate (Figure 3, n-type c-Si Substrate);
a first conductive area formed on a first surface of the single crystalline semiconductor substrate (Figure 3, #230) that comprises a first semiconductor layer and a second semiconductor layer (Paragraph 0030 – the layers can be selected to be intrinsic e.g. not doped) sequentially stacked in a thickness direction (Figure 3, #232 & Paragraph 0035),
wherein a thickness of the first polycrystalline semiconductor layer can be selected to be greater than a thickness of the second polycrystalline semiconductor layer (Paragraph 0037 – the layers 242 and 244 are selected to be in the range of 1-20nm);
Hekmatshoar-Tabari et al. does not disclose that a tunneling layer is formed on a first surface of the single crystalline semiconductor substrate.
Chang et al. discloses a tunneling layer formed on a first surface of a single crystalline semiconductor substrate for the advantages of passivating the surface of the semiconductor substrate that has many recombination sites and facilitates the transfer of carriers through a tunneling effect (Figure 13, #44 & Paragraph 0056-0057). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a tunneling layer formed on a first surface of the single crystalline semiconductor substrate for the advantages of passivating the surface of the semiconductor substrate that has many recombination sites and facilitates the transfer of carriers through a tunneling effect.
Modified Hekmatshoar-Tabari et al. does not disclose an interface layer interjected between the doped and undoped semiconductor layers such that the interface layer is in oxide layer having a higher oxygen concentration than each of the doped and undoped semiconductor layers and having a less oxygen concentration than the tunneling layer and that a thickness of the interface layer is less than a thickness of any one of the first semiconductor layer, the second semiconductor layer and the tunneling layer.
Yano discloses an interface layer (Figure 1, #33) that is interjected between first and second semiconductor layers (Figure 1, #21-#22), wherein the interface layer is an oxide layer that has an oxygen concentration that can be 1.5 times the oxygen concentration in adjacent silicon layers (Paragraph 0018) and can have a thickness of 0.5 nm (Paragraph 0019). Yano discloses that the interface layer advantageously prevents diffusion of hydrogen, dopants, and so on between the formation of adjacent semiconductor layers and thus the influence between adjoining layers can be reduced (Paragraph 0017). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the interface layer of Yano interjected between the doped and undoped semiconductor layers of Hekmatshoar-Tabari et al. for the advantages of preventing diffusion of hydrogen, dopants, and so on between the formation of adjacent semiconductor layers and thus the influence between adjoining layers can be reduced.
In regards to the limitation that the interface layer has “less oxygen concentration that the tunneling layer”. Applicant discloses that the first and second semiconductor layers comprise amorphous or polycrystalline silicon (Paragraph 0033) and wherein the oxygen concentration of the interface layer is at least 1.5 times the oxygen concentration in the first and second semiconductor layer (Paragraph 0038). Yano discloses an interface layer (Figure 1, #33) that is interjected between first and second semiconductor layers (Figure 1, #21-#22), wherein the interface layer is an oxide layer that has an oxygen concentration that can be 1.5 times the oxygen concentration in adjacent amorphous silicon layers (Paragraph 0018). It is the Examiner’s position that the oxygen content of the interface layer as disclosed by Yano would have a oxygen concentration less than the tunneling layer when the interface layer is at least 1.5 times the concentration of oxygen of the adjacent first and second polycrystalline layers of Hekmatshoar-Tabari.
Hekmatshoar-Tabari et al. discloses the doped and undoped layers (Fig. 3, #230 – comprising alternating doped or undoped layers) are deposited via CVD or plasma enhanced vapor deposition or other methods may be employed (Paragraph 0049), although is silent upon “a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%”, as there is no mention of the temperature of the deposition of the doped and undoped layers of Hekmatshoar-Tabari. Graff discloses polysilicon layers depositing via LPCVD that are deposited at temperatures higher than 600 °C (Paragraph 0022) and also discloses that this method can deposit undoped layers with higher uniformity (Paragraph 0030) and that this method improves the manufacturing of polysilicon with reduced recombination carriers within the substrate (0009-0010). Accordingly, it would have been obvious to use Graff’s deposition method to deposit the doped and undoped layers of Hekmatshoar-Tabari et al. at temperatures higher than 600 °C for the advantage of depositing the undoped layer w/ higher uniformity and utilizing an improved method with reduced recombination carriers within the substrate.
In regards to the limitation, “and a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%”. Applicant discloses that when a doped semiconductor layer (Fig. 3E, #202a) is deposited over an undoped semiconductor layer (Fig. 3E, #201a) using vapor deposition at temperatures of 600 degrees Celsius or more, that dopants diffuse from the doped semiconductor layer 202a to the undoped semiconductor layer 201a (Instant Specification – Paragraph 0072-0073 & 0078), thus resulting in “a doping concentration is reduced in the undoped semiconductor layer with increasing distance from the doped semiconductor layer”.
Thus, the undoped layer of Hekmatshoar-Tabari et al. (Fig. 3, #242) and the doped layer (Fig. 3, #244) would result in the undoped layer meeting the limitation “a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%”.
In view of Claim 25, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Yano discloses that the oxygen concentration of the interface layer is at least 1.5 times the oxygen concentration of adjoining first and second semiconductor layers (Paragraph 0018) while Hekmatshoar-Tabari et al. discloses that these layers are polycrystalline. The Examiner notes that the difference between amorphous and polycrystalline silicon is the atomic structure, while the material is essentially all silicon, thus Yano’s interface layer would have a 1.5 times the oxygen concentration of adjoining doped and undoped semiconductor layers.
In view of Claim 26, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 25. Yano discloses that the oxygen concentration of the interface layer is at least 1.5 times to 1000 times the oxygen concentration of adjoining first and second semiconductor layers (Paragraph 0018) while Hekmatshoar-Tabari et al. discloses that these layers are polycrystalline. The Examiner notes that the difference between amorphous and polycrystalline silicon is the atomic structure, while the material is essentially all silicon, thus Yano’s interface layer can be selected to have 1.5 times the oxygen concentration of adjoining doped and undoped semiconductor layers.
In view of Claim 28, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Yano teaches that the interface layer has a thickness of 1 nm or less (Paragraph 0019).
In view of Claim 30, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Chang et al. discloses that the tunneling layer is situation with a first surface in contact with a first surface of a single crystalline semiconductor substrate (Figure 13, #44 contacts bottom surface #110), and a second surface of the tunneling layer contacts an adjoining first polycrystalline semiconductor layer (Figure 13, #44 contacts layer #30a), thus it would have been obvious to have the tunneling layer of Chang et al. situation adjacent the bottom surface of Hekmatshoar-Tabari et al. single crystalline semiconductor substrate (Figure 3, #202 bottom surface) and a second surface of the tunneling layer contacting the doped semiconductor layer (Figure 3, #244).
In view of Claim 31, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the tunneling layer is an oxide layer (Paragraph 0058).
In view of Claim 32, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the tunneling layer is 0.5-5nm (Paragraph 0058), while Yano discloses that the thickness of the interface layer can be 0.5 nm (Paragraph 0019). Accordingly, there are overlapping ranges of these selections that result in a ratio of the thickness of the tunneling layer to the thickness of the interface layer being with a range from 1:0.1 to 1:0.8.
In view of Claim 33, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the thickness of the tunneling layer is within a range from 0.5 to 2 nm (Paragraph 0059).
In view of Claim 35, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Yano was relied upon to disclose why it would be obvious that the interface layer would be in contact with Hekmatshoar-Tabari et al. doped and undoped semiconductor layers (Figure 3, #242/#244).
In view of Claim 36, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Hekmatshoar-Tabari et al. teaches a second conductive area formed on a second surface of the single crystalline semiconductor substrate (Figure 3, #220), wherein the first conductive area has a first conductive type opposite to a conductive type of the second conductive area (Figure 3, one side is p+ and the other side is n+).
In view of Claim 37, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 36. Hekmatshoar-Tabari et al. discloses that the second surface is a front surface of the single crystalline semiconductor substrate and wherein the first surface is a back surface of the single crystalline semiconductor substrate (Figure 3 & Paragraph 0015).
In view of Claim 38, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 36. Hekmatshoar-Tabari et al. teaches that the conductive type of the first conductive area (Figure 3, #242/#244 n+) is the same as a conductive type of the single crystalline semiconductor substrate (Figure 3, #202 n).
In view of Claim 39, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 36. Hekmatshoar-Tabari et al. teaches that a dopant included in the first conductive area has a higher doping concentration (Figure 3, #242/#244 n+) than that in the single crystalline semiconductor substrate (Figure 3, #202 n).
In view of Claim 40, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 38. Hekmatshoar-Tabari et al. does not disclose a first passivation layer formed on the first conductive area and having a first opening; a second passivation layer formed on the second conductive area and having a second opening; a first electrode connected to the first conductive area through the first opening; and a plurality of second electrodes connected to the second conductive area through the second opening.
Chang et al. teaches a first passivation layer (Figure 14, #21 – bottom element & Paragraph 0036) formed on the first conductive area (Figure 14, #30) and having an opening (Figure 14, where #34 penetrates through); a second passivation layer (Figure 14, #21 top element) formed on the second conductive area (Figure 14, #20) and having a second opening (Figure 14, where #24 penetrates through); a first electrode connected to the first conductive area through the first opening (Figure 14, #34 & Paragraph 0036); and a plurality of second electrodes connected to the second conductive area through the second opening (Figure 14, #24 & Paragraph 0036). Chang et al. teaches that this configuration can increase the amount of light incident upon a semiconductor substrate (Paragraph 0052) while also effectively passivating a emitter area (Paragraph 0053). Accordingly, it would have been obvious to adopt the passivating and electrode configuration of Chang et al. in Hekmatshoar-Tabari et al. solar cell for the advantages of increasing the amount of light incident upon Hekmatshoar-Tabari et al. semiconductor substrate while also effectively passivating the emitter.
In view of Claim 41, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 40. Chang et al. teaches that each of the first and second electrode comprises finger and bus bar electrodes (Figure 2 & Paragraph 0068-0069).
In view of Claim 42, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 40. Chang et al. teaches that the second passivation layer comprises an anti-reflection film (Figure 14, #21 & Paragraph 0051).
In view of Claim 43, Hekmatshoar-Tabari et al., Chang et al., Yano, and Graff are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the single crystalline semiconductor substrate is a single crystalline silicon substrate (Paragraph 0050), the doped semiconductor layer is a first polycrystalline silicon layer (Paragraph 0050), the undoped semiconductor layer is a second polycrystalline silicon layer (Paragraph 0061), and the interface layer is a silicon oxide layer (Paragraph 0058).
Claims 24-26, 28, 30-33, and 35-43 are rejected under 35 U.S.C. 103 as being unpatentable over Hekmatshoar-Tabari et al. (US 2012/0318336 A1) in view of Chang et al. (US 2014/0299187 A1) in view of Yano (US 2015/0059839 A1).
In view of Claim 24, Hekmatshoar-Tabari et al. discloses a solar cell (Figure 3) comprising:
a single crystalline semiconductor substrate (Figure 3, n-type c-Si Substrate);
a first conductive area formed on a first surface of the single crystalline semiconductor substrate (Figure 3, #230) that comprises a first semiconductor layer and a second semiconductor layer (Paragraph 0030 – the layers can be selected to n+ e.g., they are doped) sequentially stacked in a thickness direction (Figure 3, #232 & Paragraph 0035),
wherein a thickness of the first polycrystalline semiconductor layer can be selected to be greater than a thickness of the second polycrystalline semiconductor layer (Paragraph 0037 – the layers 242 and 244 are selected to be in the range of 1-20nm);
Hekmatshoar-Tabari et al. does not disclose that a tunneling layer is formed on a first surface of the single crystalline semiconductor substrate.
Chang et al. discloses a tunneling layer formed on a first surface of a single crystalline semiconductor substrate for the advantages of passivating the surface of the semiconductor substrate that has many recombination sites and facilitates the transfer of carriers through a tunneling effect (Figure 13, #44 & Paragraph 0056-0057). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a tunneling layer formed on a first surface of the single crystalline semiconductor substrate for the advantages of passivating the surface of the semiconductor substrate that has many recombination sites and facilitates the transfer of carriers through a tunneling effect.
Hekmatshoar-Tabari et al. does not disclose a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%.
Chang et al. teaches that doping concentrations may be gradual or stepwise increased between doping concentrations of first and second semiconductor layers (Fig. 17, #30a-b) and that this can minimize the contact resistance between a back field surface area and a second electrode (Paragraph 0132). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the first and second semiconductor layers of Hekmatshoar-Tabari et al. have a gradual increased doping concentration between these layers in order to minimize the contact resistance between a back field surface and the back electrode. A gradual doping concentration would result in a difference between the layers being less than 30% as it would gradual change from 0% to above 0%, thus meeting the limitation of having a doping concentration of a second semiconductor that is greater than 0% and less than 30%.
Modified Hekmatshoar-Tabari et al. does not disclose an interface layer interjected between the doped and undoped semiconductor layers such that the interface layer is in oxide layer having a higher oxygen concentration than each of the doped and undoped semiconductor layers and having a less oxygen concentration than the tunneling layer and that a thickness of the interface layer is less than a thickness of any one of the first semiconductor layer, the second semiconductor layer and the tunneling layer.
Yano discloses an interface layer (Figure 1, #33) that is interjected between first and second semiconductor layers (Figure 1, #21-#22), wherein the interface layer is an oxide layer that has an oxygen concentration that can be 1.5 times the oxygen concentration in adjacent silicon layers (Paragraph 0018) and can have a thickness of 0.5 nm (Paragraph 0019). Yano discloses that the interface layer advantageously prevents diffusion of hydrogen, dopants, and so on between the formation of adjacent semiconductor layers and thus the influence between adjoining layers can be reduced (Paragraph 0017). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the interface layer of Yano interjected between the doped and undoped semiconductor layers of Hekmatshoar-Tabari et al. for the advantages of preventing diffusion of hydrogen, dopants, and so on between the formation of adjacent semiconductor layers and thus the influence between adjoining layers can be reduced.
In regards to the limitation that the interface layer has “less oxygen concentration that the tunneling layer”. Applicant discloses that the first and second semiconductor layers comprise amorphous or polycrystalline silicon (Paragraph 0033) and wherein the oxygen concentration of the interface layer is at least 1.5 times the oxygen concentration in the first and second semiconductor layer (Paragraph 0038). Yano discloses an interface layer (Figure 1, #33) that is interjected between first and second semiconductor layers (Figure 1, #21-#22), wherein the interface layer is an oxide layer that has an oxygen concentration that can be 1.5 times the oxygen concentration in adjacent amorphous silicon layers (Paragraph 0018). It is the Examiner’s position that the oxygen content of the interface layer as disclosed by Yano would have a oxygen concentration less than the tunneling layer when the interface layer is at least 1.5 times the concentration of oxygen of the adjacent first and second polycrystalline layers of Hekmatshoar-Tabari.
In view of Claim 25, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Yano discloses that the oxygen concentration of the interface layer is at least 1.5 times the oxygen concentration of adjoining first and second semiconductor layers (Paragraph 0018) while Hekmatshoar-Tabari et al. discloses that these layers are polycrystalline. The Examiner notes that the difference between amorphous and polycrystalline silicon is the atomic structure, while the material is essentially all silicon, thus Yano’s interface layer would have a 1.5 times the oxygen concentration of adjoining doped and undoped semiconductor layers.
In view of Claim 26, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 25. Yano discloses that the oxygen concentration of the interface layer is at least 1.5 times to 1000 times the oxygen concentration of adjoining first and second semiconductor layers (Paragraph 0018) while Hekmatshoar-Tabari et al. discloses that these layers are polycrystalline. The Examiner notes that the difference between amorphous and polycrystalline silicon is the atomic structure, while the material is essentially all silicon, thus Yano’s interface layer can be selected to have 1.5 times the oxygen concentration of adjoining doped and undoped semiconductor layers.
In view of Claim 28, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Yano teaches that the interface layer has a thickness of 1 nm or less (Paragraph 0019).
In view of Claim 30, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Chang et al. discloses that the tunneling layer is situation with a first surface in contact with a first surface of a single crystalline semiconductor substrate (Figure 13, #44 contacts bottom surface #110), and a second surface of the tunneling layer contacts an adjoining first polycrystalline semiconductor layer (Figure 13, #44 contacts layer #30a), thus it would have been obvious to have the tunneling layer of Chang et al. situation adjacent the bottom surface of Hekmatshoar-Tabari et al. single crystalline semiconductor substrate (Figure 3, #202 bottom surface) and a second surface of the tunneling layer contacting the doped semiconductor layer (Figure 3, #244).
In view of Claim 31, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the tunneling layer is an oxide layer (Paragraph 0058).
In view of Claim 32, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the tunneling layer is 0.5-5nm (Paragraph 0058), while Yano discloses that the thickness of the interface layer can be 0.5 nm (Paragraph 0019). Accordingly, there are overlapping ranges of these selections that result in a ratio of the thickness of the tunneling layer to the thickness of the interface layer being with a range from 1:0.1 to 1:0.8.
In view of Claim 33, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the thickness of the tunneling layer is within a range from 0.5 to 2 nm (Paragraph 0059).
In view of Claim 35, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Yano was relied upon to disclose why it would be obvious that the interface layer would be in contact with Hekmatshoar-Tabari et al. doped and undoped semiconductor layers (Figure 3, #242/#244).
In view of Claim 36, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Hekmatshoar-Tabari et al. teaches a second conductive area formed on a second surface of the single crystalline semiconductor substrate (Figure 3, #220), wherein the first conductive area has a first conductive type opposite to a conductive type of the second conductive area (Figure 3, one side is p+ and the other side is n+).
In view of Claim 37, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 36. Hekmatshoar-Tabari et al. discloses that the second surface is a front surface of the single crystalline semiconductor substrate and wherein the first surface is a back surface of the single crystalline semiconductor substrate (Figure 3 & Paragraph 0015).
In view of Claim 38, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 36. Hekmatshoar-Tabari et al. teaches that the conductive type of the first conductive area (Figure 3, #242/#244 n+) is the same as a conductive type of the single crystalline semiconductor substrate (Figure 3, #202 n).
In view of Claim 39, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 36. Hekmatshoar-Tabari et al. teaches that a dopant included in the first conductive area has a higher doping concentration (Figure 3, #242/#244 n+) than that in the single crystalline semiconductor substrate (Figure 3, #202 n).
In view of Claim 40, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 38. Hekmatshoar-Tabari et al. does not disclose a first passivation layer formed on the first conductive area and having a first opening; a second passivation layer formed on the second conductive area and having a second opening; a first electrode connected to the first conductive area through the first opening; and a plurality of second electrodes connected to the second conductive area through the second opening.
Chang et al. teaches a first passivation layer (Figure 14, #21 – bottom element & Paragraph 0036) formed on the first conductive area (Figure 14, #30) and having an opening (Figure 14, where #34 penetrates through); a second passivation layer (Figure 14, #21 top element) formed on the second conductive area (Figure 14, #20) and having a second opening (Figure 14, where #24 penetrates through); a first electrode connected to the first conductive area through the first opening (Figure 14, #34 & Paragraph 0036); and a plurality of second electrodes connected to the second conductive area through the second opening (Figure 14, #24 & Paragraph 0036). Chang et al. teaches that this configuration can increase the amount of light incident upon a semiconductor substrate (Paragraph 0052) while also effectively passivating a emitter area (Paragraph 0053). Accordingly, it would have been obvious to adopt the passivating and electrode configuration of Chang et al. in Hekmatshoar-Tabari et al. solar cell for the advantages of increasing the amount of light incident upon Hekmatshoar-Tabari et al. semiconductor substrate while also effectively passivating the emitter.
In view of Claim 41, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 40. Chang et al. teaches that each of the first and second electrode comprises finger and bus bar electrodes (Figure 2 & Paragraph 0068-0069).
In view of Claim 42, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 40. Chang et al. teaches that the second passivation layer comprises an anti-reflection film (Figure 14, #21 & Paragraph 0051).
In view of Claim 43, Hekmatshoar-Tabari et al., Chang et al., and Yano are relied upon for the reasons given above in addressing Claim 24. Chang et al. teaches that the single crystalline semiconductor substrate is a single crystalline silicon substrate (Paragraph 0050), the doped semiconductor layer is a first polycrystalline silicon layer (Paragraph 0050), the undoped semiconductor layer is a second polycrystalline silicon layer (Paragraph 0061), and the interface layer is a silicon oxide layer (Paragraph 0058).
Response to Arguments
Applicant argues that Graff does not involve the concentration difference between the two polysilicon layers in the back conductive region. The Examiner respectfully points out to Applicant that Hekmatshoar-Tabari et al. discloses the doped and undoped layers (Fig. 3, #230 – comprising alternating doped or undoped layers) are deposited via CVD or plasma enhanced vapor deposition or other methods may be employed (Paragraph 0049), although is silent upon “a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%”, as there is no mention of the temperature of the deposition of the doped and undoped layers of Hekmatshoar-Tabari. Graff discloses polysilicon layers depositing via LPCVD that are deposited at temperatures higher than 600 °C (Paragraph 0022) and also discloses that this method can deposit undoped layers with higher uniformity (Paragraph 0030) and that this method improves the manufacturing of polysilicon with reduced recombination carriers within the substrate (0009-0010). Accordingly, it would have been obvious to use Graff’s deposition method to deposit the doped and undoped layers of Hekmatshoar-Tabari et al. at temperatures higher than 600 °C for the advantage of depositing the undoped layer w/ higher uniformity and utilizing an improved method with reduced recombination carriers within the substrate.
In regards to the limitation, “and a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%”. Applicant discloses that when a doped semiconductor layer (Fig. 3E, #202a) is deposited over an undoped semiconductor layer (Fig. 3E, #201a) using vapor deposition at temperatures of 600 degrees Celsius or more, that dopants diffuse from the doped semiconductor layer 202a to the undoped semiconductor layer 201a (Instant Specification – Paragraph 0072-0073 & 0078), thus resulting in “a doping concentration is reduced in the undoped semiconductor layer with increasing distance from the doped semiconductor layer”.
Thus, the undoped layer of Hekmatshoar-Tabari et al. (Fig. 3, #242) and the doped layer (Fig. 3, #244) would result in the undoped layer meeting the limitation “a difference between a doping concentration of the first semiconductor layer and a doping concentration of the second semiconductor layer is greater than 0 and less than 30%”. Accordingly, for the reasons stated above, this argument is unpersuasive.
Applicant’s arguments with respect to the claims have been considered but are moot because the arguments do not apply to the new grounds for rejection being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANIEL P MALLEY JR./Primary Examiner, Art Unit 1726
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