Prosecution Insights
Last updated: October 27, 2026
Application No. 17/959,126

DISPLAY WITH TWO BARRIER LAYERS IN THE ENCAPSULATION LAYER

Final Rejection §103
Filed
Oct 03, 2022
Priority
Oct 08, 2021 — RE 10-2021-0133700
Examiner
BRADFORD, PETER
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
4 (Final)
81%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
622 granted / 769 resolved
+12.9% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
36 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
45.8%
+5.8% vs TC avg
§102
21.9%
-18.1% vs TC avg
§112
31.2%
-8.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 769 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The claim objection is overcome by the amendment to claim 1. The applicant argues on page 10 that “In Imamura ‘FIG. 16 is a cross-sectional view showing the major portion of a Sealing Structure in a display device’ (paragraph [0082], emphasis added)”, and that Imamura does not disclose that “when seen in the plan view parallel to the base layer, an edge of the second barrier layer is outside an edge of the first barrier layer,” as recited in amended claim 1. The examiner disagrees. Claim 1 requires that “an edge” of second barrier is outside; there is not any requirement that an entirety of the edges or even an entire single edge is outside as claimed. Thus if an edge of the second barrier layer is outside an edge of the first barrier layer in vertical cross section, as seen in FIG. 16, it will also be outside at that point when seen in plan view. Furthermore, Imamura discloses that “because each of the liquid-repelling regions 314a1, 314a2, and 314a3 is formed in a loop-shape, the flattening resin layers 314cl, 314c2, and 314c3 are held inside the liquid-repelling regions 314a1, 314a2, and 314a3, respectively” [0191] and that “a closed-loop blocking region which is formed on the substrate so as to surround the entire electronic element section or a portion of the electronic element section while also surrounding the flattening resin layer.” [0012]. Thus there is explicit disclosure that the that all the elements are loops, that it is, that cross sectional view shown in FIG. 16 is present all the way around the display, and thus “an edge of the second barrier layer is outside an edge of the first barrier layer” all the way around the display in plan view. At a minimum Imamura suggests this. It is not clear how the disclosed liquid repelling protective loop would function otherwise. The applicant’s argument is not persuasive. The applicant further argues that “in Imamura, a flattening resin layer (organic layer, 314c2) is essentially interposed between the first barrier layer (314d1) and the second barrier layer (314d2) (see paragraph [0084]). This fundamentally differs from claim 1, where the second barrier layer is disposed directly on top of (i.e., in direct contact with) the first barrier layer in the specified region (e.g., overlapping the light-emitting element) while having its edge extended further outward than that of the first barrier layer without any intervening organic layers (e.g., ‘wherein in a plan view, the second barrier layer directly contacts the first barrier layer in a region overlapping the light-emitting element’ (claim 1)). Moreover, because the intervening organic resin layer is an indispensable element in Imamura's sealing structure to prevent cracking and pinholes (see paragraph [0083]), a person of ordinary skill in the art (PHOSITA) attempting to apply Imamura's extended edge structure to Kato would feel compelled to incorporate Imamura's resin layer as well.” The examiner disagrees. Imamura discloses a sealing layer made up of two inorganic layers with an organic layer in between. Imamura focusses on the structure at the periphery, where there is a protection loop. Kato discloses a sealing layer with two inorganic layers with an organic layer between them. It would have been obvious to gain the benefit of the waterproof protection loop of Imamura by including that outermost structure in Kato together with the existing structure of Kato, which has its own advantages. It would not be required to have a continuous organic layer in the display region of Kato in order to gain the benefits of the protection loop around the periphery. If the applicant continues to disagree with the examiner’s analysis, the applicant is invited to contact the examiner to discuss the matter. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6, 11, 12, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kato, US 2014/0225089 A1, in view of Imamura, US 2003/0164674 A1. Claim 1: Kato discloses a base layer (10); a circuit layer (AR) on the base layer; a light-emitting element layer on the circuit layer and comprising a pixel defining layer (LIB) and a light-emitting element including a functional layer (13) in an opening defined in the pixel defining layer; and an encapsulation layer including a first barrier layer (L1) on the light-emitting element layer and having at least one of silicon oxycarbide or silicon oxide ([0042]), and a second barrier layer (L3) directly on top of the first barrier layer and having at least one of silicon oxynitride or silicon nitride ([0042]), wherein a content of a Carbon (C) element is in a range of 0 at% to 10 at% with respect to a total content of the first barrier layer (silicon oxide, 0 at% C, [0042]), wherein in a plan view, the second barrier layer directly contacts the the first barrier layer in a region overlapping the light-emitting element (FIG. 2). PNG media_image1.png 460 376 media_image1.png Greyscale Kato does not disclose that when seen in a plan view parallel to the base layer, an edge of the second barrier layer is outside an edge of the first barrier layer. However, this was known in the art. See Imamura FIG. 16, which shows second barrier layer 314d2 outside an edge of the first barrier layer 314d1. It would have been obvious to have formed the layers in Kato in this was as a configuration that is known in the art and easily applicable to Kato. Imamura discloses a sealing layer made up of two inorganic layers with an organic layer in between. Imamura focusses on the structure at the periphery, where there is a protection loop. Kato discloses a sealing layer with two inorganic layers with an organic layer between them. It would have been obvious to gain the benefit of the waterproof protection loop of Imamura by including that outermost structure in Kato together with the existing structure of Kato, which has its own advantages. It would not be required to have a continuous organic layer in the display region of Kato in order to gain the benefits of the protection loop around the periphery. PNG media_image2.png 262 516 media_image2.png Greyscale Further note that Imamura discloses that “because each of the liquid-repelling regions 314a1, 314a2, and 314a3 is formed in a loop-shape, the flattening resin layers 314cl, 314c2, and 314c3 are held inside the liquid-repelling regions 314a1, 314a2, and 314a3, respectively” [0191] and that “a closed-loop blocking region which is formed on the substrate so as to surround the entire electronic element section or a portion of the electronic element section while also surrounding the flattening resin layer.” [0012]. Thus there is explicit disclosure that the that all the elements are loops, that it is, that cross sectional view shown in FIG. 16 is present all the way around the display, and thus “an edge of the second barrier layer is outside an edge of the first barrier layer” all the way around the display in plan view. At a minimum Imamura suggests this. Claim 2: Kato discloses that the first and second barrier layers are the same thickness ([0041]). However, through ordinary variations in manufacturing, it would be expected that the barrier thicknesses will have some random differences, including in some cases that a first thickness of the first barrier layer is greater than a second thickness of the second barrier layer by a small amount. Furthermore, changes in dimensions are not typically a source of patentable distinction absent unexpected results. See MPEP 2144.04(IV). Furthermore, where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Claim 3: Kato does not disclose that the first thickness is in a range of 3 µm to 10 µm. However, changes in dimensions are not typically a source of patentable distinction absent unexpected results. See MPEP 2144.04(IV). Furthermore, where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Claim 4 recites that with respect to the total content of the first barrier layer, a Silicon (Si) element is included in an amount in a range of 30 at% to 50 at%, and an Oxygen (O) element is included in an amount in a range of 50 at% to 60 at%. Claim 17 has an analogous recitation. Kato does not disclose the quantities of silicon and oxygen in the silicon oxide. However, the most stable silicon oxide compound is silicon dioxide, by far the most commonly used in semiconductor devices, which has a mass percentage of 46.75 at% silicon and 53.25 at% oxygen. ((Mass of Si / Molar mass of SiO₂) * 100 = (28.0855 g/mol Si / 60.0835 g/mol of SiO₂) * 100 = 46.749 at%.) Thus the by far most common form of silicon oxide falls within the scope of claim 4, and it would have been obvious and expected to have used this ubiquitous material. Claim 6: as explained above with respect to claim 1, in Kato in view of Imamura, in a plan view, an area of the second barrier layer would be larger than an area of the first barrier layer. Claim 11: the first barrier layer covers a top surface of the light-emitting element layer (FIG. 2). Claim 12: a top surface of the first barrier layer (the surface over the light emitting region) is a flat surface, and the first barrier layer fills a space between the light-emitting element layer and the second barrier layer (FIG. 2). That is, the barrier layer partially fills the space between light emitting element layer and the second barrier layer. Alternatively, the first barrier layer fills a lower space that is between the light-emitting element layer and the second barrier layer and layer L2. Claim 16: Kato discloses an electronic device including an active region (ACT) and a peripheral region outside the active region (FIG. 4), the electronic device comprising: a base layer (10); a circuit layer on the base layer (AR); a light-emitting element layer (LIB, 12-14) on the circuit layer; and an encapsulation layer on the light-emitting element layer, wherein the encapsulation layer includes a first barrier layer (L1) configured to cover an uneven top surface of the light-emitting element layer, and a second barrier layer (L3) directly on the first barrier layer, and the first barrier layer includes at least one of silicon oxycarbide or silicon oxide ([0042]), and a content of a Carbon (C) element is 0 at% to 10 at% with respect to a total content of the first barrier layer (silicon oxide, 0 at% C, [0042]), wherein the second barrier layer directly contacts the first barrier layer in the active region (FIG. 2). Kato does not disclose that when seen in a plan view parallel to the base layer, in a plan view, an edge of the second barrier layer is spaced further apart from the active region than an edge of the first barrier layer. However, this was known in the art. See Imamura FIG. 16, which shows second barrier layer 314d2 further out than the first barrier layer 314d1. It would have been obvious to have formed the layers in Kato in this was as a configuration that is known in the art and easily applicable to Kato. Imamura discloses a sealing layer made up of two inorganic layers with an organic layer in between. Imamura focusses on the structure at the periphery, where there is a protection loop. Kato discloses a sealing layer with two inorganic layers with an organic layer between them. It would have been obvious to gain the benefit of the waterproof protection loop of Imamura by including that outermost structure in Kato together with the existing structure of Kato, which has its own advantages. It would not be required to have a continuous organic layer in the display region of Kato in order to gain the benefits of the protection loop around the periphery. PNG media_image2.png 262 516 media_image2.png Greyscale Further note that Imamura discloses that “because each of the liquid-repelling regions 314a1, 314a2, and 314a3 is formed in a loop-shape, the flattening resin layers 314cl, 314c2, and 314c3 are held inside the liquid-repelling regions 314a1, 314a2, and 314a3, respectively” [0191] and that “a closed-loop blocking region which is formed on the substrate so as to surround the entire electronic element section or a portion of the electronic element section while also surrounding the flattening resin layer.” [0012]. Thus there is explicit disclosure that the that all the elements are loops, that it is, that cross sectional view shown in FIG. 16 is present all the way around the display, and thus “an edge of the second barrier layer is outside an edge of the first barrier layer” all the way around the display in plan view. At a minimum Imamura suggests this. Claim 17 recites that with respect to the total content of the first barrier layer, a Silicon (Si) element content is in a range of 30 at% to 50 at%, and an Oxygen (O) element content is in a range of 50 at% to 60 at%. Kato does not disclose the quantities of silicon and oxygen in the silicon oxide. However, the most stable silicon oxide compound is silicon dioxide, by far the most commonly used in semiconductor devices, which has a mass percentage of 46.75 at% silicon and 53.25 at% oxygen. ((Mass of Si / Molar mass of SiO₂) * 100 = (28.0855 g/mol Si / 60.0835 g/mol of SiO₂) * 100 = 46.749 at%.) Thus the by far most common form of silicon oxide falls within the scope of claim 4, and it would have been obvious and expected to have used this ubiquitous material. Claim 18: Kato does not disclose that the first barrier layer has a thickness in a range of 3 µm to 10 µm, and the second barrier layer has a thickness in a range of 1 µm or less. However, changes in dimensions are not typically a source of patentable distinction absent unexpected results. See MPEP 2144.04(IV). Furthermore, where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Claim 20: in Kato, the light-emitting element layer corresponds to the active region, the encapsulation layer covers the light-emitting element layer and extends to the peripheral region (FIG. 4): PNG media_image3.png 352 506 media_image3.png Greyscale Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Jeong, US 2020/0106050. Claim 7: Kato discloses that the first and second barrier layers L1 and L3 can be silicon oxide or silicon nitride ([0042]). In a case in which L1 is silicon oxide and L3 is silicon nitride, a refractive index of the second barrier layer would be greater than a refractive index of the first barrier layer. Furthermore, see Jeong, which discloses that a refractive index of the second barrier layer (“second inorganic layer IOL2 may have a refractive index of about 1.7 to 2.0 with respect to the wavelength of about 633 nm” [0137]) is greater than a refractive index of the first barrier layer (“the first inorganic layer IOL1 may have a refractive index of about 1.60 to about 1.65” [0108]). It would have been obvious to have had such an arrangement as known in the art and in order to reduce color shifting (Jeong [0109]). Claim 13: Jeong discloses a sensor layer (TS) on the encapsulation layer, wherein the sensor layer is directly on the second barrier layer (FIG. 8A). Sensors were very common in the art of displays, especially for handheld devices, and it would have been obvious to have been obvious to position them as taught by Jeong as known in the art as an effective placement of the sensor. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER BRADFORD/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Show 2 earlier events
Oct 29, 2025
Response Filed
Feb 11, 2026
Final Rejection mailed — §103
Apr 10, 2026
Response after Non-Final Action
May 11, 2026
Request for Continued Examination
May 13, 2026
Response after Non-Final Action
May 19, 2026
Non-Final Rejection mailed — §103
Aug 19, 2026
Response Filed
Oct 16, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
81%
Grant Probability
85%
With Interview (+4.4%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 769 resolved cases by this examiner. Grant probability derived from career allowance rate.

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