DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-18 without traverse in the reply filed on 10/08/2025 is acknowledged. Claims 19-32 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
Amendment to specification 10/08/2025 has been acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 11, 13, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. ( US 11,417,675 B2) in view of KIM et al. (US 2020/0381447 A1).
Regarding claim 1, Jang teaches,
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A semiconductor memory device (FIG. 4A as annotated above) comprising:
a semiconductor substrate (10, Col. 5, l. 47) including a top surface (top surface of 10), the top surface facing a first direction (D3) and extending in a second direction (D2);
a first source structure (portion of source structure SC on left side of 150 as marked above, Col. 7, l. 4) and a second source structure (SC on right side of 150 as marked above) spaced apart from the semiconductor substrate in the first direction (D3) and spaced apart (by intervening layer 150) from each other in the second direction (D2);
a filling pattern (insulating pattern 150, Col. 7, l. 2) between the first source structure and the second source structure (see above);
a memory cell array (cell array structure CS on the left, Col. 5, l. 42) overlapping with the first source structure;
But Jang does not explicitly teach,
and a plurality of discharge contacts penetrating the second source structure and connected to the semiconductor substrate.
Meanwhile, KIM teaches,
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The source film SLa, SLb, or SLc and the discharge impurity region DCI may be connected to each other by the conductive contact plug DCC. Therefore, the charge accumulated in the source film SLa, SLb, or SLc may be discharged to the substrate SUB through the discharge impurity region DCI via the conductive contact plug DCC (para [0037], FIG. 2A).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Jang such that the second source structure/source film SC/SLa are connected to a discharge impurity region DCI in the substrate 10/SUB via a conductive contact plug DCC such that a plurality of discharge contact (first to fifth patterns P1-P5, para [0039], Kim, Fig. 2A, discharging charge to substrate, hence discharge contacts) penetrating the second source structure SC (similar way DCC penetrating SLa in Kim FIG. 2A) and connected to the semiconductor substrate (10/SUB), according to teaching of KIM, in order to discharge charge accumulated in the source structure SC to the substrate 10, as taught by KIM above.
Regarding claim 2, Jang & Kim teach the semiconductor memory device of claim 1 and further teaches, further comprising: a trench comprising a first groove (groove inside the first source structure as marked), a second groove (groove inside the second source structure as marked), and third groove (grove inside the filling pattern 150 as marked) being aligned in the second direction (D2) and connected to each other (as seen), the first groove disposed inside the first source structure, the second groove disposed inside the second source structure, and the third groove disposed inside the filling pattern (as defined);
But Jang & Kim do not explicitly teach,
a source contact structure disposed in the first groove of the trench and in contact with the first source structure.
But Kim additionally teaches,
a source contact structure (SCT, para [0052], FIG. 2A) disposed in the first groove of the trench (inside the source structure SLa, FIG. 2A on left) and in contact with the first source structure (SLa on left).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Jang such that a source contact structure SCT disposed in the first groove of the trench and in contact with the first source structure, according to teaching of Kim, in order to form a common source line as widely known in art.
Regarding claim 3, Jang & Kim teach the semiconductor memory device of claim 2 and further teaches , wherein a length of the source contact structure is shorter than a length of the first groove in the second direction (Kim, FIG. 2A, length of SCT in lateral direction is shorter than half lateral length of groove of source structure SLa, hence in combined device, SCT would be obviously shorter than a length of the first groove).
Regarding claim 5, Jang & Kim teach the semiconductor memory device of claim 2 and further teaches , wherein the memory cell array comprises: a plurality of conductive patterns (CGE, Jang FIG. 4A) disposed above the first source structure (as seen above), spaced apart from each other in the first direction (D3), and disposed on both sides of the first groove (right side and top side of the first groove); a channel layer (VS) penetrating the plurality of conductive patterns and in contact with the first source structure; and a memory layer (DSP, col. 6, l. 56) disposed between each of the plurality of conductive patterns and the channel layer.
Regarding claim 6, Jang & Kim teach the semiconductor memory device of claim 1 and further teaches , wherein the first source structure (considering source structure including SCP1, SCP2 & 100, FIG. 4A) comprises a first semiconductor layer (100),an interlayer semiconductor layer (SCP1), and a second semiconductor layer (SCP2, FIG. 4A, Col. 7, l. 9) stacked in the first direction, and wherein the interlayer semiconductor layer (SCP1) is in contact with the first semiconductor layer (100) and the second semiconductor layer (SCP2).
Regarding claim 7, Jang & Kim teach the semiconductor memory device of claim 6 and further teaches, wherein the second semiconductor layer is penetrated by a trench (including trenches of 150, 11a & 12a) and wherein the trench extends in the second direction (D2) to be disposed inside the filling pattern (150) and the second source structure (trench of 11a, 12a is inside SCP2).
Regarding claim 11, Jang teaches,
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A semiconductor memory device (FIG. 4A as annotated above)comprising:
a semiconductor substrate including a first area (AR1), a second area (AR2), a first extension area (EA1)between the first area and the second area, and a second extension area (EA2) extending away from the second area opposite the first extension area;
a first source structure (SC structure on left side of 150 as marked) overlapping with the first area of the semiconductor substrate;
a second source structure (SC structure on right side of 150 as marked) overlapping with the second area of the semiconductor substrate;
...…….a filling pattern (insulating pattern 150, Col. 7, l. 2) overlapping with the first extension area of the semiconductor substrate and interposed between the first source structure and the second source structure (as seen);
a plurality of interlayer dielectrics (ILD) and a plurality of conductive patterns (CGE) alternately disposed above the first source structure;
and a channel layer (VS, FIG. 4A) penetrating the plurality of interlayer dielectrics and the plurality of conductive patterns and connected to the first source structure (as seen),
wherein a trench (trench of the first source structure as defined) is formed in a surface of the first source structure facing the plurality of interlayer dielectrics and the plurality of conductive patterns,
and wherein the plurality of interlayer dielectrics and the plurality of conductive patterns are penetrated by a slit (slit of CPLG, FIG. 4A) overlapping with the trench.
But PARK does not explicitly teach,
a plurality of discharge contacts penetrating the second source structure and connected to the second area of the semiconductor substrate;
Meanwhile, KIM teaches,
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The source film SLa, SLb, or SLc and the discharge impurity region DCI may be connected to each other by the conductive contact plug DCC. Therefore, the charge accumulated in the source film SLa, SLb, or SLc may be discharged to the substrate SUB through the discharge impurity region DCI via the conductive contact plug DCC (para [0037], FIG. 2A).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Jang such that the second source structure/source film SC/SLa are connected to a discharge impurity region DCI in the substrate 10/SUB via a conductive contact plug DCC such that a plurality of discharge contact (comprising first to fifth patterns P1-P5 , para [0039], Kim, Fig. 2A, discharging charge to DCI/SUB , hence discharge contacts) penetrating the second source structure SC (similar way DCC penetrating SLa on right in Kim FIG. 2A) and connected to the second area AR2 of the substrate (10/SUB), according to teaching of KIM, in order to discharge charge accumulated in the source structure SC to the substrate 10, as taught by KIM above.
Regarding claim 13, Jang & Kim teach the semiconductor memory device of claim 11 and further teaches ,wherein the first source structure comprises: a first semiconductor layer (100, Jang, FIG. 4A) overlapping with the first area of the semiconductor substrate; an interlayer semiconductor layer (SCP1, FIG. 4A) on the first semiconductor layer; and a second semiconductor layer (SCP2) on the interlayer semiconductor layer, wherein the interlayer semiconductor layer SCP1 is in contact with the first semiconductor layer 100 and the second semiconductor layer SCP2, and wherein the second semiconductor layer SCP2 is penetrated by the trench (as seen).
Regarding claim 16, Jang & Kim teach the semiconductor memory device of claim 13 and further teaches, wherein the channel layer (VS, Jang Fig. 4A) penetrates the second semiconductor layer (SCP2) of the first source structure, extends into the first semiconductor layer (100) of the first source structure, and is in contact with the interlayer semiconductor layer (SCP1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. in view of KIM et al. and further in view of OH et al. (US 2017/0323898 A1)
Regarding claim 12, Jang & Kim teaches the semiconductor memory device of claim 11 but does not explicitly teach, further comprising: a circuit structure disposed in the second extension area of the semiconductor substrate and configured to transmit an operating voltage to the plurality of conductive patterns.
Meanwhile OH teaches,
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a circuit structure (including ROW decoder 120 ) configured to transmit an operating voltage (S) to the plurality of conductive patterns (WL) ( para [0030])
Thus, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to further modify Jang & Kim to form a circuit structure (including ROW decoder 120 ) configured to transmit an operating voltage (S) to the plurality of conductive patterns (CGE), according to teaching of OH, in order to transmit word line voltage S from voltage generator 160 to the word lines WL/Jang’s CGE used as word line ( Col. 8, ll. 5-6).
Allowable Subject Matter
Claims 4,8-10,14-15, 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 4,8, 10,14-15, 17 the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
wherein the plurality of discharge contacts are disposed on both sides of the second groove at a position spaced apart from the second groove of the trench (claim 4).
wherein the interlayer semiconductor layer extends into a part of the trench defined inside the filling pattern and the second source structure(claim 8).
wherein the second source structure comprises a first semiconductor layer, a first passivation layer, a source sacrificial layer, a second passivation layer, and a second semiconductor layer stacked in the first direction (claim 10)
wherein the trench extends to cross the filling pattern and the second source structure, and wherein the slit is spaced apart from the filling pattern and the second source structure(claim 14).
wherein the interlayer semiconductor layer extends to overlap with the filling pattern and the second source structure(claim 15)
wherein the second source structure comprises: a first semiconductor layer overlapping with the second area of the semiconductor substrate; a first passivation layer on the first semiconductor layer; a source sacrificial layer on the first passivation layer; a second passivation layer on the source sacrificial layer; and a second semiconductor layer on the second passivation layer(claim 17)
Claim 9 is objected to being dependent on claim 8.
Claim 18 is objected to being dependent on claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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/K.A.R/Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813