DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed February 19th, 2024 has been entered. Claims 1-21 remain pending in the application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/05/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 objected to because of the following informalities:
First time acronyms OAM and PCS should be spelled out
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1, 4, 5, 6, 9, 10, 12, 13, 14, 16, 17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over William LO (US2020/0177522), LO hereinafter, in view of Chu Ming TU et al. (2016/0365967), TU hereinafter, and further in view of Hossein Sedarat (US10594524) et al., Sederat hereinafter.
Re. Claim 1, LO teaches A physical layer Ethernet device, utilizing time domain duplexing, capable of symmetrical or asymmetrical communication, comprising: (Fig 27 & ¶0059 – “In FIG. 27, one example of the transition from symmetric to asymmetric mode is shown.”);
a time domain duplexing PCS comprising: (¶0085 - Any changes required should not touch the Media Access Control (MAC) layer, and any change should be limited to the PHY and reconciliation sublayers. The PHY includes of the Physical Coding Sublayer (PCS) and Physical Medium Attachment (9).)
receive first data, over an XGMII interface; ( ¶0020 -21 - A replicating circuit is configured to replicate the first data at the first speed by a ratio of the second speed over the first speed to generate replicated first data at the second speed. A downsampling circuit is configured to receive the replicated first data at the second speed, to downsample the replicated first data to recover and output the first data at the first speed to the MAC. In other features, first data at the first speed comprises MII data and the second data at the second speed comprises XGMII data. A first serializer is configured to serialize the first data from the PHY to provide first serialized data.)
encode the first data to create second data using XGMII encoding; (Fig 9 & ¶0091 - Referring now to FIG. 9, a data path from XGMII to line is shown. The data path includes an encoder 910 to encode the data)
a framer configured to process the mapped data with Reed Solomon FEC framing and perform scrambling to create data bursts, that include a header and one or more phyL blocks; (Fig 9 & ¶0016 - In other features, the transmit path further includes an error correcting encoder to encode an output of the encoder. The error correcting encoder comprises a Reed Solomon encoder; ¶0114 - Referring now to FIG. 17A, an example of framing of the 64 bits is shown to include a header field, a data payload field and a parity field. In FIG. 17B, a low speed data path is shown. The low speed data path includes an encoder 1710 to encode the XGMII data (or MII data). A scrambler 1714 is optional and can be used to scramble an output of the encoder 1710. A error correcting encoder 1718 encodes an output of the scrambler 1714; ¶0091 - Referring now to FIG. 9, a data path from XGMII to line is shown. The data path includes an encoder 910 to encode the data. In some examples, the encoder 910 includes a 64 bit/65 bit encoder. An aggregator 914 aggregates data. In some examples, the aggregator 914 aggregates blocks of data into frames. For example, the aggregator 914 aggregates 50 blocks of 64/65 encoded blocks into a Reed Solomon frame of 325 ten-bit symbols. An error correcting encoder 918 adds error correction. For example the error correcting encoder 918 may include a Reed Solomon that appends one additional 10-bit symbol followed by 34 10-bit parity symbol. This is the RS(360, 326) GF(2.sup.10) coding. The Reed Solomon encoder may interleave the RS frame 4×, 2× or not at all depending on the configuration.)
LO does not expressly teach the claimed features of a burst mapper configured to receive the second data and generate mapped data, the mapped data comprising blocks of data, OAM data, and reserved bits.
However, in analogous art, TU explicitly discloses a burst mapper configured to receive the second data and generate mapped data, the mapped data comprising blocks of data, OAM data, and reserved bits. (¶0077 - The scrambler 236 performs an XOR operation on the RS symbols 1540 and the scrambler sequence and outputs the scrambled data blocks to the signal mapper 238. Thus, the OAM blocks (in addition to the data blocks) are encoded by the RS encoder 234 and scrambled by the scrambler 236. The signal mapper 238 maps three bits of the scrambled data blocks to two ternary symbols to generate the PAM symbols 1550.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include a burst mapper configured to receive the second data and generate mapped data, the mapped data comprising blocks of data, OAM data, and reserved bits.
The motivation for doing so would be for establishing link for single pair ethernet. (¶0002)
Yet, LO and TU, do not expressly teach the claimed features of a mapping module configured to performing pulse amplitude mapping on the data bursts to create mapped signals; and a PMA configured to transmit and receive the PAM4 signals and the PAM2 signals over a channel, ranging from 2 Gbps to 16 Gbps. sending, by the distributed unit, second information to a central unit of the network device.
However, in analogous art, Sederat explicitly discloses a mapping module configured to performing pulse amplitude mapping on the data bursts to create mapped signals; ((8) According to various embodiments, a transmitter uses Tomlinson-Harashima precoding (THP) to implement partial equalization of a data signal prior to its transmission to a receiver, and the receiver uses decision feedback equalizer (DFE) to equalize the data signal once received from the transmitter. For some embodiments, the THP is implemented at the transmitter by a precoder that uses one or more integer taps (e.g., one or two taps). For some embodiments, the tap coefficients for the precoder implementing THP have a value of 1 or −1, etc. For instance, FIG. 2 shows an example of a simple construction of a precoder implementing THP that comprises a single unity-t)
a PMA configured to transmit and receive the PAM4 signals and the PAM2 signals over a channel, ranging from 2 Gbps to 16 Gbps. (Section 1 lines 35 – 40 - Generally, the PHY layer of a communications interface compatible with a given channel can compensate for channel effects and achieve a certain level of data rate/speed (e.g., 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, or 100 Gbps) by using different types of encoding or signal modulation schemes for transmitting data over the given channel and noise. In order to guarantee interoperability among various transceivers, the transmit specifications are typically defined by standard bodies such as the Institute of Electrical and Electronics Engineers (IEEE). An example IEEE standard includes the IEEE 802.3 standards, which standardizes the physical layers of various Ethernet protocols. Among other things, the standard may specify the transmit signal modulation, transmit filtering and precoding. The modulation may be a pulse amplitude modulation (PAM) scheme (e.g., PAM2 or PAM4), and transmit filtering and precoding may be linear or nonlinear.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to have a mapping module configured to performing pulse amplitude mapping on the data bursts to create mapped signals; and a PMA configured to transmit and receive the PAM4 signals and the PAM2 signals over a channel, ranging from 2 Gbps to 16 Gbps. sending, by the distributed unit, second information to a central unit of the network device.
The motivation for doing so would be to correct for post cursor ISI (Section 2 line 1)
Re. Claim 4, LO, TU, and Sederat teach claim 1.
Yet, LO does not expressly teach disclose the device of claim 1 wherein the mapped data comprising 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits.
TU explicitly discloses wherein the mapped data comprising 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits. (¶0077 - The scrambler 236 performs an XOR operation on the RS symbols 1540 and the scrambler sequence and outputs the scrambled data blocks to the signal mapper 238. Thus, the OAM blocks (in addition to the data blocks) are encoded by the RS encoder 234 and scrambled by the scrambler 236. The signal mapper 238 maps three bits of the scrambled data blocks to two ternary symbols to generate the PAM symbols 1550.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the mapped data to comprise of 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits;
The motivation for doing so would be for establishing link for single pair ethernet. (¶0002)
Re. Claim 5, LO, TU, and Sederat teach claim 1.
Yet, LO, does not expressly teach discloses wherein the mapped signal comprise PAM2 signal, PAM4 signals, or both, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals.
However, in analogous art Sederat explicitly discloses wherein the mapped signal comprise PAM2 signal, PAM4 signals, or both, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals. (Section 1 lines 35 – 40 - Generally, the PHY layer of a communications interface compatible with a given channel can compensate for channel effects and achieve a certain level of data rate/speed (e.g., 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, or 100 Gbps) by using different types of encoding or signal modulation schemes for transmitting data over the given channel and noise. In order to guarantee interoperability among various transceivers, the transmit specifications are typically defined by standard bodies such as the Institute of Electrical and Electronics Engineers (IEEE). An example IEEE standard includes the IEEE 802.3 standards, which standardizes the physical layers of various Ethernet protocols. Among other things, the standard may specify the transmit signal modulation, transmit filtering and precoding. The modulation may be a pulse amplitude modulation (PAM) scheme (e.g., PAM2 or PAM4), and transmit filtering and precoding may be linear or nonlinear.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the mapped signal to comprise PAM2 signal, PAM4 signals, or both, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals
The motivation for doing so would be to correct for post cursor ISI (Section 2 line 1)
Re. Claim 6, LO, TU, and Sederat teach claim 1.
LO explicitly discloses wherein each phyL block comprises 240 bytes. (Fig 28 & ¶0231 Referring now to FIG. 28, examples of upstream and downstream transmit parameters are shown. The discussion of PHY training can be made more concrete by using specific numbers instead of abstract variables. However, the present disclosure is not limited to using only these specific parameters. Note that the speeds with the downstream frame size of 240 bytes use stronger FEC (more parity bytes) as compared to the 216 byte frame.)
Re. Claim 8, LO, TU, and Sederat teach claim 1.
LO explicitly discloses wherein the data rates in asymmetrical mode comprise: 2.5 Gbps and 100 Mbps; 5 Gbps and 100 Mbps; 10 Gbps and 100 Mbps; and 10 Gbps and 1Gbps. (¶0088 - While the present disclosure discusses the asymmetric PHY using specific examples and numbers for illustration, variations of the examples set forth herein are contemplated. For example in the disclosure below, the 2.5GBASE-T1, 5GBASE-T1, and 10GBASE-T1 PHY is used as the high speed path running 2.5 Gb/s, 5 Gb/s and 10 Gb/s respectively and a low speed path of 10 Mb/s is used. However, the teaching set forth herein can be generalized to other PHYs such as 1000BASE-T1, 100BASE-T1, 1000BASE-T, 2.5GBASE-T, 5GBASE-T, 10GBASE-T (note -T not -T1) and the low speed path can be something other than 10 Mb/s (i.e. 100 Mb/s, 1000 Mb/s, etc.)
Re. Claim 9
LO explicity discloses a method, utilizing time domain duplexing, capable of symmetrical or asymmetrical communication, performed by a physical layer device, comprising: performing XGMII encoding on first data, received over an XGMII interface, (Fig 27 & ¶0059 - In FIG. 27, one example of the transition from symmetric to asymmetric mode is shown; ¶0085 - IEEE 802 defines Ethernet to be a layered architecture. Any changes required should not touch the Media Access Control (MAC) layer, and any change should be limited to the PHY and reconciliation sublayers. The PHY includes of the Physical Coding Sublayer (PCS) and Physical Medium Attachment (9); Fig 9 & ¶0091 - Referring now to FIG. 9, a data path from XGMII to line is shown. The data path includes an encoder 910 to encode the data)
framing the mapped data with Reed Solomon FEC framing and performing scrambling to create data bursts, the data bursts including a header and one or more phyL blocks;
(¶0016 - In other features, the transmit path further includes an error correcting encoder to encode an output of the encoder. The error correcting encoder comprises a Reed Solomon encoder.)
TU explicitly discloses wherein the first data comprises 64 bits of payload and 4 bits of control per 32 bits of payload, to create second data; (¶0019 - The framer 210 may receive the bit stream and generate one or more frames by dividing the bit stream into smaller pieces of pre-specified size and adding control bits. The framer 210 may add control bits such as synchronization bits, cyclic redundancy check bits, and stuffing bits to cause frame alignment, error detection, and to mark the frame boundaries. In one embodiment, each frame may comprise a payload bits and control bits.)
mapping the second data with a burst mapper to generate mapped data; (¶0077 - The example bit ordering 1500 begins with 80-bit data blocks 1510 that are appended with a header and encoded to 81-bit data blocks 1520 by the PCS encoder 232. Forty-five 81-bit data blocks plus a 9-bit operations, administration, and maintenance (OAM) block are aggregated to form the RS encoder 234 payloads 1530. The RS encoder 234 generates RS symbols 1540 (or codewords) from the payloads. The scrambler 236 performs an XOR operation on the RS symbols 1540 and the scrambler sequence and outputs the scrambled data blocks to the signal mapper 238. Thus, the OAM blocks (in addition to the data blocks) are encoded by the RS encoder 234 and scrambled by the scrambler 236. The signal mapper 238 maps three bits of the scrambled data blocks to two ternary symbols to generate the PAM symbols 1550.)
Sederat explicitly discloses performing PAM2/PAM4 mapping on the data bursts to create PAM4 signals and PAM2 signals; and transmitting and receiving the PAM4 signals and the PAM2 signals, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals. (Section 1 lines 35 – 40 - Generally, the PHY layer of a communications interface compatible with a given channel can compensate for channel effects and achieve a certain level of data rate/speed (e.g., 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, or 100 Gbps) by using different types of encoding or signal modulation schemes for transmitting data over the given channel and noise. In order to guarantee interoperability among various transceivers, the transmit specifications are typically defined by standard bodies such as the Institute of Electrical and Electronics Engineers (IEEE). An example IEEE standard includes the IEEE 802.3 standards, which standardizes the physical layers of various Ethernet protocols. Among other things, the standard may specify the transmit signal modulation, transmit filtering and precoding. The modulation may be a pulse amplitude modulation (PAM) scheme (e.g., PAM2 or PAM4), and transmit filtering and precoding may be linear or nonlinear.)
and transmitting and receiving the PAM4 signals and the PAM2 signals, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals. (Section 1 lines 35 – 40 - Generally, the PHY layer of a communications interface compatible with a given channel can compensate for channel effects and achieve a certain level of data rate/speed (e.g., 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, or 100 Gbps) by using different types of encoding or signal modulation schemes for transmitting data over the given channel and noise. In order to guarantee interoperability among various transceivers, the transmit specifications are typically defined by standard bodies such as the Institute of Electrical and Electronics Engineers (IEEE). An example IEEE standard includes the IEEE 802.3 standards, which standardizes the physical layers of various Ethernet protocols. Among other things, the standard may specify the transmit signal modulation, transmit filtering and precoding. The modulation may be a pulse amplitude modulation (PAM) scheme (e.g., PAM2 or PAM4), and transmit filtering and precoding may be linear or nonlinear.)
Re. Claim 10, LO, TU, and Sederat teach claim 9.
Yet, LO, TU, and Sederat, do not expressly teach discloses The device of claim 1 wherein the mapped data comprising 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits;
However in analogous art, TU explicitly discloses wherein the mapped data comprising 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits. (¶0077 - The scrambler 236 performs an XOR operation on the RS symbols 1540 and the scrambler sequence and outputs the scrambled data blocks to the signal mapper 238. Thus, the OAM blocks (in addition to the data blocks) are encoded by the RS encoder 234 and scrambled by the scrambler 236. The signal mapper 238 maps three bits of the scrambled data blocks to two ternary symbols to generate the PAM symbols 1550.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include the mapped data comprising 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits;
The motivation for doing so would be for establishing link for single pair ethernet. (¶0002)
Re. Claim 12 , LO, TU, and Sederat teach claim 9.
LO explicitly discloses the method of claim 9 wherein the method occurs in a communication system configured to operate in symmetrical mode or asymmetrical mode based on TDD within an Ethernet compatible network. (¶0002 - The present disclosure relates to data communication systems, and more particularly to data communication systems including asymmetrical Ethernet physical layer devices.)
Re. Claim 13 , LO, TU, and Sederat teach claim 9.
LO explicitly discloses wherein the data line rates in asymmetrical mode comprise: 2.5 Gbps downstream and 100 Mbps upstream;5 Gbps downstream and 100 Mbps upstream; 10 Gbps downstream and 100 Mbps upstream; and 10 Gbps downstream and 1 Gbps upstream. (¶0088 - While the present disclosure discusses the asymmetric PHY using specific examples and numbers for illustration, variations of the examples set forth herein are contemplated. For example in the disclosure below, the 2.5GBASE-T1, 5GBASE-T1, and 10GBASE-T1 PHY is used as the high speed path running 2.5 Gb/s, 5 Gb/s and 10 Gb/s respectively and a low speed path of 10 Mb/s is used. However, the teaching set forth herein can be generalized to other PHYs such as 1000BASE-T1, 100BASE-T1, 1000BASE-T, 2.5GBASE-T, 5GBASE-T, 10GBASE-T (note -T not -T1) and the low speed path can be something other than 10 Mb/s (i.e. 100 Mb/s, 1000 Mb/s, etc.).
Re. Claim 14, LO, TU, and Sederat teach claim 9.
LO explicitly discloses The method of claim 9 wherein the number of blocks in the mapped data, created by the burst mapper, is varied to change the effective line rate.. (¶0096 - The MAC is an entity that generates and receives data frames. The frames are presented to the reconciliation sublayer where the frames are presented serially to the *MII interface. Several options describing how the signals are physically instantiated on the *MII to a multi speed PHY are discussed below. In this example, 2.5, 5, 10 Gb/s are used for the high speed mode and 10 Mb/s for the low speed mode.)
Re. Claim 16
LO explitly discloses An Ethernet PHY device comprising: a time domain duplexing PCS comprising:
(¶0085 - Any changes required should not touch the Media Access Control (MAC) layer, and any change should be limited to the PHY and reconciliation sublayers. The PHY includes of the Physical Coding Sublayer (PCS) and Physical Medium Attachment (9).)
receive first data, over an XGMII interface; ( ¶0020 -21 - A replicating circuit is configured to replicate the first data at the first speed by a ratio of the second speed over the first speed to generate replicated first data at the second speed. A downsampling circuit is configured to receive the replicated first data at the second speed, to downsample the replicated first data to recover and output the first data at the first speed to the MAC. In other features, first data at the first speed comprises MII data and the second data at the second speed comprises XGMII data. A first serializer is configured to serialize the first data from the PHY to provide first serialized data.)
a framer configured to process the mapped data with Reed Solomon FEC framing and perform scrambling to create data bursts, that include a header and one or more phyL blocks;
(Fig 9 & ¶0016 - In other features, the transmit path further includes an error correcting encoder to encode an output of the encoder. The error correcting encoder comprises a Reed Solomon encoder; ¶0114 - Referring now to FIG. 17A, an example of framing of the 64 bits is shown to include a header field, a data payload field and a parity field. In FIG. 17B, a low speed data path is shown. The low speed data path includes an encoder 1710 to encode the XGMII data (or MII data). A scrambler 1714 is optional and can be used to scramble an output of the encoder 1710. A error correcting encoder 1718 encodes an output of the scrambler 1714; ¶0091 - Referring now to FIG. 9, a data path from XGMII to line is shown. The data path includes an encoder 910 to encode the data. In some examples, the encoder 910 includes a 64 bit/65 bit encoder. An aggregator 914 aggregates data. In some examples, the aggregator 914 aggregates blocks of data into frames. For example, the aggregator 914 aggregates 50 blocks of 64/65 encoded blocks into a Reed Solomon frame of 325 ten-bit symbols. An error correcting encoder 918 adds error correction. For example the error correcting encoder 918 may include a Reed Solomon that appends one additional 10-bit symbol followed by 34 10-bit parity symbol. This is the RS(360, 326) GF(2.sup.10) coding. The Reed Solomon encoder may interleave the RS frame 4×, 2× or not at all depending on the configuration.)
LO does not expressly teach the claimed features of wherein the first data comprises 64 bits of payload and 4 bits of control per 32 bits of payload, encode the first data to create second data using XGMII encoding, and a burst mapper configured to receive the second data and generate mapped data, the mapped data comprising 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits;
However, in analogous art, TU explicitly discloses ,wherein the first data comprises 64 bits of payload and 4 bits of control per 32 bits of payload; (¶0019 - The framer 210 may receive the bit stream and generate one or more frames by dividing the bit stream into smaller pieces of pre-specified size and adding control bits. The framer 210 may add control bits such as synchronization bits, cyclic redundancy check bits, and stuffing bits to cause frame alignment, error detection, and to mark the frame boundaries. In one embodiment, each frame may comprise a payload bits and control bits.)
encode the first data to create second data using XGMII encoding; (¶0032 - The MAC module 210 is communicatively coupled to the PHY module 220 via an interface, such as a gigabit medium independent interface (GMII), or any other interface, over which data is communicated between the MAC module 210 and the PHY module 220. The PCS encoder 232 performs one or more encoding and/or transcoding functions on data received from the MAC module 210, such as 80b/81b line encoding. The RS encoder 234 performs RS encoding on the data received from the PCS encoder 232. The scrambler 236 is an additive or synchronous scrambler such that bit errors will not result in descrambler re-synchronization, as may be the case for multiplicative scramblers.)
a burst mapper configured to receive the second data and generate mapped data, the mapped data comprising 26 blocks of data, each having 65 bits along with 22 bits for OAM and reserved bits; (¶0077 - The example bit ordering 1500 begins with 80-bit data blocks 1510 that are appended with a header and encoded to 81-bit data blocks 1520 by the PCS encoder 232. Forty-five 81-bit data blocks plus a 9-bit operations, administration, and maintenance (OAM) block are aggregated to form the RS encoder 234 payloads 1530. The RS encoder 234 generates RS symbols 1540 (or codewords) from the payloads. The scrambler 236 performs an XOR operation on the RS symbols 1540 and the scrambler sequence and outputs the scrambled data blocks to the signal mapper 238. Thus, the OAM blocks (in addition to the data blocks) are encoded by the RS encoder 234 and scrambled by the scrambler 236. The signal mapper 238 maps three bits of the scrambled data blocks to two ternary symbols to generate the PAM symbols 1550.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include data comprises 64 bits of payload and 4 bits of control per 32 bits of payload, encode the first data to create second data using XGMII encoding, and a burst mapper configured to receive the second data and generate mapped data, the mapped data comprising blocks of data, OAM data, and reserved bits.
The motivation for doing so would be for establishing link for single pair ethernet. (¶0002)
Yet, LO and TU, do not expressly teach the claimed features of PAM2/PAM4 mapping module configured to performing pulse amplitude mapping on the data bursts to create PAM4 signals and PAM2 signals and a PMA configured to transmit and receive the PAM4 signals and the PAM2 signals over a channel, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals and transmitting and receiving the PAM4 signals and the PAM2 signals, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals.
However, in analogous art, Sederat explicitly discloses PAM2/PAM4 mapping module configured to performing pulse amplitude mapping on the data bursts to create PAM4 signals and PAM2 signals;
(Section 1 lines 38 – 40 - by using different types of encoding or signal modulation schemes for transmitting data over the given channel and noise. In order to guarantee interoperability among various transceivers, the transmit specifications are typically defined by standard bodies such as the Institute of Electrical and Electronics Engineers (IEEE). An example IEEE standard includes the IEEE 802.3 standards, which standardizes the physical layers of various Ethernet protocols. Among other things, the standard may specify the transmit signal modulation, transmit filtering and precoding. The modulation may be a pulse amplitude modulation (PAM) scheme (e.g., PAM2 or PAM4), and transmit filtering and precoding may be linear or nonlinear.)
and a PMA configured to transmit and receive the PAM4 signals and the PAM2 signals over a channel, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals (Section 1 lines 35 – 40 - Generally, the PHY layer of a communications interface compatible with a given channel can compensate for channel effects and achieve a certain level of data rate/speed (e.g., 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, or 100 Gbps) by using different types of encoding or signal modulation schemes for transmitting data over the given channel and noise. In order to guarantee interoperability among various transceivers, the transmit specifications are typically defined by standard bodies such as the Institute of Electrical and Electronics Engineers (IEEE). An example IEEE standard includes the IEEE 802.3 standards, which standardizes the physical layers of various Ethernet protocols. Among other things, the standard may specify the transmit signal modulation, transmit filtering and precoding. The modulation may be a pulse amplitude modulation (PAM) scheme (e.g., PAM2 or PAM4), and transmit filtering and precoding may be linear or nonlinear.)
and transmitting and receiving the PAM4 signals and the PAM2 signals, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals. (Section 1 lines 35 – 40 - Generally, the PHY layer of a communications interface compatible with a given channel can compensate for channel effects and achieve a certain level of data rate/speed (e.g., 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, or 100 Gbps) by using different types of encoding or signal modulation schemes for transmitting data over the given channel and noise. In order to guarantee interoperability among various transceivers, the transmit specifications are typically defined by standard bodies such as the Institute of Electrical and Electronics Engineers (IEEE). An example IEEE standard includes the IEEE 802.3 standards, which standardizes the physical layers of various Ethernet protocols. Among other things, the standard may specify the transmit signal modulation, transmit filtering and precoding. The modulation may be a pulse amplitude modulation (PAM) scheme (e.g., PAM2 or PAM4), and transmit filtering and precoding may be linear or nonlinear.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to have PAM2/PAM4 mapping module configured to performing pulse amplitude mapping on the data bursts to create PAM4 signals and PAM2 signals; and a PMA configured to transmit and receive the PAM4 signals and the PAM2 signals over a channel, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals, and transmitting and receiving the PAM4 signals and the PAM2 signals, ranging from 2 Gbps to 16 Gbps, such that 12 Gbps and 16 Gbps signals are transmitted as PAM4 signals and 8 Gbps and lower signal are transmitted as PAM2 signals.
The motivation for doing so would be to correct for post cursor ISI (Section 2 line 1)
Re. Claim 18 , LO, TU, and Sederat teach claim 16.
LO explicitly discloses wherein the user selectable data rates comprise: the following asymmetrical rates: 2.5 Gbps downstream and 100 Mbps upstream; 5 Gbps downstream and 100 Mbps upstream; 10 Gbps downstream and 100 Mbps upstream; 10 Gbps downstream and 1 Gbps upstream; and the following symmetrical rates: 1 Gbps downstream and 1 Gbps upstream; 2.5 Gbps downstream and 2.5 Gbps upstream; and 5 Gbps downstream and 5 Gbps upstream. (¶0088 - While the present disclosure discusses the asymmetric PHY using specific examples and numbers for illustration, variations of the examples set forth herein are contemplated. For example in the disclosure below, the 2.5GBASE-T1, 5GBASE-T1, and 10GBASE-T1 PHY is used as the high speed path running 2.5 Gb/s, 5 Gb/s and 10 Gb/s respectively and a low speed path of 10 Mb/s is used. However, the teaching set forth herein can be generalized to other PHYs such as 1000BASE-T1, 100BASE-T1, 1000BASE-T, 2.5GBASE-T, 5GBASE-T, 10GBASE-T (note -T not -T1) and the low speed path can be something other than 10 Mb/s (i.e. 100 Mb/s, 1000 Mb/s, etc.).
Re. Claim 20, LO, TU, and Sederat teach claim 16
Yet, LO, TU, and Sederat, do not expressly teach the device of claim 16 wherein the pyhL blocks comprises payload, OAM/reserved allocation, and forward error correction data;
However in analogous art, TU explicitly discloses the device of claim 16 wherein the pyhL blocks comprises payload, OAM/reserved allocation, and forward error correction data.; (¶0077 - The example bit ordering 1500 begins with 80-bit data blocks 1510 that are appended with a header and encoded to 81-bit data blocks 1520 by the PCS encoder 232. Forty-five 81-bit data blocks plus a 9-bit operations, administration, and maintenance (OAM) block are aggregated to form the RS encoder 234 payloads 1530. The RS encoder 234 generates RS symbols 1540 (or codewords) from the payloads. The scrambler 236 performs an XOR operation on the RS symbols 1540 and the scrambler sequence and outputs the scrambled data blocks to the signal mapper 238. Thus, the OAM blocks (in addition to the data blocks) are encoded by the RS encoder 234 and scrambled by the scrambler 236. The signal mapper 238 maps three bits of the scrambled data blocks to two ternary symbols to generate the PAM symbols 1550.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include having the pyhL blocks comprising of payload, OAM/reserved allocation, and forward error correction data;
The motivation for doing so would be for establishing link for single pair ethernet. (¶0002)
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over LO, in view of TU, further in view of Sederat, and further in view of Sujan Pandey et al. (US 10439761), Pandey hereinafter.
Re. Claim 21, LO, TU, and Sederat teach claim 9.
Yet, LO, TU, and Sederat, do not expressly teach discloses the device of claim 20 wherein each pyhL block comprises 211.25 bytes of payload, 22 bits of OAM/reserved allocation, and 26 bits of forward error correction data.
However in analogous art, Pandey explicitly discloses wherein each pyhL block comprises 211.25 bytes of payload, 22 bits of OAM/reserved allocation, and 26 bits of forward error correction data. (¶0050 - As described above, the technique for performing physical layer operations in a communications network involves utilizing an OAM word in an FEC frame. FIG. 2A depicts an example of an FEC frame 230 (M bits) that can be used to communicate information that is used to set and/or adjust the level of interleaving in an Ethernet based in-vehicle network. As depicted in FIG. 2A, the FEC frame 230 includes payload bits 232 (K bits, K.sub.1, K.sub.2, K.sub.3, . . . K.sub.i) and OAM bits 234 (X bits, X.sub.1, X.sub.2, X.sub.3, . . . X.sub.j) (also referred to collectively herein as an “OAM word”), with parity bits 236 (P bits, P.sub.1, P.sub.2, P.sub.3, . . . P.sub.M−i−j) interspersed within the payload bits and the OAM bits. In the example of FIG. 2A, the payload bits include bits of data received from a higher layer in the network stack, e.g., from the data link layer and which are intended to be communicated across the link to the same higher layer in the receiving node, the OAM bits include bits of operations, administration, and management information that are communicated between the physical layers (e.g., between the PHY chips) in OAM words, and the parity bits are bits added to strings of binary values in the FEC frame to provide a check on the corresponding bit values in the FEC frame. In an embodiment, an FEC frame is M bits, including K bits of data, X bits of OAM data, and M—K—X parity bits. In an embodiment, an FEC frame makes up a portion of a PDU such as an Ethernet PDU.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to specify each pyhL block comprises 211.25 bytes of payload, 22 bits of OAM/reserved allocation, and 26 bits of forward error correction data.
The motivation for doing so would be for receiving OAMs and setting interleaving levl as a response (Abstract)
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over LO, in view of TU, further in view of Sederat, and further in view of Andrew Yang et al. (2009/0304022), Andrew Yang hereinafter.
Re. Claim 15, LO, TU, and Sederat teach claim 9.
Yet, LO, TU, and Sederat, do not expressly teach discloses the method of claim 9 wherein in the case of 10.000 Gbps data rate from a MAC, the XGMII rate is 10.105 Gbps and the transmit line rate is 16 Gbps.;
However in analogous art, Yang explicitly discloses wherein in the case of 10.000 Gbps data rate from a MAC, the XGMII rate is 10.105 Gbps and the transmit line rate is 16 Gbps.;. (¶0018 - includes a network MAC 201 that may be configured to provide a number of features including full duplex operation at 10 Gbps, The four lanes may be bonded together into a single logical interface link to form the XAUI port. ¶0020 - The XAUI 202 may be configured to communicate directly with an optical transceiver (not shown). The XAUI 202 port may also include independently controllable physical coding sublayer (PCS) functionality. It is contemplated that in other embodiments, other types of interfaces to the network such as a 10 Gigabit media independent interface (XGMII), for example, may be used. ¶0027 - In such an implementation, each such port may be configured as a PCIe endpoint that provides 16 Gbps of full duplex user bandwidth to the PCIe hierarchy of a processing unit 30. In addition, each I/O interface link may also include an integrated SerDes per lane, each of which may run at 2.5 Gbps. The eight lanes may be bonded together into a single logical interface link that runs at 16 Gbps. The PIO unit 223 includes configuration and status registers, and supports memory mapped I/O posted and non-posted transactions, and as described above each I/O interface unit 25 may be connected to a single respective processing unit such as processing unit 30a of FIG. 1, for example. It is noted that in other implementations, other lane and link speeds may be used. For example, the lanes may each operate at 5 Gbps, for a total of 32 Gbps of full duplex user bandwidth to the PCIe hierarchy.
The reference clearly states the 10 Gbps MAC rate, a variable or other link speed XGMII rate, and a 16 Gbps transmit rate. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to specify the case of 10.000 Gbps data rate from a MAC, the XGMII rate is 10.105 Gbps and the transmit line rate is 16 Gbps.
The motivation for doing so would be for establishing link for to have shared resources in a networked environment. (¶0005)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over LO, in view of TU, further in view of Sederat, and further in view of Andrey Belogolovyl et al. (2009/0010318), Belogolovyl hereinafter.
Re. Claim 2, LO, TU, and Sederat teach claim 1.
Yet, LO, TU, and Sederat, do not expressly teach the device of claim 1 wherein the first data comprises 64 bits of payload and 4 bits of control per 32 bits of payload;
However, in analogous art, Belogolovyl explicitly discloses wherein the first data comprises 64 bits of payload and 4 bits of control per 32 bits of payload (¶0019 - The framer 210 may receive the bit stream and generate one or more frames by dividing the bit stream into smaller pieces of pre-specified size and adding control bits. The framer 210 may add control bits such as synchronization bits, cyclic redundancy check bits, and stuffing bits to cause frame alignment, error detection, and to mark the frame boundaries. In one embodiment, each frame may comprise a payload bits and control bits.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include having the first data comprising of 64 bits of payload and 4 bits of control per 32 bits of payload
The motivation for doing so would be to correct to implement an efficient scheme of communicating between devices. (Background)
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over LO, in view of TU, further in view of Sederat, and further in view of Chengdu Wei Su et al. (2018/0098076), Wei Su hereinafter;
Re. Claim 3, LO, TU, and Sederat teach claim 1.
Yet, LO, TU, and Sederat, do not expressly the device of claim 1 wherein the XGMII encoding comprises 64b/65b encoding or 64B/66b encoding.
However, in analogous art, Wei Su explicitly discloses wherein the XGMII encoding comprises 64b/65b encoding or 64B/66b encoding. (¶0063 - The packet service refers to a service based on a packet transfer technology. A length of a packet that carries a service is variable. An idle character is included between adjacent packets. A quantity of idle characters is also variable. The packet service includes an Internet Protocol (IP) service, an Ethernet service, a multiprotocol label switching (MPLS) service, and the like. The code block stream in this embodiment of the present disclosure refers to a data stream including code blocks. The code block may be an 8B/10B code block, a 64B/66B code block, a 64B/65B code block, a 256B/258B code block, a 256B/257B code block, or another code block.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include the XGMII encoding comprises 64b/65b encoding or 64B/66b encoding.
The motivation for doing so would be to increase bandwidth utilization. (Background)
Re. Claim 17, LO, TU, and Sederat teach claim 16.
Yet, LO, TU, and Sederat, do not expressly wherein the XGMII encoding comprises 64b/65b encoding or 64B/66b encoding.
However in analogous, Wei Su explicitly discloses wherein the XGMII encoding comprises 64b/65b encoding or 64B/66b encoding. (¶0063 - The packet service refers to a service based on a packet transfer technology. A length of a packet that carries a service is variable. An idle character is included between adjacent packets. A quantity of idle characters is also variable. The packet service includes an Internet Protocol (IP) service, an Ethernet service, a multiprotocol label switching (MPLS) service, and the like. The code block stream in this embodiment of the present disclosure refers to a data stream including code blocks. The code block may be an 8B/10B code block, a 64B/66B code block, a 64B/65B code block, a 256B/258B code block, a 256B/257B code block, or another code block.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include the XGMII encoding comprises 64b/65b encoding or 64B/66b encoding.
The motivation for doing so would be to increase bandwidth utilization. (Background)
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over LO, in view of TU, further in view of Sederat, and further in view of Andrew Mills et al. (US6795450), Mills hereinafter;
Re. Claim 7, LO, TU, and Sederat teach claim 1.
Yet, LO, TU, and Sederat, do not expressly teach the device of claim 1 further comprising incorporating idle symbols, prior to burst mapping, to reduce the effective data rate.
However, in analogous art, Mills explicitly discloses The device of claim 1 further comprising incorporating idle symbols, prior to burst mapping, to reduce the effective data rate.. (¶0078 - In an embodiment for a 100BASE-TX link, when link-suspend mode is enabled and active, a LS Switch PHY transmitter will start sending LSPs 530 within the timeframe LSPPeriod 532, following the end of transmitting a valid frame 502. LSPs may be made up of a series of scrambled idle symbol bursts, consisting typically of 32 symbols. The number of symbols in an idle burst may be altered via the parameter LSPWidth 534, allowing a range of 32 up to 512 symbols (default 32). The LSPPeriod period parameter may be programmed as multiples of a base value of 512 ms, for example. In this case, LSPPeriod 532 may be equal to "0", causing an LSP pulse to occur every 512 ms, or "3" (e.g. binary 11, as shown in FIG. 7) extending the period to 2048 ms. In addition, the PHY may transmit a normal data frame 502, when TXEN (Transmit Enable) is asserted at the LS modified MII transmit interface, and ceases sending LSPs until the frame is completely transmitted 502. Further embodiments include LSPs having fixed non-programmable LSP Width and LSP Period)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include incorporating idle symbols, prior to burst mapping, to reduce the effective data rate.
The motivation for doing so would be to notify the capability to support LS Mode as well as support “wake-up” schemes. (Abstract)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over LO, in view of TU, further in view of Sederat, and further in view of Hossien Sederat et al. (US11552776), Sederat 2 hereinafter;
Re. Claim 11, LO, TU, and Sederat 1 teach claim 9.
Yet, LO, TU, and Sederat 1, do not expressly teach the method of claim 9 further comprising performing time domain duplexing bursting with an ASA compatible PCS.
However, in analogous art, Sederat 2 explicitly discloses further comprising performing time domain duplexing bursting with an ASA compatible PCS. (¶33 - To configure the hybrid physical layer component 200 to support ASA, the central processing component 206 communicates with the various components, such as the transmitter component 202, the receiver component 204 and the PCS component 208 to cause the components to initiate the LPI mode. The hybrid physical layer component 200 also cause the PCS component 208 to operate according to ASA, such as by performing the appropriate startup and training sequences for ASA as well as formatting data using the appropriate framing structures, bit-packing format, headers, preambles, and the like, for ASA.)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include performing time domain duplexing bursting with an ASA compatible PCS
The motivation for doing so would be to notify the capability have a hybrid ethernet asa scheme. (Abstract)