DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-20 are pending; claims 1 and 15 are independent.
Response to Arguments
Applicant's arguments filed 05/28/2026 have been fully considered but they are not persuasive.
Rejection to claims 1-19 under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement has been withdrawn based on explanation in the remark.
In response to applicant’s argument that in claims 1 and 15 require that the same point on the low level line overlap, both the gate electrode of the driving transistor and the anode of the LED when viewed from the top, i.e.., in a plan view of the organic light emitting diode display device.
However, the examiner respectfully disagrees, Kim as a primary reference taught in figs 5A/B, fig. 6 and (figs 7A/B as cross-sectional view), wherein the low-potential supply line 162, as illustrated in FIGS. 5B and 6, include the first and second low-potential supply lines 162a and 162b crossing each other. The cathode electrode 136 is electrically connected to the low-potential supply line 162 and gate electrode 102 (Para 0071).
Park as a secondary reference discloses a second driving low voltage line 176-1 overlaps a driving low voltage line 156 and extends in the second direction. The second driving low voltage line 176-1 and the driving voltage line 155 are connected through an opening 86-1. Wherein the extended part 192-1 of the anode and the driving low voltage line 156 overlap to form the additional capacitors Ca and Cb (figs 13-14 and Paras 0233-0238). The second driving low voltage line 176-1 is also disposed per three pixel columns. The three pixels PX1, PX2, and PX3, and the gate electrode 154 of the driving transistor T1 of each of the pixels PX1, PX2, and PX3 may be formed with various sizes. Here, the three pixels PX1, PX2, and PX3 may respectively display one color among three primary colors. For example, pixel PX1 could display red, pixel PX2 could display green, and pixel PX3 could display blue (fig. 17 and Para 0287).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 13, 15-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2019/0189721), and further in view of Park (US 2020/0185481), hereinafter “Park”.
Regarding claim 1, Kim teaches an organic light emitting diode display device (fig. 1), comprising:
a substrate having a plurality of subpixels (figs 3A/B and Para 026, wherein the display panel 200 is divided into an active area AA provided on a substrate 101. The active area AA displays an image using unit pixels arranged in a matrix form. The unit pixel may include red (R), green (G), and blue (B) subpixels);
a driving transistor in each of the plurality of subpixels on the substrate (fig. 5A/B, a driving transistor DT and Para 0037);
a light emitting diode in each of the plurality of subpixels (fig. 5A/B, a light-emitting element 130 and Para 0037);
a first planarizing layer on the driving transistor of each of the plurality of subpixels such that the first planarizing layer is between the light emitting diode and the driving transistor of each of the plurality of subpixels (figs 7A/B, the first planarization layer 126, Paras 0071 and 0073);
a low level line on the first planarizing layer in a cross-sectional view of the organic light emitting diode display device in each of the plurality of subpixels (figs 7A/B as cross-sectional view and Para 0071, wherein the second low-potential supply line 162b is formed on the first planarization layer 126),
the low level line between the driving transistor and the light emitting diode in the cross- sectional view such that the low level line overlaps a portion of the driving transistor in the cross-sectional view (figs 7A/B as cross-sectional view, wherein the cathode electrode 136 is electrically connected to the low-potential supply line 162 and gate electrode 102, Para 0071);
a second planarizing layer between the low level line and the light emitting diode; and a connecting electrode between the first planarizing layer and the second planarizing layer, the connecting electrode connected to an anode of the light emitting diode (figs 7A/B and Para 0075, the second planarization layer 128 and Paras 0071-0075, wherein the second low-potential supply line 162b is electrically connected to the first low-potential supply line 162a, which is exposed through a first line contact hole 164 formed in the upper interlayer insulation layer 124 and the first planarization layer 126).
Kim does not expressly disclose a same point on the low level line overlaps both a gate electrode of the driving transistor and an anode the light emitting diode in a plan view of the organic light emitting diode display device;
However, Park discloses “a same point on the low level line overlaps both a gate electrode of the driving transistor and an anode the light emitting diode in a plan view of the organic light emitting diode display device”, see figs 13-14, Paras 0233-0238, fig. 17 and Para 0287.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Kim by applying the teaching of Park to include a second driving low voltage line 176-1 overlaps a driving low voltage line 156 and extends in the second direction. The second driving low voltage line 176-1 and the driving voltage line 155 are connected through an opening 86-1. The second driving low voltage line 176-1 is also disposed per three pixel columns. Wherein the extended part 192-1 of the anode and the driving low voltage line 156 overlap to form the additional capacitors Ca and Cb, as a known technique to yield a predictable result.
Regarding claim 2, Kim in view of Park teaches the organic light emitting diode display device of claim 1, wherein the plurality of subpixels include red, green and blue subpixels (Para 0026, wherein the unit pixel may include red (R), green (G), and blue (B) subpixels, Kim), and
wherein the low level line of the green subpixel is disposed between a gate electrode of the driving transistor of the green subpixel and an anode of the light emitting diode of the blue subpixel in a cross-sectional view (figs 5A/B and Paras 0042-0043, wherein the low-potential supply line 162 (162a/162b), included in the pixel-driving circuit, is formed to have a mesh shape so as to be shared by at least two subpixels. The second low-potential supply line 162b is disposed parallel to the data line DL, and is formed in a number of one for at least two subpixels, from fig. 3A, the green subpixel and the blue subpixel are adjacent to each other, Kim).
Regarding claim 3, Kim in view of Park teaches the organic light emitting diode display device of claim 2, wherein an anode of the light emitting diode of the red subpixel is disposed in the red subpixel, wherein an anode of the light emitting diode of the green subpixel is disposed in the red and green subpixels, and wherein the anode of the light emitting diode of the blue subpixel is disposed in the green and blue subpixels (figs 3A/B and Para 0026, Kim).
Regarding claim 4, Kim in view of Park teaches the organic light emitting diode display device of claim 1, wherein a low level voltage supplied to a cathode of the light emitting diode is applied to the low level line (figs 5A/B and Paras 0042-0043, Kim).
Regarding claim 5, Kim in view of Park teaches the organic light emitting diode display device of claim 1, further comprising a storage capacitor connected to the driving transistor in each of the plurality of subpixels (figs 5A/B, a capacitor Cst), wherein the storage capacitor includes a storage electrode which covers a gate electrode of the corresponding driving transistor (fig. 7A and Para 063, the upper storage electrode 184 is connected to the other one of the second gate electrode 102 of the driving transistor DT, Kim ).
Regarding claim 13, Kim in view of Park teaches the organic light emitting diode display device of claim 5, wherein the storage electrode completely covers the gate electrode such that the gate electrode is not exposed outside the storage electrode (fig. 7A and Para 063, the upper storage electrode 184 is connected to the other one of the second gate electrode 102 of the driving transistor DT, Kim).
Regarding claim 15, Kim teaches an organic light emitting diode display device (fig. 1), comprising:
a substrate having first and second subpixels (figs 3A/B and Para 026, wherein the display panel 200 is divided into an active area AA provided on a substrate 101. The active area AA displays an image using unit pixels arranged in a matrix form. The unit pixel may include red (R), green (G), and blue (B) subpixels);
a driving transistor in each of the first and second subpixels on the substrate (fig. 5A/B, a driving transistor DT and Para 0037);
a light emitting diode in each of the first and second subpixels on the driving transistor (fig. 5A/B, a light-emitting element 130 and Para 0037);
a first planarizing layer on the driving transistor of each of the first and second subpixels such that the first planarizing layer is between the light emitting diode and the driving transistor of the first subpixel and between the light emitting diode and the driving transistor of the second subpixel ((figs 7A/B, the first planarization layer 126, Paras 0071 and 0073);
a low level line on the first planarizing layer in a cross-sectional view of the organic light emitting diode display device (figs 7A/B as cross-sectional view and Para 0071, wherein the second low-potential supply line 162b is formed on the first planarization layer 126),
the low level line between a gate electrode of the driving transistor of the first subpixel and an anode of the light emitting diode of the second subpixel in the cross-sectional view (figs 7A/B as cross-sectional view, wherein the cathode electrode 136 is electrically connected to the low-potential supply line 162 and gate electrode 102, Para 0071); and
a second planarizing layer between the low level line and the light emitting diode; and a connecting electrode between the first planarizing layer and the second planarizing layer, the connecting electrode connected to an anode of the light emitting diode (figs 7A/B and Para 0075, the second planarization layer 128 and Paras 0071-0075, wherein the second low-potential supply line 162b is electrically connected to the first low-potential supply line 162a, which is exposed through a first line contact hole 164 formed in the upper interlayer insulation layer 124 and the first planarization layer 126).
Kim does not expressly disclose a same point on the low level line overlaps both the gate electrode of the driving transistor of the first subpixel and the anode of the light emitting diode of the second subpixel in a plan view of the organic light emitting diode display device.
However, Park discloses “a same point on the low level line overlaps both the gate electrode of the driving transistor of the first subpixel and the anode of the light emitting diode of the second subpixel in a plan view of the organic light emitting diode display device”, see figs 13-14, Paras 0233-0238, fig. 17 and Para 0287.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Kim by applying the teaching of Park to include a second driving low voltage line 176-1 overlaps a driving low voltage line 156 and extends in the second direction. The second driving low voltage line 176-1 and the driving voltage line 155 are connected through an opening 86-1. The second driving low voltage line 176-1 is also disposed per three pixel columns. Wherein the extended part 192-1 of the anode and the driving low voltage line 156 overlap to form the additional capacitors Ca and Cb, as a known technique to yield a predictable result.
Regarding claim 16, Kim in view of Park teaches the organic light emitting diode display device of claim 15, further comprising a storage capacitor connected to the driving transistor in each of the first and second subpixels (figs 5A/B, a capacitor Cst), wherein the storage capacitor includes a storage electrode which covers the gate electrode of the corresponding driving transistor (fig. 7A and Para 063, the upper storage electrode 184 is connected to the other one of the second gate electrode 102 of the driving transistor DT, Kim).
Regarding claim 17, Kim in view of Park teaches the organic light emitting diode display device of claim 1, wherein the driving transistor and the light emitting diode overlap each other (fig. 7A, wherein the drive transistor 100 and the light emitting diode 130 overlap each other), and the low level line is disposed between the driving transistor and the light emitting diode overlapping each other (figs 7A/B as cross-sectional view, wherein the cathode electrode 136 is electrically connected to the low-potential supply line 162 and gate electrode 102, Para 0071, Kim).
Regarding claim 19, Kim in view of Park teaches the organic light emitting diode display device of claim 1, wherein the low level line is disposed directly above the portion of the driving transistor, and the light emitting diode is disposed directly above the low level line (figs 13-14 and Paras 0233-0238, Park)
Claim(s) 6-7 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Park, and further in view of JI (US 2019/0295476).
Regarding claim 6, Kim in view of Park teaches the organic light emitting diode display device of claim 1, wherein each of the plurality of subpixels comprises: a first transistor connected to a data line and switched according to a gate first voltage (figs 5B and Paras 0038-0039, wherein a first switching transistor ST1 connected to the data line DL, Kim);
a storage capacitor connected to the first transistor and including first and second capacitor electrodes (figs 5A/B, a capacitor Cst, Kim);
a second transistor as the driving transistor connected to a high level line and switched according to a voltage of the second capacitor electrode of the storage capacitor (fig. 5A, a driving transistor DT and Para 0037, Kim);
a fourth transistor connected to the storage capacitor and a reference line and switched according to an emission voltage (fig. 5B, transistor ST2 and Para 0040, Kim);
Kim in view of Park does not expressly disclose a third transistor connected to the storage capacitor and the second transistor and switched according to a gate second voltage; a fifth transistor connected to the second transistor and the light emitting diode and switched according to the emission voltage; and a sixth transistor connected to the light emitting diode and the reference line and switched according to the gate second voltage.
However, JI discloses a third transistor connected to the storage capacitor and the second transistor and switched according to a gate second voltage (fig. 1, M2 and Para 0038);
a fifth transistor connected to the second transistor and the light emitting diode and switched according to the emission voltage (fig. 1, M7 and Para 0038); and
a sixth transistor connected to the light emitting diode and the reference line and switched according to the gate second voltage (fig. 1, M5 and Para 0034).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Kim, in view of Park by applying the teaching of JI to include a pixel circuit effectively avoiding the problem of the display unevenness of the display device, due to the difference in the current flowing into the light-emitting diode caused by the power voltage drop (Para 0006, JI).
Regarding claim 7, Kim, in view of Park and in view of JI teaches the organic light emitting diode display device of claim 6, wherein the fifth transistor is connected to the light emitting diode through the connecting electrode, and wherein the connecting electrode has a same layer and a same material as the low level line (fig. 1, M7 and Para 0038, JI).
Regarding claim 10, Kim, in view of Park and in view of JI teaches the organic light emitting diode display device of claim 6, wherein during an initial period, the gate first voltage and the emission voltage have a low level voltage and the gate second voltage has a high level voltage, during a sensing period after the initial period, the gate first voltage and the gate second voltage have the low level voltage and the mission voltage has the high level voltage, during a holding period after the sensing period, the gate first voltage, the gate second voltage and the emission voltage have the high level voltage, and during an emission period after the holding period, the gate first voltage and the gate second voltage have the high level voltage and the emission voltage has the low level voltage (fig. 2 and Paras 0043-0054, JI).
Regarding claim 11, Kim, in view of Park and in view of JI teaches the organic light emitting diode display device of claim 6, further comprising a gate first line transmitting the gate first voltage (fig. 5B, Para 0039 and a scan control signal SC1 from the first scan line SL1, Kim),
a gate second line transmitting the gate second voltage (fig. 5B, Para 0040 and a scan control signal SC2 from the first scan line SL2, Kim), and
an emission line transmitting the emission voltage (fig. 5B, Para 0041 and an emission control signal EM from the emission control line EL, Kim),
wherein the gate first line (fig. 5B, the first scan line SL1), the gate second line (fig. 5B, the second scan line SL2) and the emission line (fig. 5B, the emission control line EM) are disposed in a horizontal direction parallel to a long side of the organic light emitting diode display device (fig. 5B, Kim) and
the reference line (fig. 5B, the reference line RL), the low level line (fig. 5B, the second low-potential supply line 162b), the high level line (fig. 5B, the second high-potential supply line 172b) and the data line (fig. 5B, the data line DL) are disposed in a vertical direction parallel to a short side of the organic light emitting diode display device (fig. 5B, Kim).
Regarding claim 12, Kim, in view of Park and in view of JI teaches the organic light emitting diode display device of claim 11, wherein the gate first line, the gate second line, and the emission line are sequentially disposed along the vertical direction (fig. 5B the first scan line SL1, the second scan line SL2 and , the emission control line EM, Kim), and
the reference line, the low level line, the high level line and the data line are sequentially disposed along the horizontal direction (fig. 5B the reference line RL, the second low-potential supply line 162b, the second high-potential supply line 172b and the data line DL, Kim).
Claim(s) 8-9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Park, in view of JI (US 2019/0295476), and further in view of Park (US 2020/0302869), hereinafter “Park 69”.
Regarding claim 8, Kim in view of Park in view of JI teaches the organic light emitting diode display device of claim 6, wherein a first interlayer insulating layer is disposed on a gate electrode of the second transistor (fig. 7A, Paras 0058 and 0062, the upper interlayer insulation layer 124 and the second gate electrode 102 of the driving transistor DT, Kim).
wherein a storage electrode is disposed on the first interlayer insulating layer over and corresponding to the gate electrode of the second transistor (fig. 7A and Paras 0063-0064, Kim),
wherein a second interlayer insulating layer is disposed on the storage electrode (fig. 7A and Para 0063, wherein the upper storage electrode 184 of the storage capacitor Cst 180 is exposed through a storage contact hole 188 formed in the second lower interlayer insulation layer 118, Kim),
wherein the low level line is disposed on the first planarizing layer over and corresponding to the gate electrode of the second transistor (fig. 7B and Para 0071, wherein the second low-potential supply line 162b is formed on the first planarization layer 126, which is the same layer as the pixel connection electrode 142, Kim),
wherein the second planarizing layer is disposed on the low level line (fig. 7B and para 0075, the second low-potential supply line 162b and the second planarization layer 128, Kim), and
wherein the anode of the light emitting diode is disposed on the second planarizing layer corresponding to the low level line (fig. 7A and Para 0066, wherein the anode electrode 132 is formed in a second planarization layer 128, Kim).
Kim in view of Park and in view of JI does not expressly disclose wherein a drain electrode of the third transistor connected to the gate electrode of the second transistor is disposed on the second interlayer insulating layer, wherein the first planarizing layer is disposed on the drain electrode of the third transistor.
However, “Park 69” discloses wherein a drain electrode of the third transistor connected to the gate electrode of the second transistor is disposed on the second interlayer insulating layer (figs 15, 16 and Paras 0134-0140), wherein the first planarizing layer is disposed on the drain electrode of the third transistor, see (figs 15, 16 and Paras 0145-0146).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Kim in view of Park and in view of JI by applying a known technique of “Park 69” to include a pixel circuit comprising a thin-film transistor, a gate insulating layer and a planarization layer, as a known technique to yield a predictable result.
Regarding claim 9, Kim in view of Park and in view of JI teaches the organic light emitting diode display device of claim 6, wherein the third transistor is further connected to the fifth transistor (fig. 1, M2, M7 and Para 0034, JI),
Kim in view of Park, in view of JI and in view of “Park 69” discloses the third transistor has a dual gate type, and the second gate voltage is applied to two gate electrodes of the third transistor (fig. 4, ST2 and Par 0079, “Park 69”).
Regarding claim 14, Kim in view of Park, in view of JI and in view of “Park 69” teaches the organic light emitting diode display device of claim 8, wherein the low level line completely covers the drain electrode of the third transistor and the gate electrode of the second transistor such that the drain electrode of the third transistor and the gate electrode of the second transistor are not exposed outside the low level line (fig. 7 and Paras 0071-073, Kim).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Park, and further in view of Hwang (US 2019/0279563).
Regarding claim 18, Kim in view of Park teaches the organic light emitting diode display device of claim 1, wherein the plurality of subpixels include a first subpixel and a second subpixel (figs 3A/B and Para 026, wherein the unit pixel may include red (R), green (G), and blue (B) subpixels, Kim),
wherein the low level line overlaps the gate electrode of the driving transistor of the first subpixel in the cross-sectional view of the organic light emitting diode display device (fig. 7B and Para 0071, wherein the second low-potential supply line 162b is formed on the first planarization layer 126, which is the same layer as the pixel connection electrode 142, Kim); and
Kim in view of Park does not expressly disclose wherein the anode of the light emitting diode of the second subpixel overlaps a gate electrode of the driving transistor of the first subpixel in the cross-sectional view of the organic light emitting diode display device.
However, Hwang “wherein the anode of the light emitting diode of the second subpixel overlaps a gate electrode of the driving transistor of the first subpixel in the cross-sectional view of the organic light emitting diode display device, see fig. 3 and Para 0068.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Kim in view of Park by applying a known technique of Hwang to include anode extension portion formed to be connected to a transistor of a sub-pixel circuit in a row different from a row in which the OLED is disposed, as a known technique to yield a predictable result.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2019/0189721), and further in view of Park (US 2020/0185481), hereinafter “Park”, and further in view of Ikeda (US 2021/0407385).
Regarding claim 20, Kim in view of Park teaches the organic light emitting diode display device of claim 1, wherein the plurality of subpixels include red, green and blue subpixels (Para 0026, wherein the unit pixel may include red (R), green (G), and blue (B) subpixels, Kim), and
Kim in view of Park does not expressly disclose wherein the low level line of the green subpixel overlaps the gate electrode of the driving transistor of the green subpixel and the anode of the light emitting diode of the blue subpixel.
However, Ikeda “wherein the low level line of the green subpixel overlaps the gate electrode of the driving transistor of the green subpixel and the anode of the light emitting diode of the blue subpixel”, see fig. 2, fig, 7 and Para 0101.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Kim in view of Park by applying a known technique of Ikeda wherein a counter electrode 25 (equivalent to a low level line) is provided in a region where the anode electrode 23 overlaps with the driving transistor DRT to shield the anode electrode 23 and the light emitting element 3 from the transistors and various wirings on the array substrate 2, it is readily available to those skilled in the art to set a low level line between the gate of the drive transistor of the green sub-pixel and the anode of the light emitting diode of the blue sub-pixel. Since the luminous efficiency of a blue organic light emitting diode is low and the area of the blue light emitting diode/anode of the blue sub-pixel's light emitting diode is large, it is a common technical means in the art to overlap the anode of the blue sub-pixel's light emitting diode with the driving transistor of the adjacent green sub-pixel, as a known technique to yield a predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang (US 2022/0051627), relate to a pixel circuit and a driving method thereof, a display substrate, and a display panel.
Ko (US 10,004,124), relates to an electroluminescent display device including pixels, a pixel circuit of each of the pixels comprising a capacitor connected between a first and second node, a driving transistor connected to the second node, a third node, and a first supply voltage, a first transistor supplying the first supply voltage or a reference voltage to the first node, a second transistor supplying the reference voltage to the second node.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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/S.E.E/Examiner, Art Unit 2625 8/12/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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