Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In view of the appeal brief filed on 01/14/2026, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/JOSHUA BENITEZ ROSARIO/ Supervisory Patent Examiner, Art Unit 2815
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 22 – 23, 25, 29 – 33, and 37 - 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2019128118 A1 hereinafter Hsieh in further view of US 20140042457 A1 hereinafter Shibata.
For claim 10, Hsieh teaches a method of manufacturing a semiconductor device, comprising: providing a substrate (Hsieh, fig. 15F numeral 1532); forming a semiconductor stack on the substrate, the semiconductor stack comprising a side surface (fig. 15F shows semiconductor stack 862; figures 2A - 2C show detailed embodiments of the semiconductor stack including the semiconductor stack shown in figure 2A numeral 122); forming an electrode on the semiconductor stack (fig. 2A shows electrodes 1241A on a surface of semiconductor stack 122, the surface being a surface of the semiconductor layer 1221 and active layer 1222); forming a resin on the electrode (figure 15F shows resin 340’ formed on the electrode of semiconductor stack 864; fig. 4E shows resin 440b and 440a formed on the electrodes of the semiconductor stacks); and forming a conductive bump on the electrode, wherein the conductive bump is covered by the resin (fig. 4E shows conductive bumps 444 and 443b formed on the electrodes 1241C-2 of the semiconductor stack; figures 14A and 14B show in more detail resin 340’ and 340 formed on conductive bumps 852, the bumps being on the electrodes of the semiconductor stack 862). Hsieh does not explicitly state the electrode is formed on a side surface of the semiconductor stack. Hsieh does teach that the electrode can have different shapes and location placements (fig. 1A – 1C numeral 124; fig. 2A numeral 1241a and 1242A).
Shibata teaches manufacturing of a semiconductor device (Shibata, fig. 5) comprising a semiconductor stack (fig. 5 numeral 3, 4a, and 5) with an electrode formed on a side surface of the semiconductor stack (fig. 5 numeral 6 and 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the side surface contacting electrodes in Shibata with the electrodes in Hsieh in order to reduce the contact resistances between the electrodes and the semiconductor stack (Shibata, Par. [0044]). Hsieh also teaches that having a larger surface area allows the electrodes to better connect with external elements (Hsieh, “Contact electrodes 1241A, 1242A have a larger bottom surface area or width relative to conductive pads 1211A, 1212A, which may be more easily connected to external electrodes (not shown)”; Par. [0097]). One of ordinary skill in the art before the effective filing date of the immediate invention would recognize increasing the size of the electrodes to cover the side surfaces of the semiconductor stack as taught in Shibata would also improve the ability for the electrodes to connect with external elements as taught by Hsieh.
For claim 22, Hsieh and Shibata teach all of claim 10. Hsieh also teaches further a plurality of conductive particles distributed in the resin (Hsieh, fig. 14A shows conductive particles 342 present in the resin 340’), and the conductive particles are subjected to a heat process to gather to form the conductive bump (fig. 14B shows the conductive particles 344 forming the conductive bump over the electrodes of the semiconductor stack 862; Par. [0130], Par. [0147], Par. [0140 - 0141]; “Referring to FIG. 13B, after curing, the connection structure 340 is formed, and the conductive particles 342 are melted and accumulated in the bonding region 1301 and become the electrical connection portion 344. Further, the resin 341 is cured to become the protective portion 343. In an embodiment, a small portion of the conductive particles 342 are dispersed in the non-bonding region 1302. The conductive particles 342 in the non-bonding region 1302 are at least partially separated from each other and thus do not cause a short circuit. 14A and 14B are schematic views showing a connection structure before and after curing in a light-emitting device according to another embodiment of the present invention. Before curing, referring to Fig. 14A, in contrast to Fig. 13A, the resin 341 is formed under and around the two light-emitting elements 862, respectively, but separated from each other. Similarly, the non-joining region 1402 has two regions, one for each of the light-emitting elements 862, and the two regions of the non-joining region 1402 are separated from each other. The portion of the land 1401 is the same as that of Fig. 13A. After curing, referring to FIG. 14B, the structure, function, and material of the connection structure 340, the protection portion 343, and the electrical connection portion 344 can be referred to the corresponding paragraphs of FIG. 13B.”).
For claim 23, Hsieh and Shibata teach all of claim 22. Hsieh also teaches the heat process comprises a laser energy irradiating on the conductive particles (Hsieh, fig. 15A – 15F, numeral E4; Par. [0147 – 152] “In one embodiment, the energy E4 is a laser so that heat can be provided in a localized area, such as a joined area. Thereafter, FIG. 15D is continued… In an embodiment, the energy E4 is a laser. A description of the energy E4, the resin, the conductive particles, and the size 340' of this step can be referred to the corresponding paragraphs of Figs. 3C, 8F, 13A to 14B, and 15F. Figure 16E is followed by Figure 16C.”).
For claim 25, Hsieh and Shibata teach all of claim 22. Hsieh also teaches the resin is in a liquid or semi-liquid state during the heat process (Hsieh, Par. [0106 - 0107] and [0114] describes melting and curing the resin to form the conductive bumps). Examiner is interpreting the term melting in Hsieh to mean changing the state of the resin from a solid to a liquid or semi-liquid state. Further, Hsieh describes the conductive particles of the resin as being a liquidus melting point alloy that undergoes liquefaction (Par. [0106 – 0107]).
For claim 29, Hsieh and Shibata teach all of claim 10. Hsieh also teaches the conductive bump has an outermost surface, and the outermost surface is not parallel with the electrode and has a convex arc shape (Hsieh, fig. 14A – 14B shows conductive bumps formed by the conductive particles 342/344 and resin 341/343 as being convex and circular in shape, resulting in a convex arc that overlaps the electrode resulting bumps being not parallel with the electrode.). Hsieh shows a further convex arc shape of the bumps in figure 16C numeral 340.
For claim 30, Hsieh and Shibata teach all of claim 21. Hsieh also teaches providing a target substrate and bonding the conductive bump to the target substrate (Hsieh, fig. 16C shows target substrate 850 and bonding the conductive bump 340 to the target substrate).
For claim 31, Hsieh and Shibata teach all of claim 30. Hsieh also teaches the bonding process comprises a laser applied to the conductive bump (Hsieh, fig. 15F shows the bonding process using energy E4, and energy E4 is described as a laser; Par. [0147 – 0152]).
For claim 32, Hsieh and Shibata teach all of claim 10. Hsieh also teaches a bonding pad on the electrode (Hsieh, fig. 1A – 1C shows embodiments with bonding pads 144a, 114b, and 144c; fig. 2A shows embodiments of the semiconductor stack 122 including a bonding pad 1241A and 1242A), and the bonding pad is subjected to a heat process to form the conductive bump (fig. 4E shows bonding pads applied to the resin and the bump and resin go through a heat process to form conductive bumps seen in figures 7C – 7G; Par. [0107]; Par. [0147]).
For claim 33, Hsieh and Shibata teach all of claim 32. Hsieh also teaches the heat process comprises a laser energy irradiating on the bonding pad (Hsieh, Par. [0147 – 0152]; “In one embodiment, the energy E4 is a laser so that heat can be provided in a localized area, such as a joined area. Thereafter, FIG. 15D is continued… In an embodiment, the energy E4 is a laser. A description of the energy E4, the resin, the conductive particles, and the size 340' of this step can be referred to the corresponding paragraphs of Figs. 3C, 8F, 13A to 14B, and 15F. Figure 16E is followed by Figure 16C.”).
For claim 37, Hsieh and Shibata teach all of claim 10. Hsieh also teaches the semiconductor stack further comprises a first semiconductor layer (Hsieh, fig. 2A numeral 1223), a second semiconductor layer (fig. 2A numeral 1221), and an active layer disposed between the first semiconductor layer and the second semiconductor layer (fig. 2A numeral 1222).
For claim 38, Hsieh and Shibata teach all of claim 37. Hsieh also teaches the active layer comprises a width less than the first semiconductor layer (Hsieh, fig. 2A shows active layer 1222 having a width less than the first semiconductor layer 1223).
For claim 39, Hsieh and Shibata teach all of claim 10. Hsieh also teaches the semiconductor stack further comprises a protective layer between the electrode and the side surface of the semiconductor stack (Hsieh, fig. 2A numeral 123A).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2019128118 A1 hereinafter Hsieh in view of US 20140042457 A1 hereinafter Shibata and in further view of US 20050194676 A1 hereinafter Fukuda.
For claim 21, Hsieh and Shibata teach all of claim 10. Hsieh and Shibata are silent regarding a cleaning step of the resin.
Fukuda teaches forming a resin (Fukuda, fig. 9A numeral 30) on a semiconductor device (fig. 9A numeral 2) that undergoes a cleaning step (fig. 9A numeral 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the cleaning methods in Fukuda with the resin in Hsieh in order to remove any unwanted resin after the heating or curing process (Fukuda, Par. [0074]) which can assist in limiting the devices size or prevent excess resin from being present during other processes, such as etching, laser usage, etc.
Claim(s) 24, and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2019128118 A1 hereinafter Hsieh in view of US 20140042457 A1 hereinafter Shibata in further view of US 20180374738 A1 hereinafter Lee.
For claim 24, Hsieh and Shibata teaches all of claim 23. Hsieh and Shibata are silent regarding the laser energy comprising a UV laser beam, a visible laser beam, or an IR laser beam. Hsieh does teach the resin the beam being used on being a UV sensitive material (Hsieh, Par. [0132]; “In addition, energy E2 is supplied to the adhesive 810' to convert the adhesive 810' into a lower viscosity adhesive 810. In one embodiment, the energy E1 is thermal energy, the energy E2 is ultraviolet light, and the adhesive 810' is an ultraviolet light dissociating gel. A description of the variation of the size 840' of this step can be referred to the corresponding paragraph of Figure 3C.”).
Lee teaches forming a semiconductor stack (Lee, fig. 6A numeral 130), bonding the stack to a target substrate (fig. 6A numeral 210) and the bonding process being performed using a laser (fig. 6A numeral LB1). Lee also teaches the laser beam being an IR or UV laser beam (Par. [0037 - 0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the laser type in Lee with the laser curing process in Hsieh and Shibata in order to bond the semiconductor stack using the UV sensitive adhesive (Hsieh, Par. [0132]) and prevent damage to other layers (Lee, Par. 0038]). One would be driven to optimize the wavelength of the laser used in order to control the energy of the laser beam and to minimize damage caused to layers sensitive to specific wavelengths of the laser.
For claim 34, Hsieh and Shibata teach all of claim 29. Hsieh and Shibata are silent regarding the resin being formed by printing, coating, spraying, or dispensing.
Lee teaches bonding a semiconductor stack (Lee, fig. 7B numeral 130-3) with a material (fig. 7B numeral 231 and 232) to a target substrate, and that the material is formed by a coating process (Par. [0028]; Par. [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the formation methods in Lee with the resin in Hsieh and Shibata, in order to ensure the resin covers a surface of the electrode it is placed on.
Claim(s) 35 – 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2019128118 A1 hereinafter Hsieh in further view of US 20180374738 A1 hereinafter Lee.
For claim 35, Hsieh teaches a method of manufacturing comprising: providing a substrate (Hsieh fig. 15F numeral 1532); forming a semiconductor stack on the substrate, forming an electrode on the semiconductor stack (fig. 2A shows electrodes 1241a and 1242A on a of semiconductor stack 122); and forming a conductive bump on the electrode (fig. 4E shows conductive bumps 444 and 443b formed on the electrodes 1241C-2 of the semiconductor stack; figures 14A and 14B show in more detail resin 340’ and 340 formed on conductive bumps 852, the bumps being on the electrodes of the semiconductor stack 862), providing a target substrate (fig. 15F numeral 850), and bonding the conductive bump to the target substrate by a laser energy (fig. 15F numeral E4 Laser). Hsieh is silent regarding the conductive bump being formed on the electrode by a first laser energy. Hsieh does teach that a first energy is used to form the conductive bumps (fig. 14A – 14B; fig. 8A – 8E) and that the energy used is an energy of ultraviolet light that irradiates the conductive bump (Par. [0132], “After that, a cured adhesive layer (or joint structure) 840 is formed. In addition, energy E2 is supplied to the adhesive 810' to convert the adhesive 810' into a lower viscosity adhesive 810. In one embodiment, the energy E1 is thermal energy, the energy E2 is ultraviolet light, and the adhesive 810' is an ultraviolet light dissociating gel. A description of the variation of the size 840' of this step can be referred to the corresponding paragraph of Figure 3C.”). Hsieh also discloses embodiments that use laser energy (fig. 15F numeral 4E laser; Par. [0147 – 0152]).
Lee teaches a semiconductor stack (fig. 6A numeral 130-3), forming a conductive bump on the electrode of the semiconductor stack (fig. 6A numeral 130-1; fig. 7B numerals 231 and 232), and that the conductive bumps are formed by a laser energy (fig. 7A numeral LB2; Par. [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the conductive bump formation by laser in Lee with the conductive bump formation in Hsieh in order to limit the number of energy sources needed, as Hsieh already teaches using a laser energy source and using the source twice would limit the number of sources needed, and to heat or cure the resin layers that form the conductive bumps in Hsieh without causing damage to other layers (Lee, Par. [0038]; Par. [0047]). One would be driven to optimize the wavelength of the laser used in order to control the energy of the laser beam and to minimize damage caused to layers sensitive to specific wavelengths of the laser.
For claim 36, Hsieh and Lee teach all of claim 35. Lee also teaches the laser beams used being a UV, IR, or visible light laser beam (Lee, Par. [0047]).
Conclusion
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/J.T.N./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815