DETAILED ACTION
Claims 1-20 are pending.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/19/2025 has been entered.
The present application is being examined under the pre-AIA first to invent provisions.
The office acknowledges the following papers:
Claims and remarks filed on 8/19/2025.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-14, and 16-20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sprangle et al. (U.S. 2009/0172349), in view of Mimar (U.S. 2013/0212353), in view of Moyer et al. (U.S. 2005/0055535), in view of Official Notice.
As per claim 1:
Sprangle and Mimar disclosed a device comprising:
a decoder (Sprangle: Figure 1 element 165, paragraph 17);
a memory interface coupled to the decoder and configured to couple to a memory, the memory interface including a set of address generators (Mimar: Figures 1-2 elements 130 and 240, paragraphs 21-22)(Sprangle: Figure 1 elements 160-165 and 310, paragraphs 16-17)(Mimar disclosed a set of LUTs within a data memory. Mimar also disclosed a set of address generators to generate effective addresses sent to each LUT. The combination adds a data memory that contains the set of LUTs and address generators within Sprangle.);
a set of vector registers coupled to the memory interface (Sprangle: Figure 1 element 150, paragraph 17);
a set of processing elements coupled to the set of vector registers in parallel (Sprangle: Figures 1 and 4-7 elements 130-150, paragraphs 19, 54-55, 69, 76-77, and 100-102)(The vector conversion elements and vector arithmetic elements read upon the processing elements.); and
a table lookup unit coupled to the set of vector registers in parallel with the set of processing elements, wherein the table lookup unit is configured to execute a table lookup loop instruction that specifies a vector command, a number of lookup tables in the memory to be accessed in parallel, and an offset for at least one lookup table to be accessed (Mimar: Figures 1-3 and 8 elements 100, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figure 1 elements 22 and 31, paragraphs 13 and 16)(Mimar disclosed vector LUT operations (i.e. table lookup loop instruction) that include a vector command to load data from a set of lookup tables. The LUT operation implicitly indicates loading from 32 LUTs and includes an index value (i.e. offset) for accessing a particular data element within each LUT. The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle.), wherein the decoder is configured to:
receive the vector command that specifies a first set of data in the memory and an address generator of the set of address generators (Mimar: Figures 1-3 and 8 elements 100, 120-131, 200, 240, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3 elements 165, 210-220, paragraphs 13, 16-17, 54-55, 67-68, and 100)(The combination adds a data memory that contains the set of LUTs and address generators within Sprangle. A fetched instruction is decoded by the coprocessor to determine if it’s a vector LUT operation. The vector LUT operation implicitly specifies corresponding address generators coupled to a given LUT.); and
based on the vector command:
cause the address generator to compute one or more addresses for the first set of data (Mimar: Figures 1-3 and 8 elements 100, 120-131, 200, 240, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3 elements 165, 210-220, paragraphs 13, 16-17, 54-55, 67-68, and 100)(The combination adds a data memory that contains the set of LUTs and address generators within Sprangle. The vector LUT operation implicitly specifies corresponding address generators coupled to a given LUT, which generates an effective address sent to the LUT.);
cause the memory interface to write the first set of data from the memory to the set of vector registers (Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, and 310-320, paragraphs 16, 54, 67-69, and 74)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. The vector LUT operation writes data from the LUTs to a destination vector register.); and
cause either the set of processing elements or the table lookup unit to perform an operation on the first set of data to produce a second set of data (Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. The vector LUT operation writes data from the LUTs to a destination vector register. Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers. The combination allows for the vector LUT operation to additionally include a conversion and/or add operation to be performed prior to writing the LUT data to the vector registers. Additionally, official notice is given that vector arithmetic operations can have data dependencies on vector load data for the advantage of performing arithmetic operations on data stored in memory. Thus, it would have been obvious to one of ordinary skill in the art that vector arithmetic instructions can further process vector LUT data.).
The advantage of implementing LUTs is that they are frequently used in image and video processing for the advantage of accessing data faster. Thus, it would have been obvious to one of ordinary skill in the art at the time of the filing date to implement the LUT of Mimar into the vector coprocessor of Sprangle for the above advantage.
Sprangle and Mimar failed to teach loop control logic coupled to the decoder, memory interface, and the set of vector registers; wherein the table lookup unit is configured to execute a table lookup loop instruction that specifies a number of data values to be retrieved per lookup table to be accessed, the vector command using a set of loops specified by the loop control logic, based on the vector command cause the address generator to compute based on indices of the set of loops specified by the loop control logic.
However, Moyer combined with Sprangle and Mimar disclosed loop control logic coupled to the decoder, memory interface, and the set of vector registers; wherein the table lookup unit is configured to execute a table lookup loop instruction that specifies a number of data values to be retrieved per lookup table to be accessed, the vector command using a set of loops specified by the loop control logic, based on the vector command cause the address generator to compute based on indices of the set of loops specified by the loop control logic (Moyer: Figure 4, paragraphs 31-33)(Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3 elements 165, 210-220, paragraphs 13, 16-17, 54-55, 67-68, and 100)(Moyer disclosed load vector operations with load element counts, stride values, skip offsets, and skip counts to load multiple destination registers with non-adjacent data from memory. Mimar disclosed vector LUT operations (i.e. table lookup loop instruction) that include a vector command to load data from a set of lookup tables. The combination allows for the vector LUT operations of Mimar to perform the loading of multiple destination registers using the load element counts (i.e. number of data values to be retrieved), stride values, skip offsets, and skip counts of Moyer. The load element count divided by the number of LUTs specifies a load count per LUT. The instruction of Moyer causes the implementation of multiple loops to perform the instruction. This includes determining if the load count is met, determining if a current destination register is full and loading starts in a subsequent adjacent vector register, and determining if a skip count is met to change the stride value for the next data element loaded. The logic that implements these determining steps reads upon the loop control logic.).
The advantage of loading non-adjacent data elements to multiple destination registers is that a load operation can be performed more efficiently by a single instruction. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the vector load instruction operation methods of Moyer into the vector load operation of Sprangle for the above advantage.
As per claim 2:
Sprangle, Mimar, and Moyer disclosed the device of claim 1, wherein the vector command specifies whether the set of processing elements or the table lookup unit is to perform the operation on the first set of data to produce the second set of data (Mimar: Figure 8, paragraph 35)(Sprangle: Figures 1 and 3 elements 130, 165, 234, and 242-244, paragraphs 17, 19, 67-69, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. Decoded vector LUT instructions are performed by the LUTs of Mimar. Decoded vector load convert (& add) instructions are performed by the execution units of Sprangle.).
As per claim 3:
Sprangle, Mimar, and Moyer disclosed the device of claim 1, wherein the set of processing elements are configured to perform at least one of: bit interleaving, bit deinterleaving, conditional movement, conditional swap, sort, addition, logical AND, or logical OR on the first set of data (Mimar: Figure 4 elements 400 and 430, paragraphs 25 and 28-29)(Sprangle: Figures 1 and 3 elements 130, 165, 234, and 242-244, paragraphs 17, 19, 67-69, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. Decoded vector LUT instructions are performed by the LUTs of Mimar and allow for conditional writeback. Decoded vector load convert and add) instructions are performed by the execution units of Sprangle.).
As per claim 4:
Sprangle, Mimar, and Moyer disclosed the device of claim 1, wherein the table lookup unit is configured to retrieve a subset of the first set of data to produce the second set of data (Mimar: Figure 4 elements 400 and 430, paragraphs 25 and 28-29)(Sprangle: Figures 1 and 3 elements 130, 165, 234, and 242-244, paragraphs 17, 19, 67-69, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. Decoded vector LUT instructions are performed by the LUTs of Mimar and allow for conditional writeback.).
As per claim 6:
Sprangle, Mimar, and Moyer disclosed the device of claim 1, wherein the decoder is configured to cause the second set of data to be stored in the set of vector registers (Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers. The decoder indicates which vector register to store the data at.).
As per claim 7:
Sprangle, Mimar, and Moyer disclosed the device of claim 1 further comprising a write buffer coupled to the set of processing elements and the table lookup unit and configured to couple to the memory (Mimar: Figures 1-2 elements 100, 120, and 131, paragraphs 21-23)(Sprangle: Figure 1 elements 22, 31, 160, and 320, paragraphs 13 and 16)(Mimar disclosed vector LUT operations. The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. Official notice is given that store queues can be implemented in processors to temporarily store data prior to cache/memory writeback for the advantage of recording and allowing out-of-order execution of memory operations to improve execution performance. Thus, it would have been obvious to one of ordinary skill in the art to implement a store queue in the coprocessor of Sprangle.), wherein the decoder is configured to cause the second set of data to be stored in either the set of vector registers or the write buffer (Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers. The decoder indicates which vector register to store the data at.).
As per claim 8:
Sprangle, Mimar, and Moyer disclosed the device of claim 7, wherein the memory interface is configured to cause the second set of data stored in the write buffer to be stored in the memory (Sprangle: Figure 1 elements 160-165 and 310, paragraphs 16-17)(In view of the above official notice, writeback data temporarily stored in the store queue is written back to the cache/memory.).
As per claim 9:
Sprangle, Mimar, and Moyer disclosed the device of claim 1 further comprising a processor coupled to the decoder (Sprangle: Figure 1 elements 24 and 165, paragraphs 13 and 17).
As per claim 10:
Sprangle and Mimar disclosed a device comprising:
a processor (Sprangle: Figure 1 element 24, paragraph 13);
a vector coprocessor coupled to the processor (Sprangle: Figure 1 elements 22-24 and 31, paragraphs 13 and 16-17) that includes:
a set of address generators (Mimar: Figures 1-2 elements 130 and 240, paragraphs 21-22)(Sprangle: Figure 1 elements 160-165 and 310, paragraphs 16-17)(Mimar disclosed a set of address generators to generate effective addresses sent to each LUT. The combination adds a data memory that contains the set of LUTs and address generators within Sprangle.);
a decoder coupled to the processor (Sprangle: Figure 1 elements 22-24, 31, and 165, paragraphs 13 and 17);
a set of vector registers coupled to the decoder (Sprangle: Figure 1 element 150, paragraph 17);
a set of processing elements coupled to the set of vector registers in parallel (Sprangle: Figures 1 and 4-7 elements 130-150, paragraphs 19, 54-55, 69, 76-77, and 100-102)(The vector conversion elements and vector arithmetic elements read upon the processing elements.); and
a table lookup unit coupled to the set of vector registers in parallel with the set of processing elements, wherein the table lookup unit is configured to execute a table lookup loop instruction that specifies a vector command, a number of lookup tables in the memory to be accessed in parallel, and an offset for at least one lookup table to be accessed (Mimar: Figures 1-3 and 8 elements 100, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figure 1 elements 22 and 31, paragraphs 13 and 16)(Mimar disclosed vector LUT operations (i.e. table lookup loop instruction) that include a vector command to load data from a set of lookup tables. The LUT operation implicitly indicates loading from 32 LUTs and includes an index value (i.e. offset) for accessing a particular data element within each LUT. The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle.), wherein the decoder is configured to:
receive the command that specifies a first set of data in a memory, for which one or more addresses are computed by an address generator, of the set of address generators (Mimar: Figures 1-3 and 8 elements 100, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3 elements 165, 210-220, paragraphs 13, 16-17, 54-55, 67-68, and 100)(The combination implements the data memory that contains the set of LUTs and address generators of Mimar into the coprocessor of Sprangle. A fetched instruction is decoded by the coprocessor to determine if it’s a vector LUT operation. The vector LUT specifies data to be loaded in parallel from a set of LUTs. The vector LUT operation implicitly specifies corresponding address generators coupled to a given LUT, which generates an effective address sent to the LUT.); and
based on the command, cause either the set of processing elements or the table lookup unit to perform an operation on the first set of data to produce a second set of data (Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. The vector LUT operation writes data from the LUTs to a destination vector register. Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers. The combination allows for the vector LUT operation to additionally include a conversion and/or add operation to be performed prior to writing the LUT data to the vector registers. Additionally, official notice is given that vector arithmetic operations can have data dependencies on vector load data for the advantage of performing arithmetic operations on data stored in memory. Thus, it would have been obvious to one of ordinary skill in the art that vector arithmetic instructions can further process vector LUT data.).
The advantage of implementing LUTs is that they are frequently used in image and video processing for the advantage of accessing data faster. Thus, it would have been obvious to one of ordinary skill in the art at the time of the filing date to implement the LUT of Mimar into the vector coprocessor of Sprangle for the above advantage.
Sprangle and Mimar failed to teach loop control logic coupled to the decoder and a set of vector registers; wherein the table lookup unit is configured to execute a table lookup loop instruction that specifies a number of data values to be retrieved per lookup table to be accessed, addresses are computed using indices of a set of loops specified by the loop control logic.
However, Moyer combined with Sprangle and Mimar disclosed loop control logic coupled to the decoder and a set of vector registers; wherein the table lookup unit is configured to execute a table lookup loop instruction that specifies a number of data values to be retrieved per lookup table to be accessed, addresses are computed using indices of a set of loops specified by the loop control logic (Moyer: Figure 4, paragraphs 31-33)(Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3 elements 165, 210-220, paragraphs 13, 16-17, 54-55, 67-68, and 100)(Moyer disclosed load vector operations with load element counts, stride values, skip offsets, and skip counts to load multiple destination registers with non-adjacent data from memory. Mimar disclosed vector LUT operations (i.e. table lookup loop instruction) that include a vector command to load data from a set of lookup tables. The combination allows for the vector LUT operations of Mimar to perform the loading of multiple destination registers using the load element counts (i.e. number of data values to be retrieved), stride values, skip offsets, and skip counts of Moyer. The load element count divided by the number of LUTs specifies a load count per LUT. The instruction of Moyer causes the implementation of multiple loops to perform the instruction. This includes determining if the load count is met, determining if a current destination register is full and loading starts in a subsequent adjacent vector register, and determining if a skip count is met to change the stride value for the next data element loaded. The logic that implements these determining steps reads upon the loop control logic.).
The advantage of loading non-adjacent data elements to multiple destination registers is that a load operation can be performed more efficiently by a single instruction. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the vector load instruction operation methods of Moyer into the vector load operation of Sprangle for the above advantage.
As per claim 11:
Sprangle, Mimar, and Moyer disclosed the device of claim 10, wherein the decoder is configured to cause the first set of data to be copied from the memory to the set of vector registers (Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, and 310-320, paragraphs 16, 54, 67-69, and 74)(Vector load convert instructions cause data in memory to be copied to vector registers. In addition, Official notice is given that vector load operations can be performed in Sprangle for the advantage of reducing power and improving performance for load operations that don’t require a conversion. Thus, it would have been obvious to one of ordinary skill in the art to implement vector load operations in Sprangle.).
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 2. Therefore, claim 12 is rejected for the same reason(s) as claim 2.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 3. Therefore, claim 13 is rejected for the same reason(s) as claim 3.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 4. Therefore, claim 14 is rejected for the same reason(s) as claim 4.
As per claim 16:
Claim 16 essentially recites the same limitations of claim 6. Claim 16 additionally recites the following limitations:
after the operation is performed on the first set of data, cause the second set of data to be stored in the set of vector registers (Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers.).
As per claim 17:
Sprangle and Mimar disclosed a method comprising:
receiving a table lookup instruction that specifies a number of lookup tables in a memory to be accessed in parallel, an offset for at least one lookup table to be accessed (Mimar: Figures 1-3 and 8 elements 100, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figure 1 elements 22 and 31, paragraphs 13 and 16)(Mimar disclosed vector LUT operations (i.e. table lookup instruction) that include a vector command to load data from a set of lookup tables. The LUT operation implicitly indicates loading from 32 LUTs and includes an index value (i.e. offset) for accessing a particular data element within each LUT. The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle for use in executing vector LUT operations.), the table lookup instruction including a vector instruction that specifies:
a first set of data stored in a memory and a specified address generator, of a set of address generators, the specified address generator computing one or more addresses for the first set of data (Mimar: Figures 1-3 and 8 elements 100, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3 elements 165, 210-220, paragraphs 13, 16-17, 54-55, 67-68, and 100)(The combination implements the data memory that contains the set of LUTs and address generators of Mimar into the coprocessor of Sprangle. A fetched instruction is decoded by the coprocessor to determine if it’s a vector LUT operation, which specifies data to be loaded from LUTs in parallel. The vector LUT operation implicitly specifies corresponding address generators coupled to a given LUT, which generates an effective address sent to the LUT.); and
whether a set of processing elements or a table lookup unit coupled in parallel with the set of processing elements is to perform an operation on the first set of data (Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. The vector LUT operation writes data from the LUTs to a destination vector register. Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers. The combination allows for the vector LUT operation to additionally include a conversion and/or add operation to be performed prior to writing the LUT data to the vector registers. Decoded vector LUT instructions are performed by the LUTs of Mimar. Decoded vector load convert (& add) instructions are performed by the execution units of Sprangle. Additionally, official notice is given that vector arithmetic operations can have data dependencies on vector load data for the advantage of performing arithmetic operations on data stored in memory. Thus, it would have been obvious to one of ordinary skill in the art that vector arithmetic instructions can further process vector LUT data.); and
performing the operation on the first set of data to produce a second set of data (Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers. Vector LUT instructions are modified to also perform a conversion and/or add operation prior to storing the data in vector registers.).
The advantage of implementing LUTs is that they are frequently used in image and video processing for the advantage of accessing data faster. Thus, it would have been obvious to one of ordinary skill in the art at the time of the filing date to implement the LUT of Mimar into the vector coprocessor of Sprangle for the above advantage.
Sprangle and Mimar failed to teach a table lookup instruct that specifies a number of data values to be retrieved per lookup table to be accessed; the vector instruction including a loop instruction for processing the first set of data using a set of loops specified by loop control logic based on indices of the set of loops.
However, Moyer combined with Sprangle and Mimar disclosed a table lookup instruct that specifies a number of data values to be retrieved per lookup table to be accessed; the vector instruction including a loop instruction for processing the first set of data using a set of loops specified by loop control logic based on indices of the set of loops (Moyer: Figure 4, paragraphs 31-33)(Mimar: Figures 1-3 and 8 elements 100, 104, 120, 131, 200, 330, and 360, paragraphs 21-24 and 35)(Sprangle: Figures 1 and 3 elements 165, 210-220, paragraphs 13, 16-17, 54-55, 67-68, and 100)(Moyer disclosed load vector operations with load element counts, stride values, skip offsets, and skip counts to load multiple destination registers with non-adjacent data from memory. Mimar disclosed vector LUT operations (i.e. table lookup loop instruction) that include a vector command to load data from a set of lookup tables. The combination allows for the vector LUT operations of Mimar to perform the loading of multiple destination registers using the load element counts (i.e. number of data values to be retrieved), stride values, skip offsets, and skip counts of Moyer. The load element count divided by the number of LUTs specifies a load count per LUT. The instruction of Moyer causes the implementation of multiple loops to perform the instruction. This includes determining if the load count is met, determining if a current destination register is full and loading starts in a subsequent adjacent vector register, and determining if a skip count is met to change the stride value for the next data element loaded. The logic that implements these determining steps reads upon the loop control logic.).
The advantage of loading non-adjacent data elements to multiple destination registers is that a load operation can be performed more efficiently by a single instruction. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the vector load instruction operation methods of Moyer into the vector load operation of Sprangle for the above advantage.
As per claim 18:
Sprangle, Mimar, and Moyer disclosed the method of claim 17, wherein:
the vector instruction is a first vector instruction (Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, and 310-320, paragraphs 16, 54, 67-69, and 74)(Vector load convert instructions cause data in memory to be copied to vector registers. In addition, Official notice is given that vector load operations can be performed in Sprangle for the advantage of reducing power and improving performance for load operations that don’t require a conversion. Thus, it would have been obvious to one of ordinary skill in the art to implement vector load operations in Sprangle.); and
the method further comprises receiving a second vector instruction that specifies the operation (Sprangle: Figures 1 and 3-4 elements 160, 222, 232-236, 240-246, and 310-320, paragraphs 16, 54, 67-69, 74, and 100-102)(Vector load convert instructions perform a conversion operation prior to storing the data in vector registers. Vector load convert add operations perform an arithmetic operation prior to storing the data in vector registers. Additionally, official notice is given that vector arithmetic operations can have data dependencies on vector load data for the advantage of performing arithmetic operations on data stored in memory. Thus, it would have been obvious to one of ordinary skill in the art that vector arithmetic instructions can further process vector load data.).
As per claim 19:
Sprangle, Mimar, and Moyer disclosed the method of claim 17, wherein:
the vector instruction specifies to perform the operation using the set of processing elements (Sprangle: Figures 1 and 4-7 elements 130-150, paragraphs 19, 54-55, 69, 76-77, and 100-102)(The vector conversion elements and vector arithmetic elements read upon the processing elements.); and
the operation includes at least one of: bit interleaving, bit deinterleaving, conditional movement, conditional swap, sort, addition, logical AND, or logical OR (Mimar: Figure 4 elements 400 and 430, paragraphs 25 and 28-29)(Sprangle: Figures 1 and 3 elements 130, 165, 234, and 242-244, paragraphs 17, 19, 67-69, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. Decoded vector LUT instructions are performed by the LUTs of Mimar and allow for conditional writeback. Decoded vector load convert and add instructions are performed by the execution units of Sprangle.).
As per claim 20:
Sprangle, Mimar, and Moyer disclosed the method of claim 17, wherein:
the vector instruction specifies to perform the operation using the table lookup unit (Mimar: Figure 4 elements 400 and 430, paragraphs 25 and 28-29)(Sprangle: Figures 1 and 3 elements 130, 165, 234, and 242-244, paragraphs 17, 19, 67-69, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. Decoded vector LUT instructions are performed by the LUTs of Mimar and allow for conditional writeback.); and
the operation includes writing a subset of the first set of data to produce the second set of data (Mimar: Figure 4 elements 400 and 430, paragraphs 25 and 28-29)(Sprangle: Figures 1 and 3 elements 130, 165, 234, and 242-244, paragraphs 17, 19, 67-69, and 100-102)(The combination implements the vector LUTs of Mimar into the coprocessor of Sprangle. Decoded vector LUT instructions are performed by the LUTs of Mimar and allow for conditional writeback.).
Claims 5 and 15 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Sprangle et al. (U.S. 2009/0172349), in view of Mimar (U.S. 2013/0212353), in view of Moyer et al. (U.S. 2005/0055535), in view of Official Notice, further in view of Sato et al. (U.S. 2011/0274346).
As per claim 5:
Sprangle, Mimar, and Moyer disclosed the device of claim 1.
Sprangle, Mimar, and Moyer failed to teach further comprising a histogram unit coupled to the set of vector registers in parallel with the set of processing elements and the table lookup unit.
However, Sato combined with Sprangle, Mimar, and Moyer disclosed a histogram unit coupled to the set of vector registers in parallel with the set of processing elements and the table lookup unit (Sato: Figure 2 element 125, paragraphs 76, 87, 91, and 96) (Mimar: Figure 4 elements 400 and 430, paragraphs 25 and 28-29)(Sprangle: Figures 1 and 3 elements 130, 165, 234, and 242-244, paragraphs 17, 19, 67-69, and 100-102)(Sato disclosed a histogram unit for generating color histograms for image processing. The combination implements the histogram unit of Sato and the vector LUTs of Mimar into the coprocessor of Sprangle.).
The advantage of implementing a histogram unit is image data can be better analyzed. Thus, it would have been obvious to one of ordinary skill in the art at the time of the filing date to implement the histogram unit of Sato into the vector coprocessor of Sprangle for the above advantage.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 5. Therefore, claim 15 is rejected for the same reason(s) as claim 5.
Response to Arguments
The arguments presented by Applicant in the response, received on 8/19/2025 are not considered persuasive.
Applicant argues regarding claim 10:
“The combination of Sprangle, Mimar, and Moyer does not teach at least the claimed limitations, in which the vector command specifies a first set of data in the memory using a set of loops specified by loop control logic and an address generator of a set of address generators, and further that the decoder is configured to, based on the vector command, cause the address generator to compute address(es) for the first set of data based indices of the set of loops, as recited in claim 1.
Thus, Applicant respectfully submits that claim 1 and its dependent claims are allowable over the cited art. Each of independent claims 10 and 17 is amended substantially the same as claim 1 and is thus believed to be allowable for at least the same reasons as claim 1. Each of the remaining claims, which depends from either claim 10 or claim 17 is allowable at least by virtue of that dependency.”
This argument is found to be persuasive for the following reason. Mimar disclosed a set of LUT tables and corresponding address generators, which generates effective addresses to access data within the LUTs. The combination implements these elements into Sprangle. The vector LUT operation of Mimar implicitly indicates an address generator to be used for a corresponding LUT table that is to be accessed. The combination with Moyer allows for the operation to be repeatedly performed based on a total number of data elements to be loaded. Thus, reading upon the newly claimed limitations.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183