DETAILED ACTION
Claims 1, 2, 4-12 and 14-20 are presented for examination.
Claims 1, 4, 11, 13, and 14 have been amended.
This office action is in response to the amendment submitted on 12-FEB-2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been received for Application No. KR10-2021-0163134, filed on 11/24/2021.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action, see 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Response to Arguments - Claim Interpretation
The applicant’s arguments regarding interpretating the claim limitation “controller” under 112(f) is persuasive and consequently the interpretation under 112(f) is withdrawn.
Response to Arguments – 35 USC 103
On pgs. 7-9 the applicant argues the amended claim 1 overcomes the rejection under 35 USC 103. The applicant argues: In Kajitani, the peripheral emulators 102b, 104b and the plant simulators 106, 108 are part of the same simulation (V-PILS). Therefore, even if Albrecht is somehow combined with Kajitani, the proposed combination would not teach or suggest at least a "signal generator" that generates "an electrical signal based on a virtual output of a virtual ECU of the one or more virtual ECUs of the SILS" (i.e., an element in one type of simulation), and transmits "the electrical signal to an ECU of the one or more ECUs of the HILS" (i.e., a different element in a different type of simulation), as recited in independent claim 1.
The examiner respectfully disagrees. Specifically, Fig. 1 of Albrecht shows the virtual ECUs sharing the same bus. The vECU communicate and generate messages that simulate the real ECU connected to the HIL system. Fig. 3 shows the messages between the various ECUs virtual and physical (HIL). Additionally, Albrecht discloses Pg. 2, “Applications on the upper OSI layer include signal panels and signal generators, for example…Therefore, a state-of-the-art test environment offers a suitable panel editor as a standard feature to create customized panels with user control and to display instruments or standard panels (Figure 2), which are configured from database information.”
The combination of Kajitani and Albercht does teach the newly amended limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-12 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kajitani et al. (US20140025365A1) in view of Albrecht et al. (Quick Paths to a Comprehensive Remaining Bus Simulation).
Regarding claim 1, Kajitani teaches a simulation device comprising: a storage configured to store a software in the loop simulation (SILS) software comprising one or more virtual ECUs ([0011] “The configuration includes multiple ECU emulators, multiple plant simulators, and a global scheduler 110 configured to schedule overall operations," and [0055] “The hard disk drive 416 further stores programs such as processor emulators, a peripheral scheduler, peripheral emulators, clock converters, and plant simulators, which will be described later. These are loaded into the main memory, assigned to the individual CPUs CPU1 to CPUn as individual threads or processes, and thereby executed. Thus, the computer system shown in FIG. 4”).
a controller configured to control at least one of the HILS module or the SILS software to perform a simulation on a network comprising at least one of the ECU or the virtual ECU (Fig. 1, and [0018] "function of a network such as the CAN (controller area network) for mutually connecting the processors requires communications among peripherals").
a signal generator configured to generate an electrical signal based on a virtual output of a virtual ECU, of the one or more virtual ECUs, and transmit the electrical signal to an ECU, ([0016] "The peripheral emulator transmits a pulse signal to the plant simulator").
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However, Kajitani is not relied on for:
a hardware in the loop simulation (HILS) module comprising one or more electronic control units (ECUs)
to an ECU, of the one or more ECUs of the HILS
Albrecht teaches a hardware in the loop simulation (HILS) module comprising one or more electronic control units (ECUs) (Fig. 1 shows physical nodes for HILS)
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to an ECU, of the one or more ECUs of the HILS (Fig. 1 shows the virtual ECUs sharing the same bus. The vECU communicate and generate messages that simulate the real ECU connected to the HIL system. Fig. 3 shows the messages between the various ECUs virtual and physical (HIL) and Pg. 2, “Applications on the upper OSI layer include signal panels and signal generators, for example. They are indispensable aids in simulating user activities and dynamic processes. They contain virtual switches, buttons and display instruments that can be used to conveniently input spontaneous operating actions on the computer screen such as activation of a turn signal, windshield wiper or window lift. They also show user system parameters and enable specific modification of signals and variables during the test runs. Therefore, a state-of-the-art test environment offers a suitable panel editor as a standard feature to create customized panels with user control and to display instruments or standard panels (Figure 2), which are configured from database information. In automatically generating simulations and panels or in making signal assignments smoothly, the following is true: The more detailed the relevant networks, messages and attributes are described in the associated database, the more precise are the models created by the generators. Preconfigured panels benefit from all available information, such as signal descriptions, specified value ranges or symbolic identifiers.”)
Kajitani, and Albrecht are analogous art because they are from the same field of endeavor in automotive ECU simulation. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, to combine Kajitani, and Albrecht to replace Kajitani’s simulated HIL and incorporate real physical ECU nodes on a HIL in the simulation thereby shortcutting the simulation cycles and “ensure[s] that a functional environment is available to the ECU, without which comprehensive tests could hardly be realized. “achieving(e) a reasonable accuracy and/or unambiguousness which is required for construction site tasks” (Albercht, Abstract).
Regarding Claim 2, Kajitani in view of Albrecht teaches the device of claim 1. Kajitani further teaches further comprising a communication interface configured to perform communication between the HILS module and the SILS software (Fig. 1, and [0011] "The configuration includes multiple ECU emulators, multiple plant simulators, and a global scheduler 110 configured to schedule overall operations. It should be understood that FIG. 1 illustrates two ECU emulators 102, 104 and two plant simulators 106, 108." Albercht also teaches this limitation as displayed in their Fig. 1, above).
Regarding Claim 4, Kajitani in view of Albrecht teaches the device of claim 1. Kajitani further teaches wherein the controller is further configured to: configure a network in which at least one of the ECUs is replaced with a virtual ECU, of the one or more virtual ECUs, using the communication interface ([0064] "a predetermined program scans source code in SystemC of the peripheral emulators, and thereby stores a table including peripheral-emulator-based processing break times in a shared memory or the like. This table is designed to allow the peripheral scheduler 502 to refer to the table. This makes it possible for the peripheral scheduler 502 to calculate the next processing break by using addition based on entries of the table, and to select, as the next target time, a processing break closest to the time of currently performed simulation" The code written in SystemC configures the network and enables/disables the available ECUs)
control both the HILS module and the SILS software to perform a simulation on the configured network ([0011] "FIG. 1 shows a typical V-PILS configuration according to a conventional concept. The configuration includes multiple ECU emulators, multiple plant simulators, and a global scheduler 110 configured to schedule overall operations").
Regarding Claim 5, Kajitani in view of Albrecht teaches the device of claim 4. Kajitani further teaches wherein the controller is further configured to:
control the HILS module to turn on power of an ECU included in the configured network, among the one or more ECUs ([0029] " in order to enable control by the peripheral scheduler, there are also prepared completion flags to which each peripheral emulator, each processor emulator, and each plant simulator correspond, respectively," and [0032] "After the preparations described above, the peripheral scheduler clears (sets to OFF) the completion flags of all the peripheral emulators to thereby start parallel operations. Then, based on the information on the processing breaks of the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of the processor emulators and the plant simulators up until a time point of the time T." Fig. 2 of Albercht covers this limitation as well).
control the SILS software to turn on a switch of a virtual ECU included in the configured network, among the one or more virtual ECUs ([0029] " in order to enable control by the peripheral scheduler, there are also prepared completion flags to which each peripheral emulator, each processor emulator, and each plant simulator correspond, respectively," and [0032] "After the preparations described above, the peripheral scheduler clears (sets to OFF) the completion flags of all the peripheral emulators to thereby start parallel operations. Then, based on the information on the processing breaks of the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of the processor emulators and the plant simulators up until a time point of the time T." Fig. 2 of Albercht covers this limitation as well).
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Regarding Claim 6, Kajitani in view of Albrecht teaches the device of claim 1. Albrecht further teaches, further comprising an inputter configured to receive a user input wherein the controller is further configured to configure a network based on the user input received through the inputter (See Fig. 2 and Pg. 2, Configuring not programming, “Project participants simply add communication databases to the simulation setup by drag and drop operation”).
Regarding Claim 7, Kajitani in view of Albrecht teaches the device of claim 6. Kajitani further teaches, wherein the controller is further configured to, when an input to perform a test on input/output electrical signals of a network is received, control the HILS module to perform a simulation on a network comprising only the one or more ECUs ([0064] "the peripheral scheduler 502 performs processing of selecting a peripheral emulator as a synchronization source in the following manner. Specifically, for example, a predetermined program scans source code in SystemC of the peripheral emulators, and thereby stores a table including peripheral-emulator-based processing break times in a shared memory or the like." The SystemC code provides the functionality to selectively activate only the HIL components).
Regarding Claim 8, Kajitani in view of Albrecht teaches the device of claim 6. Kajitani further teaches wherein the controller is further configured to, when an input to perform a test on control logics of a network, control the SILS software to perform a simulation on a network comprising only the one or more virtual ECUs ([0064] "the peripheral scheduler 502 performs processing of selecting a peripheral emulator as a synchronization source in the following manner. Specifically, for example, a predetermined program scans source code in SystemC of the peripheral emulators, and thereby stores a table including peripheral-emulator-based processing break times in a shared memory or the like." The SystemC code provides the functionality to selectively activate only the SIL components).
Regarding Claim 9, Kajitani in view of Albrecht teaches the device of claim 1. Albercht wherein the controller is further configured to:
transmit and receive data to and from the HILS module, based on an electrical signal (Fig. 2 show the user modifying signal values).
transmit and receive data to and from the SILS software, based on a virtual signal (Fig. 2 show the user modifying signal values).
determine a result of the simulation based on at least one of the electrical signal received from the HILS module or the virtual signal received from the SILS software (Fig. 4 show the results based on the configured signals).
Regarding Claim 10, Kajitani in view of Albrecht teaches the device of claim 9. Albercht comprising a display, wherein the controller is further configured to control the display to display the result of the simulation (Fig. 4 shows the UI and the simulation results).
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Claims 11-12 and 14-20 are method claims that recite limitations similar to claim 1-2 and 4-10 respectively and are rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Palander et al. (US20200244558A1): Discloses interconnected HIL and SIL system integrated over a wireless network.
Wunner et al. (Development and Testing of Automotive Ethernet-Networks together in one Tool - OMNeT++): Discloses RestBus simulation integrating HIL and SIL.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.E.D./Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199