DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/01/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramaraju et al. [US 2006/0250880 A1].
Regarding Claim 8, Ramaraju teaches “A memory device comprising: a first plurality of bitcells coupled via a first local bitline (LBL);” as “As illustrated in FIG. 1, the read bit lines, write bit lines, and column select lines run in the column direction, and the write word lines and read word lines run in the row direction. ” [¶0013] (Fig. 1 shows a memory device with cells attached to read and write bit lines.)
“a second plurality of bitcells coupled via a second LBL, each bitcell of the first plurality of bitcells and the second plurality of bitcells comprising a single read (1R) port and a single write (1W) port; and” as “the word line signal with the column address signal to control the memory cell access transistors, both the write port and the read port of the memory cell can be separately optimized for both write margin and cell stability in a dual-port memory that allows a portion of a row that is less than a cache line to be accessed.” [¶0011] (There is a separate write port to write data to the memory)
“read merge circuitry coupled to the first LBL and the second LBL, the read merge circuitry to perform operations comprising: pre-charging a node of the first LBL to a first supply voltage;” as “During a read operation to memory cell 20, the bit line RBL0 is precharged to a logic high voltage equal to the voltage provided at power supply voltage terminal VDD. ” [¶0017]
“pre-discharging a node of the second LBL to a second supply voltage;” as “if storage node N2 is storing a logic high voltage, transistor 56 will be conductive, and the voltage on bit line RBLO will be pulled to the voltage of power supply voltage terminal VSS.” [¶0017]
“activating an equalization path between the first LBL and the second LBL, the activating of the equalization path causing charge sharing between the node of the first LBL and the node of the second LBL;” as “ Column logic 16 includes, for example, column decoders, sense amplifiers, bit line equalization and precharge circuits, and buffer circuits.” [¶0013]
“detecting a read wordline (RWL) for a selected bitcell of the first plurality of bitcells or the second plurality of bitcells; and” as “N-channel transistor 58 has a source coupled to the drain of transistor 56, a gate for receiving read word line signal RWL0, and a drain coupled to read bit line RBL0.” [¶0015] (Read wordline signals are for receiving read bits)
“performing a read operation of the selected bitcell based on the detecting of the RWL.” as “The read word lines RWL0-RWLN are coupled to row decoder 14.” [¶0013] (Row decoder receives the address to read data from the memory device.)
Regarding Claim 18, Ramaraju teaches “A memory device comprising: a first plurality of bitcells coupled via a first local bitline (LBL);” as “As illustrated in FIG. 1, the read bit lines, write bit lines, and column select lines run in the column direction, and the write word lines and read word lines run in the row direction. ” [¶0013] (Fig. 1 shows a memory device with cells attached to read and write bit lines.)
“a second plurality of bitcells coupled via a second LBL, each bitcell of the first plurality of bitcells and the second plurality of bitcells comprising a single read (1R) port and a single write (1W) port; and” as “the word line signal with the column address signal to control the memory cell access transistors, both the write port and the read port of the memory cell can be separately optimized for both write margin and cell stability in a dual-port memory that allows a portion of a row that is less than a cache line to be accessed.” [¶0011] (There is a separate write port to write data to the memory)
“read merge circuitry coupled to the first LBL and the second LBL, the read merge circuitry comprising: a pre-charge device coupled to the first LBL, the pre-charge device configured to pre-charge a node of the first LBL to a first supply voltage during a pre-charging phase of the read merge circuitry;” as “During a read operation to memory cell 20, the bit line RBL0 is precharged to a logic high voltage equal to the voltage provided at power supply voltage terminal VDD. ” [¶0017]
“a pre-discharge device coupled to the second LBL, the pre-discharge device configured to pre-discharge a node of the second LBL to a second supply voltage during the pre-charging phase; and” as “if storage node N2 is storing a logic high voltage, transistor 56 will be conductive, and the voltage on bit line RBLO will be pulled to the voltage of power supply voltage terminal VSS.” [¶0017]
“an equalization path configured between the first LBL and the second LBL,” as “ Column logic 16 includes, for example, column decoders, sense amplifiers, bit line equalization and precharge circuits, and buffer circuits.” [¶0013]
“the equalization path causing prior to a read operation, charge sharing between the node of the first LBL and the node of the second LBL and equalizing a voltage on the first LBL and a voltage on the second LBL to a voltage level between the first supply voltage and the second supply voltage.” as “N-channel transistor 58 has a source coupled to the drain of transistor 56, a gate for receiving read word line signal RWL0, and a drain coupled to read bit line RBL0.” [¶0015] (Read wordline signals are for receiving read bits)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju et al. [US 2006/0250880 A1] in view of Wong [US 2003/0002329 A1].
Claim 1 is rejected over Ramaraju and Wong.
Ramaraju teaches “A memory device comprising: at least one bitcell coupled to a local bitline, the at least one bitcell comprising:” as “As illustrated in FIG. 1, the read bit lines, write bit lines, and column select lines run in the column direction, and the write word lines and read word lines run in the row direction. ” [¶0013] (Fig. 1 shows a memory device with cells attached to read and write bit lines.)
“a first set of a plurality of transistor devices configured to form a single write (1W) port, the 1W port to receive digital data;” as “the word line signal with the column address signal to control the memory cell access transistors, both the write port and the read port of the memory cell can be separately optimized for both write margin and cell stability in a dual-port memory that allows a portion of a row that is less than a cache line to be accessed.” [¶0011] (There is a separate write port to write data to the memory)
“a third set of the plurality of transistor devices configured to form a single read (1R) port, the 1R port to access the digital data stored at the inverter pair and output the digital data on the local bitline,” as “the word line signal with the column address signal to control the memory cell access transistors, both the write port and the read port of the memory cell can be separately optimized for both write margin and cell stability in a dual-port memory that allows a portion of a row that is less than a cache line to be accessed.” [¶0011] (A separate read port is recited)
Ramaraju does not explicitly teach a second set of the plurality of transistor devices configured as an inverter pair, the inverter pair to store the digital data; and
and the plurality of transistor devices consisting of the first, second and thirds sets that together consist of an equal number of P-channel transistor devices and N- channel transistor devices.
However, Wong teaches “a second set of the plurality of transistor devices configured as an inverter pair, the inverter pair to store the digital data; and” as “Specifically, the memory cell includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters.” [¶0003]
“and the plurality of transistor devices consisting of the first, second and thirds sets that together consist of an equal number of P-channel transistor devices and N- channel transistor devices.” as [Fig. 5(a)] (Fig. 5(a) shows write port made of NFET pass gates NL and NR, which are 2 N-channels, cross-coupled inverter pair made of Conventional CMOS latch, 2 P-channel + 2 N-channel and read port made of PFET pass gates PL and PR, which are 2 P-Channels. In total there are 4 P-channel + 4 N-channel)
Ramaraju and Wong are analogous arts because they teach semiconductor memory implementation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ramaraju and Wong before him/her, to modify the teachings of Ramaraju to include the teachings of Wong with the motivation of changing the internal cell node voltage at a faster rate and thereby quickening the write time to the cell. With this embodiment, the particular bias setting of V.sub.L (depending on the overall voltage budget) has its own advantages. [Wong, ¶0026]
Claim 2 is rejected over Ramaraju and Wong.
Ramaraju teaches “wherein the plurality of transistor devices consists of four N-channel metal-oxide semiconductor (NMOS) transistors and four P-channel metal-oxide semiconductor (PMOS) transistors.” as “ In the illustrated embodiment, storage cell 70 is a cross-coupled pair of inverters. One inverter of the cross-coupled pair of inverters 70 includes a P-channel transistor 72 and an N-channel transistor 74. The other inverter includes P-channel transistor 76 and N-channel transistor 78.” [¶0020]
Claim 3 is rejected over Ramaraju and Wong.
Ramaraju teaches “wherein the first set of the plurality of transistor devices consists of a first NMOS transistor of the four NMOS transistors and a first PMOS transistor of the four PMOS transistors.” as [Fig. 4] (Fig. 4 shows NMOS and PMOS transistors building the memory cell.)
Claim 6 is rejected over Ramaraju and Wong.
Ramaraju teaches “wherein the third set of the plurality of transistor devices consists of a second NMOS transistor of the four NMOS transistors and a second PMOS transistor of the four PMOS transistors.” as [Fig. 4] (Fig. 4 shows NMOS and PMOS transistors building the memory cell.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju et al. [US 2006/0250880 A1] in view of Wong [US 2003/0002329 A1] and in further view of Liaw [US 2014/0063919 A1].
Claim 4 is rejected over Ramaraju, Wong and Liaw.
The combination of Ramaraju and Wong does not explicitly teach wherein the 1W port is formed by drain terminals of the first NMOS transistor and the first PMOS transistor.
However, Liaw teaches “wherein the 1W port is formed by drain terminals of the first NMOS transistor and the first PMOS transistor.” as “The gates of the PMOS transistor 204 and the NMOS transistor 208 are also coupled together at the node 220, and their drains coupled at the node 218” [¶0008]
Ramaraju, Wong and Liaw are analogous arts because they teach semiconductor memory implementation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ramaraju, Wong and Liaw before him/her, to modify the teachings of combination of Ramaraju and Wong to include the teachings of Liaw with the motivation of to a method for providing a multiple-port static-random-access-memory (SRAM) cell structure with balanced read and write operation speeds and an improved noise margin. [Liaw, ¶0002]
Claim 5 is rejected over Ramaraju, Wong and Liaw.
Ramaraju teaches “wherein a gate terminal of the first NMOS transistor forms a write-wordline (wwl) terminal and a gate terminal of the first PMOS transistor forms a write-wordline-bar (wwl b) terminal, the wwl terminal and the wwlb terminal associated with writing the digital data into the inverter pair.” as “each of the memory cells is coupled to one of a plurality of write word lines labeled "WWLBO" to "WWLBN", to one pair of a plurality of pairs of write bit lines labeled "WBL0/WBLB0" to "WBLN/WBLBN",” [¶0012]
Claim 7 is rejected over Ramaraju, Wong and Liaw.
The combination of Ramaraju and Wong does not explicitly teach wherein the IR port is formed by drain terminals of the second NMOS transistor and the second PMOS transistor.
However, Liaw teaches “wherein the IR port is formed by drain terminals of the second NMOS transistor and the second PMOS transistor.” as “The gates of the PMOS transistor 204 and the NMOS transistor 208 are also coupled together at the node 220, and their drains coupled at the node 218” [¶0008]
Ramaraju, Wong and Liaw are analogous arts because they teach semiconductor memory implementation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ramaraju, Wong and Liaw before him/her, to modify the teachings of combination of Ramaraju and Wong to include the teachings of Liaw with the motivation of to a method for providing a multiple-port static-random-access-memory (SRAM) cell structure with balanced read and write operation speeds and an improved noise margin. [Liaw, ¶0002]
Claim(s) 9-12 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju et al. [US 2006/0250880 A1] in view of Behrends et al. [US 2013/0235681 A1].
Claim 9 is rejected over Ramaraju and Behrends.
Ramaraju does not explicitly teach wherein the read merge circuitry further comprises: a P-channel metal-oxide semiconductor (PMOS) transistor configured as a pre-charge device.
However, Behrends teaches “wherein the read merge circuitry further comprises: a P-channel metal-oxide semiconductor (PMOS) transistor configured as a pre-charge device.” as “SRAM precharge and write circuit 100 includes a pair of precharge P-channel field effect transistors (PFETs) 102, 104 respectively coupled between a voltage supply rail VD and respective true and complement bit lines BLT, BLC.” [¶0019]
Ramaraju and Behrends are analogous arts because they teach semiconductor memory implementation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ramaraju and Behrends before him/her, to modify the teachings of Ramaraju to include the teachings of Behrends with the motivation of providing improvements to both the wordline signal and the precharge signal. [Behrends, ¶0017]
Claim 10 is rejected over Ramaraju and Behrends.
Ramaraju does not explicitly teach wherein the pre-charge device is configured to perform the pre-charging of the node of the first LBL to the first supply voltage during a pre-charging phase of the read merge circuitry.
However, Behrends teaches “wherein the pre-charge device is configured to perform the pre-charging of the node of the first LBL to the first supply voltage during a pre-charging phase of the read merge circuitry.” as “The respective write data signals WC, WT are respectively applied to a gate of the NFETs 106, 108. NFETs 106, 108 are coupled between the voltage supply rail VD and the respective true and complement bit lines BLT, BLC.” [¶0021]
Claim 11 is rejected over Ramaraju and Behrends.
Ramaraju does not explicitly teach wherein the read merge circuitry further comprises: a first N-channel metal-oxide semiconductor (NMOS) transistor configured as a pre-discharge device.
However, Behrends teaches “wherein the read merge circuitry further comprises: a first N-channel metal-oxide semiconductor (NMOS) transistor configured as a pre-discharge device.” as “SRAM precharge and write circuit 100 includes an NFET 110 receiving a gate input of the write signal WR and respectively connected between a ground potential rail and a second pair of N-channel field effect transistors (NFETs) 112, 114. ” [¶0020]
Claim 12 is rejected over Ramaraju and Behrends.
Ramaraju does not explicitly teach wherein the pre-discharge device is configured to perform the pre-discharging of the node of the second LBL to the second supply voltage during the pre-charging phase of the read merge circuitry.
However, Behrends teaches “wherein the pre-discharge device is configured to perform the pre-discharging of the node of the second LBL to the second supply voltage during the pre-charging phase of the read merge circuitry.” as “SRAM precharge and write circuit 100 includes a pair of precharge P-channel field effect transistors (PFETs) 102, 104 respectively coupled between a voltage supply rail VD and respective true and complement bit lines BLT, BLC. The precharge signal PCHG_B is applied to a gate of each precharge PFETs 102, 104 for precharging the respective true and complement bit lines BLT, BLC.” [¶0019]
Claim 19 is rejected over Ramaraju and Behrends.
Ramaraju does not explicitly teach wherein the pre-charge device is a P- channel metal-oxide semiconductor (PMOS) transistor, and
wherein the pre- discharge device is an N-channel metal-oxide semiconductor (NMOS) transistor.
However, Behrends teaches “wherein the pre-charge device is a P- channel metal-oxide semiconductor (PMOS) transistor, and” as “SRAM precharge and write circuit 100 includes a pair of precharge P-channel field effect transistors (PFETs) 102, 104 respectively coupled between a voltage supply rail VD and respective true and complement bit lines BLT, BLC.” [¶0019]
“wherein the pre- discharge device is an N-channel metal-oxide semiconductor (NMOS) transistor.” as “SRAM precharge and write circuit 100 includes an NFET 110 receiving a gate input of the write signal WR and respectively connected between a ground potential rail and a second pair of N-channel field effect transistors (NFETs) 112, 114. ” [¶0020]
Ramaraju and Behrends are analogous arts because they teach semiconductor memory implementation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ramaraju and Behrends before him/her, to modify the teachings of Ramaraju to include the teachings of Behrends with the motivation of providing improvements to both the wordline signal and the precharge signal. [Behrends, ¶0017]
Claim(s) 17 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramaraju et al. [US 2006/0250880 A1] in view of Naffziger et al. [US 5815432 A].
Claim 17 is rejected over Ramaraju and Naffziger.
Ramaraju does not explicitly teach a feed-forward multiplexing inverter coupled to the first LBL and the second LBL, the feed-forward multiplexing inverter comprising a global bitline (GBL) configured to receive digital data from one the first plurality of bitcells via the first LBL or from one of the second plurality of bitcells via the second LBL.
However, Naffziger teaches “a feed-forward multiplexing inverter coupled to the first LBL and the second LBL, the feed-forward multiplexing inverter comprising a global bitline (GBL) configured to receive digital data from one the first plurality of bitcells via the first LBL or from one of the second plurality of bitcells via the second LBL.” as “The supply voltage of storage element 10 is preferably substantially less than 2 volts, and bitline 96 is allowed to slew down from the supply voltage to a trip point of a sensor, such as an inverter or a multiplexer such as mux 98, shown in FIG. 5, may detect the bit value. ” [Col 6, lines 33-37]
Ramaraju and Naffziger are analogous arts because they teach semiconductor memory implementation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ramaraju and Naffziger before him/her, to modify the teachings of Ramaraju to include the teachings of Naffziger with the motivation of the use of sense amps to improve the speed of the system increases the size. Reducing this increased size by minimizing the number of sense amps slows the system again, offsetting the speed benefit of sense amps. [Naffziger, Col 4, lines 66-67]
Claim 22 is rejected over Ramaraju and Naffziger under the same rationale of rejection of claim 17.
Allowable Subject Matter
Claim 13-16 and 20-21 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 requires a second equalizing device coupled to the node of the second LBL, wherein the first equalizing device and the second equalizing device are further coupled to each other to form the equalization path. The prior arts of record appear to teach column decoders, sense amplifiers, bit line equalization and pre-charge circuits, and buffer circuits. However, the prior arts do not appear to teach or fairly suggest two equalizing devices coupled to each other to form the equalization path. Based on this rationale, claim 13 and its dependent claims 14-16 are objected.
Under the same rationale, claims 20 and its dependent claim 21 are also objected.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MASUD K KHAN/Primary Examiner, Art Unit 2132
Prosecution Insights