DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed May 21, 2026 has been entered. Claims 1-20 remain pending in the application.
Response to Arguments
Applicant's arguments filed May 21, 2026 have been fully considered but they are not persuasive. Applicant argues, see pages 9-11, that the previously presented rejections under 35 U.S.C. § 103 are invalid because they require five references and used impermissible hindsight reasoning. Examiner respectfully disagrees.
In response to applicant's argument that the examiner has combined an excessive number of references, reliance on a large number of references in a rejection does not, without more, weigh against the obviousness of the claimed invention. See In re Gorman, 933 F.2d 982, 18 USPQ2d 1885 (Fed. Cir. 1991).
In this case, applicant has not provided any specific issues with the rejections provided by the examiner, merely restating the number of references applied in the rejections, and therefore applicant’s argument does not weigh against the obviousness of the claimed invention.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In this case, applicant has stated that the rejections provided by the examiner lack sufficient motivation to combine in the prior art, however, the applicant has not provided any reasoning to rebut the rationales provided in the Non-Final Office Action mailed January 27, 2026, hereafter referred to as the Non-Final Office Action.
As recited by the Non-Final Office Action, the reference Wagh et al. (Patent Number US 9,716,477 B2), hereafter referred to as Wagh, was used to include an envelope tracking system to the power amplifier of the primary reference An et al. (Patent Publication Number CN 104,124,924 A), hereafter referred to as An, for the purpose of improving the linearity of the power amplifier of An. As the applicant has not provided any specific reasoning to rebut this motivation to combine, the combination remains valid.
As recited by the Non-Final Office Action, the reference Kwon et al. (Patent Publication Number DE 10 2015/108468 A1), hereafter referred to as Kwon, was used to provide copper pillars as a connection medium between elements of the circuit of An, for the purpose of dissipating excess heat in the power amplifier of An. As the applicant has not provided any specific reasoning to rebut this motivation to combine, the combination remains valid.
As recited by the Non-Final Office Action, the reference Then et al. (Patent Publication Number US 2020/0235216 A1), hereafter referred to as Then, was used to provide implementing transistors of An as Gallium Nitride transistors, for the purpose of further improving the linearity of the power amplifier of An. As the applicant has not provided any specific reasoning to rebut this motivation to combine, the combination remains valid.
As recited by the Non-Final Office Action, the reference Birner et al. (Patent Publication Number US 2017/0373138 A1), hereafter referred to as Birner, was used to provide a through-silicon via to couple two transistors in the circuit of An, for the purpose of providing a well-known connection medium to connect two transistors. As the applicant has not provided any specific reasoning to rebut this motivation to combine, the combination remains valid.
Furthermore, the newly amended features of a gate connected bias node and input matching circuit are additionally present in references Then (see Fig. 4A and Paragraph 34) and Kwon (see Fig. 1B), respectively, so therefore the amendments provided by the applicant do not overcome the prior art rejections.
Therefore, all of applicant’s arguments are unconvincing, and the rejections of claims 1-20 are maintained.
Claim Objections
Claim 20 is objected to because of the following informality: On claim 20, lines 23-24, replace “the at least one Gallium Nitride field-effect transistor” with “the at least one Gallium Nitride field-effect-transistor”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10, and 20 recite the limitation "at least one Gallium Nitride field-effect-transistor" in lines 30, 31-32, and 31, respectively. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the at least one Gallium Nitride field-effect-transistor” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 2-9 and 11-19 are likewise rejected under this logic by virtue of their dependencies on claims 1 and 10, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Wagh, Kwon, Then, and Birner.
Regarding claim 1, An discloses:
A power amplifier system (An, Fig. 3) comprising: a power amplifier (Fig. 3) that amplifies the radio frequency signal (Paragraph 24, lines 1-3) with at least one complementary metal-oxide semiconductor transistor (Fig. 3, see transistors M1), the adaptation circuit (Fig. 3, M2 and M1a) adapts the supply voltage to provide operating power to the power amplifier (Fig. 3, see connection between supply VDD and amplifying transistors M1 via M2 and M1a), the adaptation circuit including at least one field-effect-transistor (Fig. 3, M2) that generates the operating power in response to an increased swing of the supply voltage (Fig. 3, see connection between VDD amplifying transistors M1 via transistors M2); at least one linearizing circuit (Fig. 3, M1a) connected to a drain of the at least one field-effect transistor (Fig. 3, see connection between M1a and drain of M2), the at least one linearizing circuit configured to linearize an operation of the at least one field-effect-transistor (Paragraph 31, lines 1-3), but fails to disclose an envelope tracker that generates a supply voltage that changes in relation to an envelope of a radio frequency signal; and an adaptation circuit connected to the power amplifier with a plurality of copper pillars, [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor], the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is on a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via; a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor; and an impedance matching circuit that blocks a direct current signal with an input connected to a radio frequency signal and an output connected to the gate of at least one Gallium Nitride field-effect-transistor.
However, Wagh teaches an envelope tracker (Wagh, Fig. 1, 180) that generates a supply voltage that changes in relation to an envelope of a radio frequency signal (Fig. 1, ETDR, see also Col. 11, lines 44-51); but fails to teach and an adaptation circuit connected to the power amplifier with a plurality of copper pillars, [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor], the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is on a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via; a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor; and an impedance matching circuit that blocks a direct current signal with an input connected to a radio frequency signal and an output connected to the gate of at least one Gallium Nitride field-effect-transistor.
However, Kwon teaches teach and an adaptation circuit connected to the power amplifier with a plurality of copper pillars (Kwon, Fig. 1B, see connection between adaptation circuit 130 and the power amplifier transistor in substrate 200 via copper pillars 50); and an impedance matching circuit (Fig. 1B, 111) that blocks a direct current signal with an input connected to a radio frequency signal (Fig. 1B, see connection between 111 and RF input 102) and an output connected to the gate of at least one Gallium Nitride field-effect-transistor (Fig. 1B, see connection between 111 and input of 110), but fails to teach [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor], the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is on a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via.
However, Then teaches [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor] (Then, Paragraph 37, lines 8-11 [see the usage of a Gallium Nitride transistor in a power amplifier in Fig. 4B]), the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer (Paragraph 17, lines 3-5) positioned on a silicon layer (Paragraph 17, lines 3-6) connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor (Paragraph 17, lines 6-8) that is on a die with the at least one complementary metal-oxide semiconductor transistor (Paragraph 71, lines 1-7); a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor (Paragraph 34, lines 1-6), but fails to teach the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via.
However, Birner teaches the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via (Birner, Paragraph 57, lines 1-6).
An, Wagh, Kwon, Then, and Birner are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified An to incorporate the teachings of Wagh, Kwon, Then, and Birner to include an envelope tracking system in the amplifier of An, which would have the effect of improving linearity of the power amplifier of An (Wagh, Col. 1, lines 53-57), to include the copper pillars and input matching circuit of Kwon between the adaptation circuit and power amplifier of An, which would have the effect of dissipating excess heat (Kwon, Page 5, Paragraph 2, lines 2-7), to use the Gallium Nitride transistors and bias circuit of Then to implement the transistors of An, which would have the effect of further improving linearity of the power amplifier of An (Then, Paragraph 17, last four lines), and to include the through-silicon via of Birner in the circuit of An, which would have the effect of providing a well-known connection medium to connect two transistors (Birner, Paragraph 57, lines 1-6).
Regarding claim 2, An further discloses:
wherein the at least one Gallium Nitride field-effect-transistor provides the power amplifier with the operating power to operate the power amplifier (An, Fig. 3, see connection between VDD and amplifying transistors M1 via transistors M2) in a linear state that amplifies the radio frequency signal proportionally (Paragraph 5, lines 1-5 [amplifier of An is a linear amplifier configured to work in a linear state]).
Regarding claim 3, An further discloses:
wherein the at least one linearizing circuit compares the operating power with the supply voltage (An, Fig. 3, see connection between M1a, M1 and VDD).
Regarding claim 4, An further discloses:
wherein the at least one linearizing circuit includes a first linearizing transistor (An, Fig. 3, see T1 in modified Fig. 3 above) and a second linearizing transistor (Fig. 3, see T2 in modified Fig. 3 above).
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Regarding claim 5, An fails to disclose:
wherein the first linearizing transistor and the second linearizing transistor are Gallium Nitride field-effect-transistors.
However, Then teaches wherein the first linearizing transistor and the second linearizing transistor are Gallium Nitride field-effect-transistors (Then, Paragraph 37, lines 8-11 [see the usage of a Gallium Nitride transistor in a power amplifier in Fig. 4B]).
An, Wagh, Kwon, Then, and Birner are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified An to incorporate the teachings of Then to use the Gallium Nitride transistors of Then to implement the transistors of An, which would have the effect of further improving linearity of the power amplifier of An (Then, Paragraph 17, last four lines).
Regarding claim 6, An further discloses:
wherein the first linearizing transistor receives the supply voltage generated by the envelope tracker (An, Fig. 3, see connection between VDD and T1 in modified Fig. 3 above) and to provide a signal to the at least one Gallium Nitride field-effect-transistor (Fig. 3, see connection between T1 and G1 in modified Fig. 3 above) depending on a signal received from the second linearizing transistor (Fig. 3, see connection between T1 and T2 in modified Fig. 3 above).
Regarding claim 7, An further discloses:
wherein the second linearizing transistor generates a signal to be sent to the first linearizing transistor based on the operating power provided to the power amplifier (An, Fig. 3, see connection between T1, T2, and VDD in modified Fig. 3 above).
Regarding claim 8, An further discloses:
wherein the first linearizing transistor has a source connected to the envelope tracker (An, Fig. 3, see connection between source of T1 and VDD in modified Fig. 3 above), and a gate connected to a gate of the second linearizing transistor (Fig. 3, see connection between gate of T1 and gate of T2 in modified Fig. 3 above).
Regarding claim 9, An further discloses:
wherein the second linearizing transistor has a drain connected to a gate of the second linearizing transistor (An, Fig. 3, see connection between drain and gate of T2), and a source connected to a source of the at least one Gallium Nitride field-effect-transistor (Fig. 3, see connection between source of T2 and source of G1 in modified Fig. 3 above).
Regarding claim 10, An discloses:
A radio frequency module (An, Fig. 3) comprising: a power amplifier (Fig. 3) that amplifies the radio frequency signal (Paragraph 24, lines 1-3) with at least one complementary metal-oxide semiconductor transistor (Fig. 3, see transistors M1); the adaptation circuit (Fig. 3, M2 and M1a) configured to adapt the supply voltage to provide operating power to the power amplifier (Fig. 3, see connection between supply VDD and amplifying transistors M1 via M2 and M1a), the adaptation circuit including at least one field-effect-transistor (Fig. 3, M2) that generates the operating power in response to an increased swing of the supply voltage (Fig. 3, see connection between VDD amplifying transistors M1 via transistors M2), at least one linearizing circuit (Fig. 3, M1a) connected to a drain of the at least one Gallium Nitride field-effect-transistor (Fig. 3, see connection between M1a and drain of M2), the at least one linearizing circuit configured to linearize an operation of the at least one field-effect-transistor (Paragraph 31, lines 1-3), but fails to disclose a packaging substrate that receives a plurality of components; and a power amplifier system implemented on the packaging substrate, the power amplifier system including an envelope tracker that generates a supply voltage that changes in relation to an envelope of a radio frequency signal; and an adaptation circuit connected to the power amplifier with a plurality of copper pillars, [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor], the at least one Gallium Nitride field-effect- transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is on a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via, a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor, and an impedance matching circuit that blocks a direct current signal with an input connected to a radio frequency signal and an output connected to the gate of at least one Gallium Nitride field-effect-transistor.
However, Wagh teaches a packaging substrate that receives a plurality of components (Wagh, Col. 64, lines 28-46); and a power amplifier system implemented on the packaging substrate (Col. 64, lines 28-46), the power amplifier system including an envelope tracker (Fig. 1, 180) that generates a supply voltage that changes in relation to an envelope of a radio frequency signal (Fig. 1, ETDR, see also Col. 11, lines 44-51); but fails to teach and an adaptation circuit connected to the power amplifier with a plurality of copper pillars, [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor], the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is on a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via, a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor, and an impedance matching circuit that blocks a direct current signal with an input connected to a radio frequency signal and an output connected to the gate of at least one Gallium Nitride field-effect-transistor.
However, Kwon teaches teach and an adaptation circuit connected to the power amplifier with a plurality of copper pillars (Kwon, Fig. 1B, see connection between adaptation circuit 130 and the power amplifier transistor in substrate 200 via copper pillars 50), and an impedance matching circuit (Fig. 1B, 111) that blocks a direct current signal with an input connected to a radio frequency signal (Fig. 1B, see connection between 111 and RF input 102) and an output connected to the gate of at least one Gallium Nitride field-effect-transistor (Fig. 1B, see connection between 111 and input of 110), but fails to teach [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor], the at least one Gallium Nitride field-effect- transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is on a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via, a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor.
However, Then teaches [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor] (Then, Paragraph 37, lines 8-11 [see the usage of a Gallium Nitride transistor in a power amplifier in Fig. 4B]), the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer (Paragraph 17, lines 3-5) positioned on a silicon layer (Paragraph 17, lines 3-6) connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor (Paragraph 17, lines 6-8) that is on a die with the at least one complementary metal-oxide semiconductor transistor (Paragraph 71, lines 1-7), a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor (Paragraph 34, lines 1-6), but fails to teach the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via.
However, Birner teaches the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via (Birner, Paragraph 57, lines 1-6).
An, Wagh, Kwon, Then, and Birner are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified An to incorporate the teachings of Wagh, Kwon, Then, and Birner to implement the amplifier of An on a packaging substrate, which would have the effect of allowing good heat dissipation (Wagh, Col. 64, lines 38-42), to include an envelope tracking system in the amplifier of An, which would have the effect of improving linearity of the power amplifier of An (Wagh, Col. 1, lines 53-57), to include the copper pillars and input matching circuit of Kwon between the adaptation circuit and power amplifier of An, which would have the effect of dissipating excess heat (Kwon, Page 5, Paragraph 2, lines 2-7), to use the Gallium Nitride transistors and bias circuit of Then to implement the transistors of An, which would have the effect of further improving linearity of the power amplifier of An (Then, Paragraph 17, last four lines), and to include the through-silicon via of Birner in the circuit of An, which would have the effect of providing a well-known connection medium to connect two transistors (Birner, Paragraph 57, lines 1-6).
Regarding claim 11, An fails to disclose:
wherein the radio frequency module is a front-end module.
However, Wagh further teaches wherein the radio frequency module is a front-end module (Wagh, Col. 8, lines 34-40).
An, Wagh, Kwon, Then, and Birner are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified An to incorporate the teachings of Wagh to include the amplifier of An in a radio frequency front-end module, which would have the effect of providing a useful implementation for the amplifier of An (Wagh, Col. 8, lines 34-40).
Regarding claim 12, An further discloses:
wherein the at least one Gallium Nitride field-effect-transistor is configured to provide the power amplifier with the operating power to operate the power amplifier (An, Fig. 3, see connection between VDD and amplifying transistors M1 via transistors M2) in a linear state that amplifies the radio frequency signal proportionally (Paragraph 5, lines 1-5 [amplifier of An is a linear amplifier configured to work in a linear state]).
Regarding claim 13, An further discloses:
wherein the at least one linearizing circuit compares the operating power with the supply voltage (An, Fig. 3, see connection between M1a, M1 and VDD).
Regarding claim 14, An further discloses:
wherein the at least one linearizing circuit includes a first linearizing transistor (An, Fig. 3, see T1 in modified Fig. 3 below) and a second linearizing transistor (Fig. 3, see T2 in modified Fig. 3 below).
Regarding claim 15, An fails to disclose:
wherein the first linearizing transistor and the second linearizing transistor are Gallium Nitride field-effect-transistors.
However, Then teaches wherein the first linearizing transistor and the second linearizing transistor are Gallium Nitride field-effect-transistors (Then, Paragraph 37, lines 8-11 [see the usage of a Gallium Nitride transistor in a power amplifier in Fig. 4B]).
An, Wagh, Kwon, Then, and Birner are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified An to incorporate the teachings of Then to use the Gallium Nitride transistors of Then to implement the transistors of An, which would have the effect of further improving linearity of the power amplifier of An (Then, Paragraph 17, last four lines).
Regarding claim 16, An further discloses:
wherein the first linearizing transistor receives the supply voltage generated by the envelope tracker (An, Fig. 3, see connection between VDD and T1 in modified Fig. 3 above) and provides a signal to the at least one Gallium Nitride field-effect-transistor (Fig. 3, see connection between T1 and G1 in modified Fig. 3 above) depending on a signal received from the second linearizing transistor (Fig. 3, see connection between T1 and T2 in modified Fig. 3 above).
Regarding claim 17, An further discloses:
wherein the second linearizing transistor generates a signal to be sent to the first linearizing transistor based on the operating power provided to the power amplifier (An, Fig. 3, see connection between T1, T2, and VDD in modified Fig. 3 above).
Regarding claim 18, An further discloses:
wherein the first linearizing transistor has a source connected to the envelope tracker (An, Fig. 3, see connection between source of T1 and VDD in modified Fig. 3 above), and a gate connected to a gate of the second linearizing transistor (Fig. 3, see connection between gate of T1 and gate of T2 in modified Fig. 3 above).
Regarding claim 19, An further discloses:
wherein the second linearizing transistor has a drain connected to a gate of the second linearizing transistor (An, Fig. 3, see connection between drain and gate of T2), and a source connected to a source of the at least one Gallium Nitride field-effect-transistor (Fig. 3, see connection between source of T2 and source of G1 in modified Fig. 3 above).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wagh in view of Kwon, An, Then, and Birner.
Regarding claim 20, Wagh discloses:
A mobile device (Wagh, Col. 14, lines 22-27) comprising: a transceiver that generates a radio frequency signal (Col. 48, lines 22-26); a power management system (Fig. 1, 180) including an envelope tracker (Fig. 1, 180) that generates a power amplifier supply voltage that changes is relation to an envelope of the radio frequency signal (Fig. 1, ETDR, see also Col. 11, lines 44-51); and a front end system (Col. 8, lines 34-40) including a power amplifier that amplifies the radio frequency signal (Fig. 1, 100) with at least one complementary metal-oxide semiconductor transistor (Fig. 1, 115) an adaptation circuit (Fig. 1, 180) adapts the power amplifier supply voltage to provide operating power to the power amplifier (Fig. 1, ETDR, see also Col. 11, lines 44-51), but fails to disclose and an adaptation circuit connected to the power amplifier with a plurality of copper pillars, the adaptation circuit including at least one Gallium Nitride field-effect-transistor configured to generate the operating power in response to an increased swing of the power amplifier supply voltage, the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is one a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via, at least one linearizing circuit connected to a drain of the at least one Gallium Nitride field-effect transistor, the at least one linearizing circuit configured to linearize an operation of the at least one Gallium Nitride field-effect-transistor, a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor, and an impedance matching circuit that blocks a direct current signal with an input connected to a radio frequency signal and an output connected to the gate of at least one Gallium Nitride field effect transistor.
However, Kwon teaches and an adaptation circuit connected to the power amplifier with a plurality of copper pillars (Kwon, Fig. 1B, see connection between adaptation circuit 130 and the power amplifier transistor in substrate 200 via copper pillars 50), and an impedance matching circuit (Fig. 1B, 111) that blocks a direct current signal with an input connected to a radio frequency signal and an output connected to the gate of at least one Gallium Nitride field effect transistor (Fig. 1B, see connection between 111 and RF input 102), but fails to teach the adaptation circuit including at least one Gallium Nitride field-effect-transistor configured to generate the operating power in response to an increased swing of the power amplifier supply voltage, the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is one a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via, at least one linearizing circuit connected to a drain of the at least one Gallium Nitride field-effect transistor, the at least one linearizing circuit configured to linearize an operation of the at least one Gallium Nitride field-effect-transistor, a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor.
However, An teaches the adaptation circuit including at least one field-effect-transistor (Fig. 3, M2) configured to generate the operating power in response to an increased swing of the power amplifier supply voltage (Fig. 3, see connection between VDD amplifying transistors M1 via transistors M2) at least one linearizing circuit (Fig. 3, M1a) connected to a drain of the at least one Gallium Nitride field-effect transistor (Fig. 3, see connection between M1a and drain of M2), the at least one linearizing circuit configured to linearize an operation of the at least one Gallium Nitride field-effect-transistor (Paragraph 31, lines 1-3), but fails to teach [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor], the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer positioned on a silicon layer connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor that is one a die with the at least one complementary metal-oxide semiconductor transistor, the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via, a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor.
However, Then teaches [the adaptation circuit including at least one] Gallium Nitride [field-effect-transistor] (Then, Paragraph 37, lines 8-11 [see the usage of a Gallium Nitride transistor in a power amplifier in Fig. 4B]), the at least one Gallium Nitride field-effect-transistor having a Gallium Nitride layer (Paragraph 17, lines 3-5) positioned on a silicon layer (Paragraph 17, lines 3-6) connecting a source and a drain of the at least one Gallium Nitride field-effect-transistor (Paragraph 17, lines 6-8) that is one a die with the at least one complementary metal-oxide semiconductor transistor (Paragraph 71, lines 1-7), a bias node connected to a gate of the at least one Gallium Nitride field-effect-transistor that provides a direct current bias voltage to the gate of the at least one Gallium Nitride field-effect-transistor (Paragraph 34, lines 1-6), but fails to teach the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via.
However, Birner teaches the at least one Gallium Nitride field-effect-transistor separated from the at least one complementary metal-oxide semiconductor transistor by a through-silicon via (Birner, Paragraph 57, lines 1-6).
Wagh, Kwon, An, Then, and Birner are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Wagh to incorporate the teachings of Kwon, An, Then, and Birner to include the copper pillars and input matching circuit of Kwon between the adaptation circuit and power amplifier of Wagh, which would have the effect of dissipating excess heat (Kwon, Page 5, Paragraph 2, lines 2-7), to include the adaptation and linearization circuits of An in the amplifier of Wagh, which would have the effect of improving the linearity of the amplifier of Wagh (An, Paragraph 30, lines 6-9), to use the Gallium Nitride transistors and bias circuit of Then to implement the transistors of An, which would have the effect of further improving linearity of the power amplifier of Wagh (Then, Paragraph 17, last four lines), and to include the through-silicon via of Birner in the circuit of Wagh, which would have the effect of providing a well-known connection medium to connect two transistors (Birner, Paragraph 57, lines 1-6).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Folkmann et al. (Patent Publication Number US 2022/0368283 A1) discloses (Fig. 4) varying a supply voltage based on envelope tracking.
Wang et al. (Patent Publication Number CN 110,635,667 A) discloses (Fig. 2) varying a supply voltage based on envelope tracking.
Khesback et al. (Patent Publication Number US 2018/0331659 A1) discloses (Fig. 1) a power amplifier with an envelope tracking system formed on a packaging substrate.
Choo et al. (Patent Publication Number US 2018/0152144 A1) discloses (Fig. 7) a power amplifier with a variable supply voltage based on envelope tracking.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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