DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/16/2026, 01/20/2026, and 02/17/2026 are being considered by the examiner.
Response to Amendment
In response to the non-final office action dated 01/15/2026, applicant has amended claims 1-4, 6, 8, 11-14, 16, 18, 21-24, 26, and 28. Claims 5, 10, 15, 20, 25, and 30 are cancelled. New claims 34-39 have been added. Claims 1-4, 6-8, 11-14, 16-18, 21-24, 26-28, and 31-39 are currently pending in the application.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 6, 11-14, 16, 21-24, and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McCarty et al (US Pub No. 2017/0094433, hereinafter McCarty).
Regarding claim 1, McCarty teaches a system (Fig 6, destination receiver module 108) comprising: one or more processors (Fig 6, 8bit processor 218); and one or more non-transitory computer-readable storage devices storing computing instructions configured to run on the one or more processors (¶ [0038], addressable storage medium configured to execute on one or more processors) and cause the one or more processors to perform: receiving, from an A/V source (¶ [0039], input signals can include audio and video) and over a powerline connection (Fig 6, powerline module 507), audio source data at a speaker (Fig 6, input signal received at destination receiver module 108 including amplifier 514) comprising at least one processor (Fig 6, 8bit processor 218) and a powerline communication modulator-demodulator (PLC modem) (Fig 6 & ¶ [0083], powerline module 507 configured to receive and demodulate the combined signal via the powerline 106); after receiving the audio source data at the speaker, extracting, using the PLC modem, packets from the audio source data (¶ [0085], powerline chipset 506 configured to transform symbols into a combined signal); forwarding, by the PLC modem, at least a portion of the packets to the at least one processor (Fig 6, combined signal sent from powerline chipset 507 to CPLD 513 via 8bit interface); reconstructing, by the at least one processor, the packets into audio data (Fig 6, PLD 513 configured to extract the control signal from its associated audio signal); and outputting the audio data via the speaker (Fig 6 & ¶ [0089], DSP module 516 outputs manipulated signal to amplifier module 520 for output).
Regarding claim 2, McCarty teaches the system of claim 1, wherein the one or more packets comprise: (1) a physical layer communication protocol portion (¶ [0079], data packet is modulated with physical layer carriers or subcarriers) followed by (2) a standardized communication protocol header portion (¶ [0078], frame control header) followed by (3) a transport layer protocol portion (¶ [0078], transport layer protocol is required for end-to-end communication); and (4) a standardized communication protocol message portion (¶ [0078], payload).
Regarding claim 3, McCarty teaches the system of claim 1, wherein the audio source data comprises at least two different channels of audio data (¶ [0088], multiple channel processing of received audio signal); and the at least one processor accepts only packets associated with a channel of audio data of the at least two channels of audio data associated with the speaker (Fig 6 & ¶ [0087], digital signal processor 516 receives audio data from programmable logic device 513).
Regarding claim 4, McCarty teaches the system of claim 3, wherein: the at least the portion of the packets comprise packets associated with the channel of audio data of the at least two channels of audio data associated with the speaker (¶ [0088], multiple channel processing of received audio signal); the computing instructions are further configured to run on the one or more processors and cause the one or more processors to perform, before forwarding the at least the portion of the packets, stripping, by the PLC modem, the at least the portion of the packets from the packets (Fig 6, PLD 513 configured to extract the control signal from its associated audio signal).
Regarding claim 6, McCarty teaches the system of claim 1, wherein: the speaker further comprises a power supply (¶ [0107], receiver components include a power supply); the computing instructions are further configured to run on the one or more processors and cause the one or more processors to perform: receiving, at the at least one processor, an alternating current signal from the power supply; and generating, by the at least one processor, a time based signal using the alternating current signal (¶ [0048], time or phase delay coded into the control signal received from the AC input source).
Regarding claim 11, McCarty teaches a method implemented via execution of computing instructions configured to run at one or more processors and configured to be stored at non-transitory computer-readable media (¶ [0038], addressable storage medium configured to execute on one or more processors), the method comprising: receiving, from an A/V source (¶ [0039], input signals can include audio and video) and over a powerline connection (Fig 6, powerline module 507), audio source data at a speaker (Fig 6, input signal received at destination receiver module 108 including amplifier 514) comprising at least one processor (Fig 6, 8bit processor 218) and a powerline communication modulator- demodulator (PLC modem) (Fig 6 & ¶ [0083], powerline module 507 configured to receive and demodulate the combined signal via the powerline 106); after receiving the audio source data at the speaker, extracting, using the PLC modem, packets from the audio source data (¶ [0085], powerline chipset 506 configured to transform symbols into a combined signal); forwarding, by the PLC modem, at least a portion of the packets to the at least one processor (Fig 6, combined signal sent from powerline chipset 507 to CPLD 513 via 8bit interface); reconstructing, by the at least one processor, the packets into audio data (Fig 6, PLD 513 configured to extract the control signal from its associated audio signal); and outputting the audio data via the speaker (Fig 6 & ¶ [0089], DSP module 516 outputs manipulated signal to amplifier module 520 for output).
Regarding claim 12, McCarty teaches the method of claim 11, wherein the one or more packets comprise: (1) a physical layer communication protocol portion (¶ [0079], data packet is modulated with physical layer carriers or subcarriers) followed by (2) a standardized communication protocol header portion (¶ [0078], frame control header) followed by (3) a transport layer protocol portion (¶ [0078], transport layer protocol is required for end-to-end communication); and (4) a standardized communication protocol message portion (¶ [0078], payload).
Regarding claim 13, McCarty teaches the method of claim 11, wherein the audio source data comprises at least two different channels of audio data (¶ [0088], multiple channel processing of received audio signal); and the at least one processor accepts only packets associated with a channel of audio data of the at least two channels of audio data associated with the speaker (Fig 6 & ¶ [0087], digital signal processor 516 receives audio data from programmable logic device 513).
Regarding claim 14, McCarty teaches the method of claim 13, wherein the at least the portion of the packets comprise packets associated with the channel of audio data of the at least two channels of audio data associated with the speaker (¶ [0088], multiple channel processing of received audio signal); and the method further comprises, before forwarding the at least the portion of the packets, stripping, by the PLC modem, the at least the portion of the packets from the packets (Fig 6, PLD 513 configured to extract the control signal from its associated audio signal).
Regarding claim 16, McCarty teaches the method of claim 11, wherein: the speaker further comprises a power supply (¶ [0107], receiver components include a power supply); and the method further comprises: receiving, at the at least one processor, an alternating current signal from the power supply; and generating, by the at least one processor, a time based signal using the alternating current signal (¶ [0048], time or phase delay coded into the control signal received from the AC input source).
Regarding claim 21, McCarty teaches an article of manufacture (Fig 6, destination receiver module 108) including a non-transitory, tangible computer readable storage medium having instructions stored thereon (¶ [0038], addressable storage medium configured to execute on one or more processors) that, in response to execution by a processor (Fig 6, 8bit processor 218), are configured to cause the processor to perform: receiving, from an A/V source (¶ [0039], input signals can include audio and video) and over a powerline connection (Fig 6, powerline module 507), audio source data at a speaker (Fig 6, input signal received at destination receiver module 108 including amplifier 514) comprising at least one processor (Fig 6, 8bit processor 218) and a powerline communication modulator- demodulator (PLC modem) (Fig 6 & ¶ [0083], powerline module 507 configured to receive and demodulate the combined signal via the powerline 106); after receiving the audio source data at the speaker, extracting, using the PLC modem, packets from the audio source data (¶ [0085], powerline chipset 506 configured to transform symbols into a combined signal); forwarding, by the PLC modem, at least a portion of the packets to the at least one processor (Fig 6, combined signal sent from powerline chipset 507 to CPLD 513 via 8bit interface); reconstructing, by the at least one processor, the packets into audio data (Fig 6, PLD 513 configured to extract the control signal from its associated audio signal); and outputting the audio data via the speaker (Fig 6 & ¶ [0089], DSP module 516 outputs manipulated signal to amplifier module 520 for output).
Regarding claim 22, McCarty teaches the article of manufacture of claim 21, wherein the one or more packets comprise: (1) a physical layer communication protocol portion (¶ [0079], data packet is modulated with physical layer carriers or subcarriers) followed by (2) a standardized communication protocol header portion (¶ [0078], frame control header) followed by (3) a transport layer protocol portion (¶ [0078], transport layer protocol is required for end-to-end communication); and (4) a standardized communication protocol message portion (¶ [0078], payload).
Regarding claim 23, McCarty teaches the article of manufacture of claim 21, wherein the audio source data comprises at least two different channels of audio data (¶ [0088], multiple channel processing of received audio signal); and the at least one processor accepts only packets associated with a channel of audio data of the at least two channels of audio data associated with the speaker (Fig 6 & ¶ [0087], digital signal processor 516 receives audio data from programmable logic device 513).
Regarding claim 24, McCarty teaches the article of manufacture of claim 23, wherein: the at least the portion of the packets comprise packets associated with the channel of audio data of the at least two channels of audio data associated with the speaker (¶ [0088], multiple channel processing of received audio signal); and the instructions are further configured to cause the processor to perform, before forwarding the at least the portion of the packets, stripping, by the PLC modem, the at least the portion of the packets from the packets (Fig 6, PLD 513 configured to extract the control signal from its associated audio signal).
Regarding claim 26, McCarty teaches the article of manufacture of claim 21, wherein: the speaker further comprises a power supply (¶ [0107], receiver components include a power supply); the instructions are further configured to cause the processor to perform: receiving, at the at least one processor, an alternating current signal from the power supply; and generating, by the at least one processor, a time based signal using the alternating current signal (¶ [0048], time or phase delay coded into the control signal received from the AC input source).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 7, 17, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over McCarty et al (US Pub No. 2017/0094433, hereinafter McCarty) as applied to claims above, and further in view of Marinescu et al (US Pub No. 20030050989, hereinafter Marinescu).
Regarding claim 7, McCarty teaches the system of claim 6, generating the time based signal using the alternating current signal.
McCarty does not explicitly teach a phase locked loop circuit.
Marinescu teaches generating a time based signal using a phase locked loop circuit (See Marinescu ¶ [0052], clock reconstitution unit 16 comprising a phase lock loop (PLL)).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the phase locked loop circuit taught by Marinescu with the system taught by McCarty. Phase locked loop circuits are well known in the art as stated by Marinescu ¶ [0052]. Phase lock loop circuits provide several benefits including clock recovery, jitter reduction and signal synchronization.
Regarding claim 17, McCarty teaches the method of claim 16, generating the time based signal using the alternating current signal.
McCarty does not explicitly teach a phase locked loop circuit.
Marinescu teaches generating a time based signal using a phase locked loop circuit (See Marinescu ¶ [0052], clock reconstitution unit 16 comprising a phase lock loop (PLL)).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the phase locked loop circuit taught by Marinescu with the method taught by McCarty. Phase locked loop circuits are well known in the art as stated by Marinescu ¶ [0052]. Phase lock loop circuits provide several benefits including clock recovery, jitter reduction and signal synchronization.
Regarding claim 27, McCarty teaches the article of manufacture of claim 26, generating the time based signal using the alternating current signal.
McCarty does not explicitly teach a phase locked loop circuit.
Marinescu teaches generating a time based signal using a phase locked loop circuit (See Marinescu ¶ [0052], clock reconstitution unit 16 comprising a phase lock loop (PLL)).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the phase locked loop circuit taught by Marinescu with the article of manufacture taught by McCarty. Phase locked loop circuits are well known in the art as stated by Marinescu ¶ [0052]. Phase lock loop circuits provide several benefits including clock recovery, jitter reduction and signal synchronization.
Claim(s) 8, 18, 28, and 34-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over McCarty et al (US Pub No. 2017/0094433, hereinafter McCarty) as applied to claims above, and further in view of Dieter et al Power reduction by varying sampling rate.
Regarding claim 8, McCarty teaches system of claim 6.
McCarty does not explicitly teach a reference frequency of 48 kHz.
Dieter teaches a reference frequency of 48 kHz (See Dieter section 2.2 first paragraph, typical audio sampling rate of 48 kHz).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the reference frequency taught by Dieter with the system taught by McCarty. As stated by Dieter, systems use sampling rates slightly above the Nyquist rate and since the human hearing range is between 20 Hz to 20 kHz it makes 48 kHz a common reference frequency. This allows for accurate reconstruction of audio data while minimizing distortion.
Regarding claim 18, McCarty teaches the method of claim 16.
McCarty does not explicitly teach a reference frequency of 48 kHz.
Dieter teaches a reference frequency of 48 kHz (See Dieter section 2.2 first paragraph, typical audio sampling rate of 48 kHz).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the reference frequency taught by Dieter with the method taught by McCarty. As stated by Dieter, systems use sampling rates slightly above the Nyquist rate and since the human hearing range is between 20 Hz to 20 kHz it makes 48 kHz a common reference frequency. This allows for accurate reconstruction of audio data while minimizing distortion.
Regarding claim 28, McCarty teaches the article of manufacture of claim 26.
McCarty does not explicitly teach a reference frequency of 48 kHz.
Dieter teaches a reference frequency of 48 kHz (See Dieter section 2.2 first paragraph, typical audio sampling rate of 48 kHz).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the reference frequency taught by Dieter with the article of manufacture taught by McCarty. As stated by Dieter, systems use sampling rates slightly above the Nyquist rate and since the human hearing range is between 20 Hz to 20 kHz it makes 48 kHz a common reference frequency. This allows for accurate reconstruction of audio data while minimizing distortion.
Regarding claim 34, McCarty teaches the system of claim 6.
McCarty does not explicitly teach determining a nominal sampling rate.
Dieter teaches determining a nominal sample rate (See Dieter section 2.2 first paragraph, sampling frequency).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the nominal sampling rate taught by Dieter with the system taught by McCarty. Sampling rates are well known in the art and required for accurate reconstruction of audio data as stated by Dieter section 2.2 first paragraph. While McCarty does not explicitly state the use of a sampling rate, they do make it clear that “digital signal processing module 516 can further enhance the signal using signal processing techniques known in the art” (¶ [0103]) which would include using a sampling rate for accurate reconstruction and to avoid distortion.
Regarding claim 35, McCarty in view of Dieter teaches the system of claim 34, wherein the computing instructions are further configured to run on the one or more processors and cause the one or more processors to perform setting a latency (See McCarty ¶ [0048], coding a time delay in the control signal, time delay is synonymous with latency) of the speaker using the nominal sample rate (See Dieter section 2.2 first paragraph, sampling frequency).
Regarding claim 36, McCarty teaches the method of claim 16.
McCarty does not explicitly teach determining a nominal sampling rate.
Dieter teaches determining a nominal sample rate (See Dieter section 2.2 first paragraph).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the nominal sampling rate taught by Dieter with the method taught by McCarty. Sampling rates are well known in the art and required for accurate reconstruction of audio data as stated by Dieter section 2.2 first paragraph. While McCarty does not explicitly state the use of a sampling rate, they do make it clear that “digital signal processing module 516 can further enhance the signal using signal processing techniques known in the art” (¶ [0103]) which would include using a sampling rate for accurate reconstruction and to avoid distortion.
Regarding claim 37, McCarty in view of Dieter teaches the method of claim 36 further comprising setting a latency (See McCarty ¶ [0048], coding a time delay in the control signal, time delay is synonymous with latency) of the speaker using the nominal sample rate (See Dieter section 2.2 first paragraph, sampling frequency).
Regarding claim 38, McCarty teaches the article of manufacture of claim 26.
McCarty does not explicitly teach determining a nominal sampling rate.
Dieter teaches determining a nominal sample rate (See Dieter section 2.2 first paragraph).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the nominal sampling rate taught by Dieter with the article of manufacture taught by McCarty. Sampling rates are well known in the art and required for accurate reconstruction of audio data as stated by Dieter section 2.2 first paragraph. While McCarty does not explicitly state the use of a sampling rate, they do make it clear that “digital signal processing module 516 can further enhance the signal using signal processing techniques known in the art” (¶ [0103]) which would include using a sampling rate for accurate reconstruction and to avoid distortion.
Regarding claim 39, McCarty in view of Dieter teaches the article of manufacture of claim 38, wherein the instructions are further configured to cause the processor to perform setting a latency (See McCarty ¶ [0048], coding a time delay in the control signal, time delay is synonymous with latency) of the speaker using the nominal sample rate (See Dieter section 2.2 first paragraph, sampling frequency).
Claim(s) 31-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over McCarty et al (US Pub No. 2017/0094433, hereinafter McCarty) as applied to claims above, and further in view of Yahata et al (US Pub No. 20210012812, hereinafter Yahata).
Regarding claim 31, McCarty teaches the system of claim 1.
McCarty does not explicitly teach storing the audio source data in a first in first out buffer.
Yahata teaches storing the audio source data in a first in first out buffer.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the first-in first-out buffer taught by Yahata with the system taught by McCarty. First-in first-out buffers are well known in the art and provide several advantages including simplicity and order allowing data to be processed in the same sequence that it is received.
Regarding claim 32, McCarty teaches the method of claim 11.
McCarty does not explicitly teach storing the audio source data in a first in first out buffer.
Yahata teaches storing the audio source data in a first in first out buffer.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the first-in first-out buffer taught by Yahata with the method taught by McCarty. First-in first-out buffers are well known in the art and provide several advantages including simplicity and order allowing data to be processed in the same sequence that it is received.
Regarding claim 33, McCarty teaches the article of manufacture of claim 21.
McCarty does not explicitly teach storing the audio source data in a first in first out buffer.
Yahata teaches storing the audio source data in a first in first out buffer.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the first-in first-out buffer taught by Yahata with the article of manufacture taught by McCarty. First-in first-out buffers are well known in the art and provide several advantages including simplicity and order allowing data to be processed in the same sequence that it is received.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 6-8, 11-14, 16-18, 21-24, 16-28, and 31-33 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Iwamura (US Pub No. 2006/0245355) teaches bandwidth management within a powerline network.
Howarter et al (US Pub No. 2010/0106268) teaches packet based conversion and distribution within a powerline network.
Gubbe et al (US Pub No. 2011/0309952) teaches conflict monitoring and error detection over a powerline communications network.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER LIEBGOTT whose telephone number is (703)756-1818. The examiner can normally be reached Mon-Fri 10-6:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fan Tsang can be reached at (571)272-7547. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.M.L./Examiner, Art Unit 2694
/FAN S TSANG/Supervisory Patent Examiner, Art Unit 2694
Prosecution Insights