Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 03/22/2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. This objection specifically refers to the Non-Patent Literature documents titled “A one-way quantum computer” and “Experimental realization of any discrete unitary operator”.
Claim Objections
Claim 4 is objected to under 37 CFR 1.71(a) because of the following informalities: on lines 8-9, "performing, by the analog processor programmed using the scaled the portion of the matrix" should read "performing, by the analog processor programmed using the scaled . Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 13-15, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kirk et al. (US 5,381,361), hereinafter Kirk, in view of Kenney et al. (US 2020/0272795), hereinafter Kenney.
Regarding Claim 1, Kirk discloses an analog processor programmed to optimize a system for an objective under at least one constraint (Figure 1), using the analog processor to perform: obtaining an objective function associated with the objective, the objective function relating sets of parameter values of the system to values providing a measure of performance of the system (Column 5, line 55, f); and optimizing parameters of the system (Column 5, lines 60-61), the optimizing comprising: determining, using the analog processor, a parameter gradient (Column 5, line 62) for parameter values of the system based on the objective function and the at least one constraint (Column 4, line 67); and updating the parameter values of the system using the parameter gradient (Column 6, line 15).
Kirk does not disclose a hybrid analog-digital system.
Kenney discloses a hybrid analog-digital processor comprising a digital controller and an analog processor (Figure 1-2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the digital controller disclosed by Kenney to control the analog processor disclosed by Kirk because a hybrid analog-digital system “combine[s] the flexibility and programmability of digital controllers with the energy efficiency and inherent speed of analog circuits” (Paragraph 0146).
Regarding claim 2, Kirk discloses the analog processor of claim 1, wherein determining, using the analog processor, the parameter gradient for the parameter values based on the objective function and the at least one constraint comprises: determining, using the analog processor, a plurality of outputs of the system when configured with the parameter values (Column 6, lines 50-64); and determining, using the analog processor, the parameter gradient using the plurality of outputs of the system configured with the parameter values (Column 6, lines 50-64).
Regarding claim 3, Kirk discloses the analog processor of claim 1, wherein determining, using the analog processor, the parameter gradient for the parameter values based on the objective function and the at least one constraint comprises: performing, using the analog processor, at least one matrix operation to obtain at least one output of the at least one matrix operation (Column 5, lines 65-68); and determining the parameter gradient using the at least one output of the at least one matrix operation (Column 6, lines 50-64, Dot products D).
Regarding claim 5, Kirk discloses the analog processor of claim 1, wherein the at least one constraint comprises at least one constraint function and the method further comprises: generating a combined function using the objective function and the at least one constraint function (Column 5, line 1); wherein determining, using the analog processor, the parameter gradient for the parameter values based on the objective function and the at least one constraint comprises: determining a gradient of the combined function for the parameter values (Column 5, line 15).
Regarding claim 6, Kirk discloses the analog processor of claim 1, wherein: the at least one constraint comprises at least one constraint function (Column 4, line 67m, Constraint MMT-I=0); and determining, using the analog processor, the parameter gradient for the parameter values based on the objective function and the at least one constraint comprises: determining a gradient of the objective function for the parameter values (Column 5, line 55, Objective M); determining a gradient of the at least one constraint function for the parameter values (Column 5, line 15); and determining the parameter gradient using the gradient of the objective function and the gradient of the at least one constraint function (Column 5, line 64).
Regarding claims 13-15, they are apparatus claims that recite the same limitations as method claims 1-3 respectively, and are rejected for the same reasons.
Regarding claims 17-18, they are apparatus claims that recite the same limitations as method claims 5-6, respectively, and are rejected for the same reasons.
Regarding claim 20, it is a non-transitory computer readable medium that recites the same limitations as method claim 1 and is rejected for the same reasons.
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kirk and Kenney as applied to claims 3 and 15, respectively, above, and further in view of Dai et al., “VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference”, hereinafter Dai.
Kirk discloses using an analog processor to perform gradient descent as discussed in claim 1 above, but the combination of Kirk and Kenney does not explicitly disclose scaling the matrix before performing a matrix operation.
Dai discloses determining a scaling factor for a portion of a matrix involved in the at least one matrix operation (Section 3, Equation 1); scaling the portion of the matrix using the scaling factor to obtain a scaled portion of the matrix (Section 3, Equation 3); programming the analog processor using the scaled portion of the matrix; and performing, by the analog processor programmed using the scaled portion of the matrix, the at least one matrix operation to obtain the at least one output of the at least one matrix operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kirk and Kenney to include the scaling factor step as disclosed by Dai because scaling to lower precisions “accelerate[s] compute-bound operations such as convolution on high throughput low-cost math units, conserve memory bandwidth for memory-bound computations, and reduce storage requirements in on-chip buffers and caches” (Section 1, Paragraph 1).
Regarding claim 16, it is an apparatus claim that has the same limitations as method claim 4 and is rejected for the same reasons.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kirk and Kenney as applied to claim 6 above, and further in view of Brown (US 4,947,482).
Kirk discloses using an analog processor to perform gradient descent as discussed in claim 6 above, but the combination of Kirk and Kenney does not disclose normalizing the gradient of the objective function.
Brown discloses determining a normalization of the gradient of the objective function (Figure 5, 145); and determining a normalization of the gradient of the at least one constraint function (Column 10, line 38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit as disclosed by the combination of Kirk and Kenney to include the normalization circuitry and perform a normalization step before performing the gradient descent process disclosed by Brown because “synaptic strengths are only modified by incrementing, these signals must be normalized to preclude the strength from increasing endlessly” (Column 6, lines 18-21).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kirk and Kenney as applied to claim 1 above, and further in view of Frerix et al., “Homogeneous Linear Inequality Constraints for Neural Network Activations”, hereinafter Frerix.
The combination of Kirk and Kenney fails to explicitly disclose the objective function’s constraint being an inequality constraint.
Frerix discloses an optimization problem wherein the at least one constraint comprises at least one inequality constraint (Section 4.1, Equation 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have added an inequality constraint disclosed by Frerix to the optimization problems disclosed by Kirk and Kenney because “[t]he main advantage of the proposed method over a simple projection method is a vast speed-up at test time. Since the constraint is incorporated into the neural network architecture, a forward pass has almost no overhead compared to an unconstrained network” (Section 4.3).
Claims 9-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kirk and Kenney as applied to claims 1 and 13, respectively, above, and further in view of Lasserre, “Why the logarithmic barrier function in convex and linear programming?”.
Regarding claim 9, Kirk discloses the at least one constraint comprises a plurality of constraints represented by a plurality of constraint functions (Figure 1, 12) as well as the process of gradient descent as discussed in claim 1 above, but the combination of Kirk and Kenney does not disclose barrier functions.
Lasserre discloses generating a barrier function (Equation 2.10) using the plurality of constraint functions (Equation 2.8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the objective function as disclosed by Kirk and Kenney to use barrier functions as disclosed by Lasserre because barrier functions perform well and are popular in the art (Section I, Paragraph 1).
Regarding claim 10, Lasserre discloses generating the barrier function using the plurality of constraints comprises generating a logarithmic barrier function (Equation 2.10).
Regarding claim 19, it is an apparatus claim that has the same limitations as method claim 9 and is rejected for the same reasons.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kirk and Kenney as applied to claim 1 above, and further in view of Hassanpourghadi et al., “A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis”, hereinafter Hassanpourghadi.
The combination of Kirk and Kenney does not disclose performing further optimization using a digital processor.
Hassanpourghadi discloses after optimizing the parameter values of the system, performing a subsequent optimization on the parameter values of the system using a digital processor (Figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system disclosed by Kirk and Kenney with the subsequent digital optimization disclosed by Hassanpourghadi because “This combination of the two optimizations helps to search over a wide range and find appropriate results within a short time.” (Section 3.2)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kirk and Kenney as applied to claim 1 above, and further in view of Alspector et al., “A Parallel Gradient Descent Method for Learning in Analog VLSI Neural Networks”, hereinafter Alspector.
The combination of Kirk and Kenney does not specifically disclose being run on a machine learning system.
Alspector discloses the system is a machine learning system (Abstract), and the objective is a task to be performed by the machine learning system (Section 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the system disclosed by Kirk and Kenney to a machine learning system as disclosed by Alspector because an analog computer can compute weight changes in parallel (Section 1), speeding up the machine learning process.
Discussion of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Carolan et al. (US 2017/0351293) discloses a hybrid optical/digital system for training neural networks using gradient descent, but does not specifically discuss optimization problems. .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew Strapp whose telephone number is (571)272-9343. The examiner can normally be reached Monday-Friday 8:00 AM-4:00 PM.
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/M.S./
Matthew StrappExaminer, Art Unit 2182 (571)272-9343
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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