DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on December 3rd, 2025. The amendments are linked to the original application filed on October 13th, 2022.
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2021-0146574, filed on October 29th, 2021.
Response to Arguments
The Examiner thanks the applicant for the remarks, edits and arguments.
Regarding Claim Rejections – 35 U.S.C. 103
Applicant Remarks:
The applicant argues that Wei fails to disclose a row arbiter tree and a neural network. The applicant states that tree arbiter disclosed in Wei is significantly different that the tree arbiter disclosed in the current application. One distinction is that Wei discloses a arbiter which contains the address encoder and multiplexer. The Applicant has amended the claims to disclose this difference.
Next, the applicant argues that Luo fail to cure the deficiencies of Wei for the independent claims. The applicant states that Luo does not describe the features of the independent claims and Luo discloses an on-chip architecture which is different than the proposed invention as well.
Next the applicant states that Farian and Luo fail to teach the elements of claims 7 and 8. The applicant argues that since Wei and Luo are unable to teach the independent claim than the combination of Wei, Luo and Farian would fail to disclose the claim as a whole by virtue of claim dependency.
Next the applicant argues that Wei and Luo fail to teach claim 9. The applicant states that the arguments against Wei and Luo for claim 1 apply to claim 9 as well. Further the applicant argues that Luo fails to disclose: logic sequences among the arbiters, latch circuits, neurons, storing information in latch circuits, tokens, and multiple paths.
For these reasons the applicant believes that the claimed subject matter is distinctly different from the proposed art. Therefore, the applicant believes that current amended claims are in condition for allowance and the rejection under 35 U.S.C. should be withdrawn.
Examiner Response:
The previous Office Action, Remarks and the proposed arts have been reconsidered as well as a complete search has been completed. The examiner has found that the previously proposed art, Farian, discloses the amended claimed subject matter better than Wei and Luo. Because of this, the examiner has removed Wei and Luo as prior art and replaced them with Farian. After further search, new art was found which is able to disclose the missing elements of Farian to cover the limitations of amended claims. The examiner believes the combination of Farian and the new art discloses the amened claims in accordance to 35 U.S.C. 103 and therefore the rejection under 35 U.S.C. 103 is upheld.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5 and 12 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 5 recites, “The electronic circuit of claim 4, further comprising: …”. Claim 5 claims to be a dependent claim of Claim 4, however the applicant has cancelled claim 4. Therefore, the claim dependency structure is invalid making claim 5 unable to further limit the cancelled claim 4. For examination purposes, claim 5 will be interpreted to be a dependent claim of claim 1. Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that the dependent claims comply with the statutory requirements. Appropriate action is required.
Claim 12 recites, “The electronic circuit of claim 11, wherein …”. Claim 12 is similarly claimed to be a dependent claim of the cancelled claim 11. Therefore, claim 12 also claims to limit a cancelled claim making the dependency invalid. For examination purposes, claim 12 will be interpreted to a dependent claim of claim 9. Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that the dependent claims comply with the statutory requirements. Appropriate action is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Farian et al, Farian et al, “A Time-to-First-n-Spikes and Time-out Read-out Extension to the AER Arbitration System”, 2013, hereinafter “Farian”) and Hafliger, (Hafliger, “A Spike Based Learning Rule and its Implementation in Analog Hardware”, 2000, hereinafter “Hafliger”) in view of Mostafa et al. (Mostafa, “Automated synthesis of asynchronous event-based interfaces for neuromorphic systems”, 2013, hereinafter “Mostafa”).
Regarding claim 1, Farian discloses, “An electronic device configured to support a neural network, the electronic device comprising:” (Abstract, pp. 1; “This paper describes extensions of the asynchronous Address Event Representation (AER) arbitration mechanism for VLSI neural networks to obtain a Time-to-First-n-Spikes (TFnS) read-out operation in addition to the standard free running read-out.” This article discloses an electronic circuit which supports a neural network.)
“a neuron array including a plurality of neurons;” (System Concept and Design, pp. 2; Figure 1, pp. 1; (Fig. 1 shows a m × m neurons array and the new blocks to extend the AER functionality to provide TFnS and timeout modes.” The system discloses the use of a M x M array of neurons.)
“a row address encoder configured to receive a plurality of spike signals from the plurality of neurons and to output a plurality of request signals in response to the received plurality of spike signals; and” (System Concept and Design, pp. 2; Figure 1, pp. 1; “The Neurons which are acknowledged send their addresses through Address Encoders.” Signals are sent from the neurons to the encoders, this is seen in figure 1. This system uses two address encoders, one connected to a row of neurons and another connected the columns of the neuron array.)
“a row arbiter tree configured to receive the plurality of request signals from the row address encoder and to output a plurality of response signals in response to the received plurality of request signals,” (System Concept and Design, pp. 2; Figure 1, pp. 1; “Arbiter Logics (AL) circuitry works as a mediator between the neurons, the arbiter-cells and the external receiver. AL passes the request signals from neurons to Arbiters Cells. Arbiters Cells are stacked to build up an Arbiters Tree structure to perform arbitration between neurons and grant exclusive acknowledge signals to them. The arbiter trees are connected to the address encoders. The arbiter trees will receive signals and will evaluate them using a tree structure.)
Farian fails to explicitly disclose the remain limitations of claim, however, Hafliger discloses, “wherein the row arbiter tree includes: a first arbiter configured to return a first token in response to a first request signal and a second request signal among the plurality of request signals;” (Figure 4.13, pp. 116; Figure 4.15, pp. 118; Figure 4.13 discloses a neuromorphic diagram containing an arbiter tree, specifically a block diagram of a 3-bit sender. The diagram discloses arbiter tree connected to nodes. An arrow is placed to show the first arbiter cell connected to a first and second row. The arbiter cell schematic is disclosed in Figure 4.15.)
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“a second arbiter configured to return a second token is response to a third request signal and a fourth request signal among the plurality of request signals;” (Figure 4.13, pp. 116; Figure 4.15, pp. 118; Figure 4.13 discloses a neuromorphic diagram containing an arbiter tree, specifically a block diagram of a 3-bit sender. The diagram discloses arbiter tree connected to nodes. An arrow is placed to show a second arbiter cell connected to the third and fourth
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row. The arbiter cell schematic is disclosed in Figure 4.15.)
“a third arbiter configured to return a third token to the first arbiter and the second arbiter based on information stored in the first latch circuit and the second latch circuit,” (Figure 4.13, pp. 116; Figure 4.15, pp. 118; Figure 4.13 discloses a neuromorphic diagram containing an arbiter tree, specifically a block diagram of a 3-bit sender. The diagram discloses arbiter tree connected to nodes. An arrow is placed to show a third arbiter cell connected to the first and second arbiters. The arbiter cell schematic is disclosed in Figure 4.15.)
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“wherein the first arbiter is further configured to: receive the first request signal among the first request signal and the second request signal; and” (Figure 4.15, pp. 118; “The schematics of the arbiter cell (see also figure 4.13). This is the stackable circuit that exclusively acknowledges one of two incoming requests if its own outgoing request is acknowledged.” This cell will require signals from multiple sources in order to send a request. This will not send a signal before the signals are received. As stated, this is one example cell in a stack of arbiter cells.)
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“receive one of the first request signal and the second request signal before outputting a first response signal to the first request signal among the plurality of response signals, and” (Figure 4.15, pp. 118; “The schematics of the arbiter cell (see also figure 4.13). This is the stackable circuit that exclusively acknowledges one of two incoming requests if its own outgoing request is acknowledged.” This cell will require signals from multiple sources in order to send a request. This will not send a signal before the signals are received. As stated, this is one example cell in a stack of arbiter cells.)
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“wherein the second arbiter is further configured to: receive the third request signal among the third request signal and the further request signal; and” (Figure 4.15, pp. 118; “The schematics of the arbiter cell (see also figure 4.13). This is the stackable circuit that exclusively acknowledges one of two incoming requests if its own outgoing request is acknowledged.” This cell will require signals from multiple sources in order to send a request. This will not send a signal before the signals are received. As stated, this is one example cell in a stack of arbiter cells.)
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“receive one of the third request signal and the fourth request signal before outputting a third response signal corresponding to the third request signal among the plurality of response signals.” (Figure 4.15, pp. 118; “The schematics of the arbiter cell (see also figure 4.13). This is the stackable circuit that exclusively acknowledges one of two incoming requests if its own outgoing request is acknowledged.” This cell will require signals from multiple sources in order to send a request. This will not send a signal before the signals are received. As stated, this is one example cell in a stack of arbiter cells.)
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Farian and Hafliger fail to explicitly disclose the remaining limitations of this claim, however, Mostafa discloses, “a first latch circuit configured to store a state of the first arbiter;” (Output Interface Implementation, pp. 3; Fig. 6, pp. 3; “The arbiter that we implemented is based on the arbiter cell proposed in [9], and shown in Fig. 6. The arbiter cell time-domain multiplexes two input non-exclusive asynchronous channels onto a shared output asynchronous channel. This cell can be described using behavioral VHDL code. We make use of the behavioral description of the Muller- C element described in section II-A.” This discloses an arbiter cell. This cell shares a similar design to the schematic design disclosed in Hafliger Figure 4.15. The arbiter cells signal and outside, row, ack signal to the Muller-C elements, C, which contain a latch gate.) And (Fig. 3, pp. 2; This figure discloses the Muller-C element. This element contains a latch gate. This is used with the arbiter and would be able to store the state of the arbiter.)
“a second latch circuit configured to store a state of the second arbiter; and” (Output Interface Implementation, pp. 3; Fig. 6, pp. 3; “The arbiter that we implemented is based on the arbiter cell proposed in [9], and shown in Fig. 6. The arbiter cell time-domain multiplexes two input non-exclusive asynchronous channels onto a shared output asynchronous channel. This cell can be described using behavioral VHDL code. We make use of the behavioral description of the Muller- C element described in section II-A.” This discloses an arbiter cell. This cell shares a similar design to the schematic design disclosed in Hafliger Figure 4.15. The arbiter cells signal and outside, row, ack signal to the Muller-C elements, C, which contain a latch gate.) And (Fig. 3, pp. 2; This figure discloses the Muller-C element. This element contains a latch gate. This is used with the arbiter and would be able to store the state of the arbiter.) And (Output Interface Implementation, pp. 3; “We synthesized a 64-channel output interface, including the arbiter, from behavioral VHDL code using only the logic elements that are found in standard cells libraries.” This system uses many different channels, meaning that it would contain many arbiters to handle the channels. Using the broadest reasonable interpretation, a person of the art would recognize that this arbiter cell would repeat multiple of times containing n number of latches connected to m number of arbiters.)
“wherein the first latch circuit and the second latch circuit are located outside the first arbiter and the second arbiter,” (Fig. 6, pp. 3; “Arbiter cell schematic. The logic blocks (C) represent Muller-C elements, which can be implemented using standard gates (see Fig. 3).” This discloses an arbiter with a Muller-C element. The arbiter in this article discloses a similar structure to the arbiter in Hafliger Figure 4.15. The arbiter process is highlighted below in the square, the arrows are pointing to the Muller-C elements which contain the latch gate. This latch gate is seen in Fig 3. The image below discloses an arbiter connected to another separate component which contains the latch gate.)
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Arbiter Cell disclosed in Hafliger, pp. 118 as reference
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Farian, Hafliger and Mostafa. Farian teaches a network with uses Address Event Representation for VLSI neural networks This system uses a neural array connected to address encoders and arbitration trees. Hafliger teaches different spiking neural networks implemented on analog hardware. Mostafa teaches a system that also uses asynchronous event0based circuits to perform actions similar to biological neural networks. One of ordinary skill would have motivation to combine an address event representation neuromorphic system with the arbitration circuits disclosed in Hafliger with a system that is able to memory gates to store states in a AER communication scheme, “We used a version of the arbitration system proposed by Häfliger [12], however the modifications we describe in this work can extend other arbitration systems as well [13]. Boahen’s [13] arbitration system use ACK signals to reset neurons. In order to use our proposed arbitration system with Boahen’s variant, the OR gate from Fig. 5 should be connected to the ACK signal instead.” (Farian, Other AER Variants, pp. 4) and “We described a design flow that uses commercially available EDA tools and standard process development kits supplied by foundries for synthesizing asynchronous digital AER circuits. This method can be applied in a wide range of situations to greatly accelerate the digital design process of neuromorphic chips, including the common (and crucial) asynchronous circuits. We used the proposed flow to create the AER interface circuits for a neuromorphic chip.” (Mostafa, Conclusion, pp. 4).
Regarding claim 3, Farian discloses, “output a row signal indicating information about a row of neurons, which correspond to the plurality of response signals, from among the plurality of neurons in response to the plurality of response signals.” (System Concept and Design, pp. 2; “Arbiters Cells are stacked to build up an Arbiters Tree structure to perform arbitration between neurons and grant exclusive acknowledge signals to them. The Neurons which are acknowledged send their addresses through Address Encoders.” The encoder will send the addresses of the acknowledged neurons. As seen in Fig 1. The row encoder will send row information as “Y-Addr”.)
Regarding claim 6, Farian discloses, “sequentially output the plurality of spike signals received from the plurality of neurons as a row signal in response to the plurality of response signals.” (System Concept and Design, pp. 2; “Arbiters Cells are stacked to build up an Arbiters Tree structure to perform arbitration between neurons and grant exclusive acknowledge signals to them. The Neurons which are acknowledged send their addresses through Address Encoders.” The encoder will send the addresses of the acknowledged neurons. As seen in Fig 1. The row encoder will send row information as “Y-Addr”. This is designed to work in a continuous system, meaning this system will receive multiple spikes to the receiver))
Regarding claim 7, Farian discloses, “a column address encoder configured to receive the plurality of spike signals from the plurality of neurons and to output a plurality of request signals in response to the received plurality of spike signals; and” (System Concept and Design, pp. 2; “Arbiters Cells are stacked to build up an Arbiters Tree structure to perform arbitration between neurons and grant exclusive acknowledge signals to them. The Neurons which are acknowledged send their addresses through Address Encoders.” As seen in Fig. 1 the acknowledged neurons will send their address through the encoder. This figure discloses a row and column encoder to obtain a X_ADDR and Y_ADDR.)
“a column arbiter tree configured to receive the plurality of request signals from the column address encoder and to output a plurality of response signals in response to the received plurality of request signals from the column address encoder.” (System Concept and Design, pp. 2; “Each neuron has its unique address in a two-dimensional plane. Arbiter Logics (AL) circuitry works as a mediator between the neurons, the arbiter-cells and the external receiver. AL passes the request signals from neurons to Arbiters Cells. Arbiters Cells are stacked to build up an Arbiters Tree structure to perform arbitration between neurons and grant exclusive acknowledge signals to them. The Neurons which are acknowledged send their addresses through Address Encoders.” As seen in Fig. 1 the acknowledged neurons will send signals through the encoder and into the arbiter the arbiter will evaluate the signals and then send signals to the encoder and neurons. This figure discloses a row and column arbiter as well as encoders to obtain a X_ADDR and Y_ADDR.)
Regarding claim 8, Farian discloses, “output a column signal indicating information about neurons, which correspond to the plurality of response signals, from among the plurality of neurons in response to the plurality of response signals received from the column arbiter tree.” (Figure 1, pp. 1; This figure discloses the architecture used by this system. On the top of the figure is disclosed the column arbiter tree. This will take signals from the address encoder to produce the x_addr which is used to generate the final response. The x_addr will produce information pertaining to the columns of the array.)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Farian and Hafliger in view of Boahen, (Boahen, “Point-to-Point Connectivity Between Neuromorphic Chips Using Address Events”, 2000, hereinafter “Boahen”).
Regarding claim 2, Farian, Hafliger and Mostafa fail to explicitly disclose the limitations of this claim. However, Boahen discloses, “generate the first request signal in response to a spike signal, which is received from neurons located in a first row among the plurality of neurons, from among the plurality of spike signals;” (Fig. 12, pp. 427; “Architecture of address-event transmitter and receiver. The sending neuron’s interface circuit [shown in [Fig. 13(a)] communicates spikes to peripheral circuitry using row and column request–select lines. A row–column controller [Fig. 13(b)] relays requests from a row or column of neurons to the arbiters and relays the arbiter’s acknowledge back;” Boahen discloses a sender receive system which uses a neural array. This array is also connected to arbiter. Each row of the array will be connected to specified arbiter. This structure is disclosed in Farian Fig. 1 shown below.)
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“generate the second request signal in response to a spike signal, which is received from neurons located in a second row among the plurality of neurons, from among the plurality of spike signals;” (Fig. 12, pp. 427; “Architecture of address-event transmitter and receiver. The sending neuron’s interface circuit [shown in [Fig. 13(a)] communicates spikes to peripheral circuitry using row and column request–select lines. A row–column controller [Fig. 13(b)] relays requests from a row or column of neurons to the arbiters and relays the arbiter’s acknowledge back;” Boahen discloses a sender receive system which uses a neural array. This array is also connected to arbiter. Each row of the array will be connected to specified arbiter. This structure is disclosed in Farian Fig. 1 shown below.)
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“generate the third request signal in response to a spike signal, which is received from neurons located in a third row among the plurality of neurons, from among the plurality of spike signals; and” (Fig. 12, pp. 427; “Architecture of address-event transmitter and receiver. The sending neuron’s interface circuit [shown in [Fig. 13(a)] communicates spikes to peripheral circuitry using row and column request–select lines. A row–column controller [Fig. 13(b)] relays requests from a row or column of neurons to the arbiters and relays the arbiter’s acknowledge back;” Boahen discloses a sender receive system which uses a neural array. This array is also connected to arbiter. Each row of the array will be connected to specified arbiter. This structure is disclosed in Farian Fig. 1 shown below.)
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“generate the fourth request signal in response to a spike signal which is received from neurons located in a fourth row among the plurality of neurons, from among the plurality of spike signals.” (Fig. 12, pp. 427; “Architecture of address-event transmitter and receiver. The sending neuron’s interface circuit [shown in [Fig. 13(a)] communicates spikes to peripheral circuitry using row and column request–select lines. A row–column controller [Fig. 13(b)] relays requests from a row or column of neurons to the arbiters and relays the arbiter’s acknowledge back;” Boahen discloses a sender receive system which uses a neural array. This array is also connected to arbiter. Each row of the array will be connected to specified arbiter. This structure is disclosed in Farian Fig. 1 shown below.)
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Farian, Hafliger and Boahen. Farian teaches a network with uses Address Event Representation for VLSI neural networks This system uses a neural array connected to address encoders and arbitration trees. Hafliger teaches different spiking neural networks implemented on analog hardware. Boahen also teaches a neuromorphic system which is able to spinning neural networks. One of ordinary skill would have motivation to combine an address event representation neuromorphic system with the arbitration circuits disclosed in Hafliger and Boahen with a system that is able to memory gates to store states in an AER communication scheme, “We used a version of the arbitration system proposed by Häfliger [12], however the modifications we describe in this work can extend other arbitration systems as well [13]. Boahen’s [13] arbitration system uses ACK signals to reset neurons. In order to use our proposed arbitration system with Boahen’s variant, the OR gate from Fig. 5 should be connected to the ACK signal instead.” (Farian, Other AER Variants, pp. 4)
Claims 9, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Farian, Hafliger, and Mostafa in view of Boahen.
Regarding claim 9, Farian discloses, “An electronic device configured to support a neural network, the electronic device comprising:” (Abstract, pp. 1; “This paper describes extensions of the asynchronous Address Event Representation (AER) arbitration mechanism for VLSI neural networks to obtain a Time-to-First-n-Spikes (TFnS) read-out operation in addition to the standard free running read-out.” This article discloses a electronic circuit which supports a neural network.)
“a neuron array including a plurality of neurons; and” (System Concept and Design, pp. 2; Figure 1, pp. 1; “Fig. 1 shows a m × m neurons array and the new blocks to extend the AER functionality to provide TFnS and timeout modes.” The system discloses the use of a M x M array of neurons.)
“wherein the interface circuit includes: a row arbiter tree configured to arbitrate a plurality of request signals corresponding to the plurality of spike signals, and” (System Concept and Design, pp. 2; Figure 1, pp. 1; “Arbiter Logics (AL) circuitry works as a mediator between the neurons, the arbiter-cells and the external receiver. AL passes the request signals from neurons to Arbiters Cells. Arbiters Cells are stacked to build up an Arbiters Tree structure to perform arbitration between neurons and grant exclusive acknowledge signals to them. The arbiter trees are connected to the address encoders. The arbiter trees will receive signals and will evaluate them using a tree structure.)
“wherein a number of tokens is greater than or equal to a number of paths.” (Fig. 1, pp. 1; As seen in Fig 1. Each of the neurons can transmit a response signal to obtain X_ADDR and Y_ADDR. The interpretation of paths in this claim would be the number of possible outcomes based on the specification and the figures presented. The number of outcomes would be equal to or greater than the number of neurons in Fig 1.)
Farian fails to explicitly disclose the remaining limitations of this claim however, Hafliger discloses, “wherein the row arbiter tree includes: a first arbiter configured to return a first token in response to a first request signal and a second request signal among the plurality of requests;” (Figure 4.13, pp. 116; Figure 4.15, pp. 118; Figure 4.13 discloses a neuromorphic diagram containing an arbiter tree, specifically a block diagram of a 3-bit sender. The diagram discloses arbiter tree connected to nodes. An arrow is placed to show the first arbiter cell connected to a first and second row. The arbiter cell schematic is disclosed in Figure 4.15.)
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“a second arbiter configured to return a second token in response to a third request signal and a fourth request signal among the plurality of request signals; and” (Figure 4.13, pp. 116; Figure 4.15, pp. 118; Figure 4.13 discloses a neuromorphic diagram containing an arbiter tree, specifically a block diagram of a 3-bit sender. The diagram discloses arbiter tree connected to nodes. An arrow is placed to show a second arbiter cell connected to the third and fourth row. The arbiter cell schematic is disclosed in Figure 4.15.)
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Farian and Hafliger fail to explicitly disclose the remaining limitations of this claim, however, Mostafa discloses, “a first latch circuit configured to store a state of the first arbiter;” (Output Interface Implementation, pp. 3; Fig. 6, pp. 3; “The arbiter that we implemented is based on the arbiter cell proposed in [9], and shown in Fig. 6. The arbiter cell time-domain multiplexes two input non-exclusive asynchronous channels onto a shared output asynchronous channel. This cell can be described using behavioral VHDL code. We make use of the behavioral description of the Muller- C element described in section II-A.” This discloses an arbiter cell. This cell shares a similar design to the schematic design disclosed in Hafliger Figure 4.15. The arbiter cells signal and outside, row, ack signal to the Muller-C elements, C, which contain a latch gate.) And (Fig. 3, pp. 2; This figure discloses the Muller-C element. This element contains a latch gate. This is used with the arbiter and would be able to store the state of the arbiter.)
“a second latch circuit configured to store a state of the second arbiter,” (Output Interface Implementation, pp. 3; Fig. 6, pp. 3; “The arbiter that we implemented is based on the arbiter cell proposed in [9], and shown in Fig. 6. The arbiter cell time-domain multiplexes two input non-exclusive asynchronous channels onto a shared output asynchronous channel. This cell can be described using behavioral VHDL code. We make use of the behavioral description of the Muller- C element described in section II-A.” This discloses an arbiter cell. This cell shares a similar design to the schematic design disclosed in Hafliger Figure 4.15. The arbiter cells signal and outside, row, ack signal to the Muller-C elements, C, which contain a latch gate.) And (Fig. 3, pp. 2; This figure discloses the Muller-C element. This element contains a latch gate. This is used with the arbiter and would be able to store the state of the arbiter.) And (Output Interface Implementation, pp. 3; “We synthesized a 64-channel output interface, including the arbiter, from behavioral VHDL code using only the logic elements that are found in standard cells libraries.” This system uses many different channels, meaning that it would contain many arbiters to handle the channels. Using the broadest reasonable interpretation, a person of the art would recognize that this arbiter cell would repeat multiple of times containing n number of latches connected to m number of arbiters.)
“wherein the first latch circuit and the second latch circuit are located outside the first arbiter and the second arbiter,” (Fig. 6, pp. 3; “Arbiter cell schematic. The logic blocks (C) represent Muller-C elements, which can be implemented using standard gates (see Fig. 3).” This discloses an arbiter with a Muller-C element. The arbiter in this article discloses a similar structure to the arbiter in Hafliger Figure 4.15. The arbiter process is highlighted below in the square, the arrows are pointing to the Muller-C elements which contain the latch gate. This latch gate is seen in Fig 3. The image below discloses an arbiter connected to another separate component which contains the latch gate.)
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Arbiter Cell disclosed in Hafliger, pp. 118 as reference:
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Farian, Hafliger, and Mostafa fail to explicitly disclose the remaining limitations of this claims, however, Boaden discloses, “an interface circuit configured to transmit a plurality of spike signals generated from the plurality of neurons to an external device in parallel,” (Fig. 12, pp. 427; “Architecture of address-event transmitter and receiver.;” This figure discloses a system which is able to communicate with another external chip. This system will send spikes to request and acknowledge signals from the sender and receiver chips.)
“wherein a spike signal corresponding to a request signal obtained by returning the first token among the first request signal and the second request signal is transmitted to the external device through a first path, and” (Fig. 12, pp. 427; “Architecture of address-event transmitter and receiver. The sending neuron’s interface circuit [shown in [Fig. 13(a)] communicates spikes to peripheral circuitry using row and column request–select lines. A row–column controller [Fig. 13(b)] relays requests from a row or column of neurons to the arbiters and relays the arbiter’s acknowledge back; it also activates the address-encoder [Fig. 15(a)]. On the receiving end, a pipeline stage [Fig. 9(b)] reads and latches the address (X and Y)” The examiner would like to state that the interpretation of the word “token” is a “response signal”, this is based on the specification, pp. 12, ln. 1-2, which states, “In this case, a time in which a response signal (or token) to one request signal is returned may increase.”. The signal will send signals to the arbiter tree. At the arbiter tree, after certain criteria is met, a signal is sent back to the neuron and encoders. As seen in Farian, Hafliger and Boahen, the neurons are arranged in columns and rows and communicate with similar arbiter trees. Each tree is connected to a first and second row or signal.)
“wherein a spike signal corresponding to a request signal obtained by returning the second token among the third request signal and the fourth request signal is transmitted to the external device through a second path implemented in parallel with the first path,” (Fig. 12, pp. 427; “Architecture of address-event transmitter and receiver. The sending neuron’s interface circuit [shown in [Fig. 13(a)] communicates spikes to peripheral circuitry using row and column request–select lines. A row–column controller [Fig. 13(b)] relays requests from a row or column of neurons to the arbiters and relays the arbiter’s acknowledge back; it also activates the address-encoder [Fig. 15(a)]. On the receiving end, a pipeline stage [Fig. 9(b)] reads and latches the address (X and Y)” The examiner would like to state that the interpretation of the word “token” is a “response signal”, as per above. The signal will send signals to the arbiter tree. At the arbiter tree, after certain criteria is met, a signal is sent back to the neuron and encoders. As seen in Farian, Hafliger and Boahen, the neurons are arranged in columns and rows and communicate with similar arbiter trees. Each tree is connected to a third and fourth row or signal.) This figure discloses a system which is able to communicate with another external chip. This system will send spikes to request and acknowledge signals from the sender and receiver chips.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Farian, Hafliger, Mostafa and Boahen. Farian teaches a network with uses Address Event Representation for VLSI neural networks This system uses a neural array connected to address encoders and arbitration trees. Hafliger teaches different spiking neural networks implemented on analog hardware. Mostafa teaches a system that also uses asynchronous event0based circuits to perform actions similar to biological neural networks. Boahen also teaches a neuromorphic system which is able to spinning neural networks. One of ordinary skill would have motivation to combine an address event representation neuromorphic system with the arbitration circuits disclosed in Hafliger and Boahen with a system that is able to memory gates to store states in a AER communication scheme, “We used a version of the arbitration system proposed by Häfliger [12], however the modifications we describe in this work can extend other arbitration systems as well [13]. Boahen’s [13] arbitration system use ACK signals to reset neurons. In order to use our proposed arbitration system with Boahen’s variant, the OR gate from Fig. 5 should be connected to the ACK signal instead.” (Farian, Other AER Variants, pp. 4)
Regarding claim 10, Farian discloses, “a row address encoder configured to: transmit the plurality of spike signals to the external device in parallel through the first path and the second path based on arbitration of the row arbiter tree.” (System Concept and Design, pp. 2, Fig. 1, pp. 1; “Each neuron has its unique address in a two-dimensional plane. Arbiter Logics (AL) circuitry works as a mediator between the neurons, the arbiter-cells and the external receiver. AL passes the request signals from neurons to Arbiters Cells. Arbiters Cells are stacked to build up an Arbiters Tree structure to perform arbitration between neurons and grant exclusive acknowledge signals to them. The Neurons which are acknowledged send their addresses through Address Encoders.” Each of the spikes from the neurons are processed by the arbiter and the encoders. The system will then send the spiking signals to a receiver as seen in Fig. 1.)
Regarding claim 12, Farian discloses, “identify a return order of the first token and the second token based on information stored in the first latch circuit and the second latch circuit.” (Simulation Results, pp. 4; “First, the AER was configured to read the neurons in TFnS mode with a limit of 8 winners. Fig. 9 shows resulting asynchronous sequence of handshake signals between neurons, the AER periphery and receiver. The membrane potentials of nine most excited neurons are shown in top plot in Fig. 9 as Membrane<1:9>.” This model is able to send output of the coordinates of the requesting neuron. This would return to the receiver which neuron fired indicating a path which the signal followed.)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/PAUL M GALVIN-SIEBENALER/Examiner, Art Unit 2147
/VIKER A LAMARDO/Supervisory Patent Examiner, Art Unit 2147