DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Amendment to specification dated 11/12/2025 has been acknowledged.
Election/Restrictions
Applicant’s election of claims 1-20 without traverse in the reply filed on 11/12/2025 is acknowledged. Claims 21-37 are withdrawn by applicant.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12, 17 & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 11,469,244 B2).
Regarding claim 1, LEE teaches,
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A semiconductor memory device (Fig. 4 as annotated above), comprising:
a first select gate structure (ELn structure on left side of separation dielectric pattern 9, see as marked above, Col. 5, ll. 59-63) including a first surface (bottom surface) facing a first direction (direction D4 as marked) and a second surface (top surface) facing a second direction (direction D3) opposite the first direction,
the first surface and the second surface extending in a third direction (direction D2);
a second select gate structure (ELn as marked on right side of 9) neighboring the first select gate structure in the third direction (D2);
a sub-block insulating layer (separation dielectric pattern 9, Col. 5, l. 59) interposed between the first select gate structure and the second select gate structure;
a plurality of conductive patterns (EL & EL2 as marked) stacked over the first surface of the first select gate structure to be spaced apart from each other in the first direction (D4) and extending in the third direction (D2) to overlap the sub-block insulating layer and the second select gate structure (as seen);
a first channel structure (VS as marked above, Col. 6, l. 32) penetrating the first select gate structure and the plurality of conductive patterns (as seen);
and a second channel structure (VS as marked above) penetrating the second select gate structure and the plurality of conductive patterns,
wherein a sidewall of each of the first channel structure and the second channel structure comprises a first inflection point (bend point of sidewall of VS marked as P1, see Fig. 4 and FIG. 4 enlarged view above) disposed at a level between the plurality of conductive patterns and the sub-block insulating layer (P1 is at a level between EL and 9, see FIG. 4 above).
Regarding claim 2, LEE teaches the semiconductor memory device of claim 1 and further teaches, wherein the sidewall of each of the first channel structure and the second channel structure further comprises: a second inflection point (bend point of sidewall of VS marked as P2 above, see above including enlarged view of FIG. 4) disposed farther away from the first select gate structure and the second select gate structure than the first inflection point (as seen).
Regarding claim 3, LEE teaches the semiconductor memory device of claim 2 and further teaches ,
wherein the sidewall of each of the first channel structure and the second channel structure further comprises:
a first portion (upward portion extending from P1 in direction D3) extending from the first inflection point (P1) in the second direction (D3);
a second portion (downward portion extending from P2 in direction D4) extending from the second inflection point (P2) in the first direction (D4);
and a protrusion (lateral protrusion of sidewall of VS between P1 and P2, see as marked in enlarged view of Fig. 4 above) protruding laterally from the first inflection point and the second inflection point and disposed between the first portion and the second portion (as seen in FIG. 4 enlarged view).
Regarding claim 4, LEE teaches the semiconductor memory device of claim 2 and further teaches , wherein the plurality of conductive patterns comprise:
a first conductive pattern (EL as marked in enlarged view of Fig. 4) surrounding the first channel structure and the second channel structure at a level between the first inflection point and the second inflection point (reconsidering P2 as below, the first conductive pattern EL as marked surrounds VS between P1 and P2);
and a second conductive pattern (EL as marked in Fig. 4 below) surrounding the first channel structure and the second channel structure at a level farther away from the first select gate structure and the second select gate structure than the first conductive pattern.
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Regarding claim 5, LEE teaches the semiconductor memory device of claim 4 and further teaches , wherein each of the first channel structure and the second channel structure comprises:
a select channel component (component of VS extending from P1 to penetrate first and second select gate structure in direction D3) extending from the first inflection point (P1) to penetrate a corresponding one of the first select gate structure (as marked ) and the second select gate structure(as marked);
a first channel component (component of VS extending from P2 to penetrate the second conductive pattern in direction D4 ) extending from the second inflection point to penetrate the second conductive pattern (see Fig. 4 above);
and a second channel component (component of VS between P1 and P2 ) coupling the select channel component to the first channel component (as seen), and protruding from the first inflection point (P1) and the second inflection point (P2) to a side portion of the first conductive pattern (protrusion of VS as marked above protruding towards a vertical side portion of the first conductive pattern EL).
Regarding claim 6, LEE teaches the semiconductor memory device of claim 5 and further teaches , wherein the select channel component is formed to be narrower than each of the second channel component and the first channel component (inner width of select channel component VS at level “A” as marked below is narrower than an outer width of second channel component between P1 and P2 at level “B” as marked below) and narrower than inner width of the first channel component (inner width of the first channel component at lowest level marked as “C”).
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Regarding claim 7, LEE teaches the semiconductor memory device of claim 1 and further teaches , and further teaches ,wherein each of the first channel structure and the second channel structure comprises: a channel layer (layer of VS, Fig. 5) extending along the sidewall of each of the first channel structure and the second channel structure; and a core insulating pattern (29, Col. 7, l. 6-7) surrounded with the channel layer.
Regarding claim 8, LEE teaches the semiconductor memory device of claim 7 and further teaches , further comprising: a horizontal doped semiconductor pattern (SC) facing the second surface (top surface) of the first select gate structure, and extending in the third direction (D2) to overlap the second select gate structure; and a gate insulating layer (HL, FIG. 5) disposed between the horizontal doped semiconductor pattern and the first select gate structure, and extending to a space between the horizontal doped semiconductor pattern and the second select gate structure(as seen), wherein the channel layer (VS) penetrates the gate insulating layer (HL) to be coupled to the horizontal doped semiconductor pattern(SC).
Regarding claim 9, LEE teaches,
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A semiconductor memory device (FIG. 4 as annotated above), comprising:
a horizontal doped semiconductor pattern (source structure SC, Col. 5, l. 15-16);
a first channel structure (as marked) and a second channel structure (as marked) contacting the horizontal doped semiconductor pattern and extending in a first direction (D4);
a sub-block structure including a first select gate structure (ELn on left of 9 as marked) surrounding the first channel structure (as seen) ,
a second select gate structure (ELn on right of 9 as marked) surrounding the second channel structure (as seen),
and a sub-block insulating layer (separation dielectric pattern 9, Col. 5, l. 59) disposed between the first select gate structure and the second select gate structure (as seen);
a first stacked body (ST2, FIG. 4) including a first conductive pattern (first conductive pattern EL as marked) and a first interlayer insulating layer (12 in ST2) that are alternately stacked over the sub-block structure;
and a second stacked body (ST1, FIG. 4) including a second conductive pattern (second conductive pattern as marked) and a second interlayer insulating layer (12 in ST1) that are alternately stacked over the first stacked body,
wherein a sidewall of each of the first channel structure and the second channel structure includes a first inflection point (P1 as marked) disposed at a level between the first stacked body (bottom EL of ST2) and the sub-block insulating layer (9).
Regarding claim 10, LEE teaches the semiconductor memory device of claim 9 and further teaches, wherein each of the first channel structure and the second channel structure comprises:
a core insulating pattern (29) extending in the first direction;
and a channel layer (layer of VS) surrounding a sidewall of the core insulating pattern.
Regarding claim 11, LEE teaches the semiconductor memory device of claim 10 and further teaches , wherein: the sidewall of each of the first channel structure and the second channel structure further comprises:
a second inflection point (P2 as marked) farther away from the sub-block structure than the first inflection point (as seen) , and the channel layer comprises:
a select channel component (component of VS extending from P1 to penetrate first and second select gate structure in direction D3)extending from the first inflection point to penetrate a corresponding one of the first select gate structure and the second select gate structure;
a first channel component (component of VS extending from P2 to penetrate the second conductive pattern in direction D4 )extending from the second inflection point in the first direction to penetrate the second stacked body(see Fig. 4 above;
and a second channel component (component of VS between P1 and P2) coupling the select channel component to the first channel component,
and protruding from the first inflection point (P1) and the second inflection point (P2) to a side portion of the first stacked body (protruding portion of VS protrudes to a vertical side portion of 12 of ST2).
Regarding claim 12, LEE teaches the semiconductor memory device of claim 10 and further teaches , wherein the channel layer comprises a pipe channel component (component of VS around SC as marked below) extending to surround a sidewall, a top surface, and a bottom surface of the horizontal doped semiconductor pattern (as seen).
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Regarding claim 17, LEE teaches the semiconductor memory device of claim 12 and further teaches , further comprising: a memory layer (including BCL, CTL, TL & HL FIG. 5) extending along a surface of each of the first channel structure, the second channel structure, and the pipe channel component.
Regarding claim 20, LEE teaches the semiconductor memory device of claim 10 and further teaches, wherein: the channel layer comprises a protrusion protruding (protrusion of VS above ELn, Fig. 4) higher than the first select gate structure and the second select gate structure in a second direction opposite the first direction, and the channel layer extends to a space between an end of the core insulating pattern (29) facing the second direction (D3) and the horizontal doped semiconductor pattern (SC), and contacts the horizontal doped semiconductor pattern (SC).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 11,469,244 B2).
Regarding claim 13, LEE teaches the semiconductor memory device of claim 12 but does not explicitly teach, ,wherein each of the horizontal doped semiconductor pattern and the pipe channel component includes n-type impurities.
But LEE additionally teaches,
SC (including SCP1 & SCP2) may include an impurity-doped polysilicon (Col. 5, ll. 20-23) and VS (comprising pipe channel component) may include a polysilicon layer doped with impurities (Col. 6, ll. 66-67).
It is widely known in art that impurities maybe p type or n type.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form both SC and VS with polysilicon doped with p-type impurities , in order to simplify manufacturing process, since it has been held that choosing from a finite number of identified, predictable solutions such as p or n type impurities, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 14, LEE teaches the semiconductor memory device of claim 12 but does not explicitly tech, wherein each of the horizontal doped semiconductor pattern and the pipe channel component comprises p-type impurities.
But LEE additionally teaches,
SC (including SCP1 & SCP2) may include an impurity-doped polysilicon (Col. 5, ll. 20-23) and VS (comprising pipe channel component) may include a polysilicon layer doped with impurities (Col. 6, ll. 66-67).
It is widely known in art that impurities maybe p type or n type.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form both SC and VS with polysilicon doped with p-type impurities , in order to simplify manufacturing process, since it has been held that choosing from a finite number of identified, predictable solutions such as p or n type impurities, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 18, LEE teaches the semiconductor memory device of claim 17 and further teaches , further comprising: a source contact structure (CSPLG1, Col. 4, l. 65) extending from the horizontal doped semiconductor pattern (SC) in the first direction (D4) to penetrate the memory layer (HL, FIG. 5) but does not explicitly teach, wherein each of the horizontal doped semiconductor pattern and the source contact structure includes n-type impurities.
But Lee additionally teaches,
SC (including SCP1 & SCP2) may include an impurity-doped semiconductor pattern (Col. 5, ll. 20-23) and CSPLG1 may include doped silicon (col. 5 , ll. 6-7).
It is widely known in art that impurities maybe p type or n type.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form both SC and CSPLG1 with semiconductor pattern with n-type impurities, in order to simplify manufacturing process, since it has been held that choosing from a finite number of identified, predictable solutions such as p or n type impurities, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Allowable Subject Matter
Claims 15-16 & 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 15 & 19, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
a vertical semiconductor pattern penetrating the horizontal doped semiconductor pattern and the pipe channel component and a source contact structure coupled to the vertical semiconductor pattern and extending in the first direction, wherein the source contact structure includes n-type impurities (claim 15)
further comprising: a vertical semiconductor pattern penetrating the memory layer, the horizontal doped semiconductor pattern, and the pipe channel component; and a source contact structure coupled to the vertical semiconductor pattern and extending in the first direction, wherein the source contact structure includes n-type impurities, and the horizontal doped semiconductor pattern includes p-type impurities(claim 19).
Claim 16 is objected to being dependent on claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813