DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed February 10, 2026 has been entered. Claims 1-4, 8-11, and 14-15 remain pending in the application. Applicant’s amendments to the claims have overcome each and every 35 U.S.C. § 112 rejection previously set forth in the Non-Final Office Action mailed November 28, 2025, hereafter referred to as the Non-Final Office Action, with one exception outlined below.
As described in the Non-Final Office Action, independent claims 1 and 8 recite the limitation “each one of the plurality of compensation transistors”, however, compensation transistors have not previously been introduced in any of the claims, and examiner believes that the limitation is meant to refer to the previously introduced “plurality of compensation capacitors”. Claims 1 and 8 should be amended to recite “each one of the plurality of compensation capacitors”.
Response to Arguments
Applicant's arguments filed February 10, 2026 have been fully considered but they are not persuasive. Applicant argues, see pages 6-9, that previously presented prior art reference Mu (Patent Publication Number US 2018/0191312 A1), hereafter referred to as Mu, fails to disclose compensation capacitors coupled to the non-control terminals of a cascode transistor, that incorporating the variable capacitor of Mu in previously presented prior art reference Yeo et al. (Patent Number US 6,292,060 B1), as cited by applicant, hereafter referred to as Yeo, would require including the entire feedback circuit path of Mu, that Yeo and Mu teach away from each other, that there is a lack of motivation to combine the references, that Mu addresses a different problem than that stated in the instant application, and that Yeo fails to disclose a selective compensation capacitor. Examiner respectfully disagrees.
Regarding applicant’s first argument, applicant argues that Mu fails to disclose compensation capacitors coupled to the non-control terminals of a cascode transistor, and that therefore, the combination with Yeo is inappropriate. Examiner respectfully disagrees.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As described in the Non-Final Office Action, Yeo discloses the feature of a compensation capacitor coupled to the non-control terminals of a cascode transistor (Yeo, Fig. 1, C2), and therefore, Mu is not required to disclose this feature as it was only cited for replacing a capacitor with a variable capacitor, which would have the effect of allowing for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7).
Regarding applicant’s second argument, applicant argues that combining Mu with Yeo would require including all of the feedback circuit path of Mu, and that therefore, the combination with Yeo is inappropriate. Examiner respectfully disagrees.
As described in the Non-Final Office Action, Mu was only cited for replacing a capacitor with a variable capacitor, and not for the larger feedback circuit. Replacing a capacitor with a variable capacitor is the only required modification for realizing the benefit of allowing for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7).
Regarding applicant’s third argument, applicant argues that Yeo teaches a compensation capacitor to provide maximum gain, and that a selective compensation capacitor would counteract this goal, and that therefore, the combination with Yeo is inappropriate. Examiner respectfully disagrees.
However, as shown in Yeo, Fig. 2 (Yeo, see also Col. 2, line 63-Col. 3, line 7), depending on the output impedance of the amplifier of Yeo, the optimum capacitance value can change. Therefore, utilizing the variable capacitor of Mu to implement the capacitor of Yeo would allow for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7). Therefore, Yeo does not teach away from including a variable capacitor, and in fact provides explicit motivation for a combination with Mu.
Regarding applicant’s fourth argument, applicant argues that there is a lack of motivation to combine Mu with Yeo. Examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the combination of replacing the fixed capacitor of Yeo with the variable capacitor of Mu would allow for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7).
Regarding applicant’s fifth argument, applicant argues that Mu addresses a variable capacitor for impedance matching instead of addressing parasitic capacitance between two cascode transistors, and that therefore, the combination with Yeo is inappropriate. Examiner respectfully disagrees.
In response to applicant's argument that Mu addresses a variable capacitor for impedance matching, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Furthermore, the difference in goal between Mu and the instant application does not affect the motivation used to combine Mu with Yeo. Namely to allow for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7). The purpose of the feedback circuit of Mu is not relevant to the combination of replacing a fixed capacitor with a variable capacitor.
Regarding applicant’s sixth argument, applicant argues that Yeo fails to disclose a selectively coupled compensation capacitor, and that therefore, the combination with Yeo is inappropriate. Examiner respectfully disagrees.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As described in the Non-Final Office Action, Mu discloses a selective capacitor, which, when combined with the fixed capacitor of Yeo, allows for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7). Therefore, Yeo is not required to disclose a selective capacitor, as that is the purpose of the combination with Mu.
Therefore, all of applicant’s arguments are unconvincing and the rejections of claims 1-4, 8-11, and 14-15 are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 8-11, and 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 8, the claims recite the limitation "each one of the plurality of compensation transistors" in lines 10 and 5-6, respectively. There is insufficient antecedent basis for this limitation in the claims. Amending the limitation to “each one of the plurality of compensation capacitors” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 2-4, 9-11, and 14-15 are likewise rejected under this logic by virtue of their dependencies on claims 1 or 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yeo in view of Mu.
Regarding claim 1, Yeo discloses:
An amplifying circuit (Yeo, Fig. 1), comprising: a first transistor (Fig. 1, M2); a second transistor (Fig. 1, M1), coupled to the first transistor in series (Fig. 1, see connection between M2 and M1); and a compensation capacitor (Fig. 1, C2), selectively coupled to a first terminal (Fig. 1, see connection between C2 and drain of M2) and a second terminal of the first transistor (Fig. 1, see connection between C2 and source of M2), wherein the first terminal and the second terminal are not control terminals (Fig. 1, see that first and second terminals of M2 are drain and source terminals, respectively), the compensation capacitor for compensating for parasitic capacitance generated between the first transistor and the second transistor (Col. 2, lines 57-62); but fails to disclose a plurality of switches; [a] plurality of [compensation capacitors], wherein each one of the plurality of compensation transistors is coupled to a corresponding one of the plurality of switches in series; wherein the plurality of compensation capacitors are coupled in parallel.
However, Mu teaches a plurality of switches (Mu, Fig. 9, 520-1 – 520-N); [a] plurality of [compensation capacitors] (Fig. 9, 510-1 – 510-N), wherein each one of the plurality of compensation transistors is coupled to a corresponding one of the plurality of switches in series (Fig. 9, see series connections of 510-1 – 510-N to 520-1 – 520-N); wherein the plurality of compensation capacitors are coupled in parallel (Fig. 9, see parallel connection of 520-1 – 520-N).
Yeo and Mu are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Yeo to incorporate the teachings of Mu to use the variable capacitor network of Mu for the compensation capacitor of Yeo, which would have the effect of allowing for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7).
Regarding claim 2, Yeo further discloses:
wherein the first transistor is a common gate amplifier (Yeo, Fig. 1, see that gate of M2 is not in RF signal path), and the second transistor is a common source amplifier (Fig. 1, see that source of M1 is not in RF signal path).
Regarding claim 3, Yeo further discloses:
wherein the first transistor and the second transistor are NMOSs (Yeo, Fig. 1, see that M2 and M1 are NMOS transistors), the first terminal is a drain (Fig. 1, see that C2 is coupled to drain of M2), and the second terminal is a source (Fig. 1, see that C2 is coupled to source of M2).
Regarding claim 4, Yeo further discloses:
wherein the first terminal of the first transistor receives a first predetermined voltage (Yeo, Fig. 1, see connection between drain of M2 and VDD), wherein the second terminal of the first transistor is coupled to a drain of the second transistor (Fig. 1, see connection between source of M2 and drain of M1), a gate of the second transistor receives an input voltage (Fig. 1, see connection between gate of M1 and Vin), and a source of the second transistor is coupled to a ground voltage level (Fig. 1, see connection between source of M1 and ground).
Claims 8-11, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheol et al. (Patent Publication Number KR 2014/0033186 A), hereafter referred to as Cheol, in view of Yeo and Mu.
Regarding claim 8, Cheol discloses:
An amplifying circuit (Cheol, Fig. 3), comprising: a plurality of first transistors (Fig. 3, see “Main” and “Aux” transistors); a second transistor (Fig. 3, see “T2” in modified Fig. 3 below), coupled to the first transistors in series (Fig. 3, see connection between T2, Main, and Aux in modified Fig. 3 below); wherein when the amplifying circuit operates in a first gain mode, a first number of the plurality of first transistors are turned on (Page 4, Paragraph 5 [Main transistor is activated, Aux transistor is deactivated]; wherein when the amplifying circuit operates in a second gain mode, a third number of the plurality of first transistors are turned on (Page 4, Paragraph 6 [Main and Aux transistors are both activated]; wherein the first number is larger than the third number (Page 4, Paragraphs 5-6), but fails to disclose and a compensation capacitor group, comprising a plurality of compensation capacitors and a plurality of switches, wherein each one of the plurality of compensation transistors is coupled to a corresponding one of the plurality of switches in series, wherein the plurality of compensation capacitors are coupled in parallel; and the plurality of compensation capacitors for compensating for parasitic capacitance generated between a first transistor of the plurality of first transistors and the second transistors; [in a first gain mode] and a second number of the plurality of compensation capacitors are coupled between a first terminal and a second terminal of the plurality of first transistors; [in a second gain mode] and a fourth number of the plurality of compensation capacitors are coupled between the first terminal and the second terminal of the plurality of first transistors; and the second number is larger than the fourth number; wherein a number of the plurality of compensation capacitors coupled to the plurality of first transistors is proportional to a gain provided by the amplifying circuit.
However, Yeo teaches and a compensation capacitor group (Yeo, Fig. 1, C2), and the plurality of compensation capacitors for compensating for parasitic capacitance generated between a first transistor of the plurality of first transistors and the second transistor (Col. 2, lines 57-62); but fails to teach comprising a plurality of compensation capacitors and a plurality of switches, wherein each one of the plurality of compensation transistors is coupled to a corresponding one of the plurality of switches in series, wherein the plurality of compensation capacitors are coupled in parallel; [in a first gain mode] and a second number of the plurality of compensation capacitors are coupled between a first terminal and a second terminal of the plurality of first transistors; [in a second gain mode] and a fourth number of the plurality of compensation capacitors are coupled between the first terminal and the second terminal of the plurality of first transistors; and the second number is larger than the fourth number; wherein a number of the plurality of compensation capacitors coupled to the plurality of first transistors is proportional to a gain provided by the amplifying circuit.
However, Mu teaches comprising a plurality of compensation capacitors (Mu, Fig. 9, 510-1 – 510-N) and a plurality of switches (Fig. 9, 520-1 – 520-N), wherein each one of the compensation transistors is coupled to a corresponding one of the plurality of switches in series (Fig. 9, see series connections of 510-1 – 510-N to 520-1 – 520-N), wherein the plurality of compensation capacitors are coupled in parallel (Fig. 9, see parallel connection of 520-1 – 520-N); [in a first gain mode] and a second number of the plurality of compensation capacitors are coupled between a first terminal and a second terminal of the plurality of first transistors (consider closing switches 520-1 and 520-2 to activate capacitors 510-1 and 510-2); [in a second gain mode] and a fourth number of the plurality of compensation capacitors are coupled between the first terminal and the second terminal of the plurality of first transistors (consider closing switch 520-1 to activate capacitor 510-1); and the second number is larger than the fourth number (for implementation as a compensation capacitor group in Cheol, additional capacitance [by coupling additional capacitors] is required when multiple first transistors are activated [when the parasitic capacitance being compensated is greater]); wherein a number of the plurality of compensation capacitors coupled to the plurality of first transistors is proportional to a gain provided by the amplifying circuit (consider the additional gain provided by activating the auxiliary amplifier of Cheol, and the additional compensation capacitor required to maintain full compensation with the auxiliary amplifier activated).
Cheol, Yeo, and Mu are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cheol to incorporate the teachings of Yeo and Mu to include the compensation capacitor of Yeo in the amplifier of Cheol, which would have the effect of increasing the gain and Q factor of the amplifier of Cheol (Cheol, Col. 2, lines 57-62) and to use the variable capacitor network of Mu for the compensation capacitor of Yeo, which would have the effect of allowing for adjusting the capacitance value of the capacitor of Yeo (Mu, Paragraph 38, lines 13-14) to provide optimum performance for a variety of operating conditions (Yeo, Col. 2, line 63-Col. 3, line 7), and to provide additional capacitance via the variable capacitor network of Mu corresponding to the higher gain modes of Cheol, which would have the effect of compensating increased capacitance from the auxiliary transistor of Cheol.
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Regarding claim 9, Cheol further discloses:
wherein the plurality of first transistors are common gate amplifiers (Cheol, Fig. 3, see that “Main” and “Aux” are in the common gate configuration), and the second transistor is a common source amplifier (Fig. 3, see connection between source of T2 and ground in modified Fig. 3 above).
Regarding claim 10, Cheol further discloses:
wherein the plurality of first transistors and the second transistor are NMOSs (Cheol, Fig. 3, see that “Main” and “Aux” are NMOS transistors), the first terminal is a drain (Fig. 3, see that terminals of “Main” and “Aux” coupled to “Supply/Output” are the respective drains in modified Fig. 3 above), and the second terminal is a source (Fig. 3, see that terminals of “Main” and “Aux” coupled to T2 are the respective sources in modified Fig. 3 above).
Regarding claim 11, Cheol further discloses:
wherein the first terminals of the plurality of first transistors receive a first predetermined voltage (Cheol, Fig. 3, see that drains of Main and Aux are coupled to Supply/Output in modified Fig. 3 above), wherein the second terminal of the plurality of first transistors is coupled to a drain of the second transistor (Fig. 3, see that sources of Main and Aux are coupled to drain of T2 in modified Fig. 3 above), a gate of the second transistor receives an input voltage (Fig. 3, see connection between Input and gate of T2 in modified Fig. 3 above), and a source of the second transistor is coupled to a ground voltage level (Fig. 3, see connection between T2 and ground in modified Fig. 3 above).
Regarding claim 14, Cheol further discloses:
wherein the amplifying circuit is located in a signal receiving circuit (Cheol, Page 4, Paragraph 6), wherein a control terminal of the second transistor receives an input voltage (Fig. 3, consider voltage of gate of T2 at “Input” in modified Fig. 3 above), wherein the input voltage is generated according to an input signal received by the signal receiving circuit (Page 4, Paragraph 6).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Cheol in view of Yeo and Mu as applied to claim 8 above, and further in view of Nishizono (Patent Number JP 4,005,401 B2), hereafter referred to as Nishizono.
Regarding claim 15, Cheol, Yeo, and Mu fail to disclose:
comprising an adjustable current source, wherein the adjustable current source provides a current drain path to decrease a gain of the amplifying circuit when the amplifying circuit operates in the second gain mode.
However, Nishizono teaches comprising an adjustable current source (Nishizono, Fig. 1, 46), wherein the adjustable current source provides a current drain path to decrease a gain of the amplifying circuit when the amplifying circuit operates in the second gain mode (Nishizono, Paragraph 38, lines 1-5).
Cheol, Yeo, Mu, and Nishizono are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cheol to incorporate the teachings of Nishizono to include the adjustable current source of Nishizono in the amplifier of Cheol, which would have the effect of providing additional control over the gain of the amplifier of Cheol (Nishizono, Paragraph 38, lines 1-5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ayranci et al. (Patent Number US 11,611,319 B2) discloses (Fig. 4) a variable capacitor array for a low noise amplifier.
Suzuki et al. (Patent Publication Number JP 2006/054607 A) discloses (Figs. 2, 5-6) an amplifier wherein a compensation capacitor is provided for each output path.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843