DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendment filed on 12/12/2025.
Response to Amendment
By this amendment, claims 1-6, 8-13, and 15-19 are amended. Claims 7, 14, and 20 are canceled. Claims 21-23 are newly added claims. Therefore, claims 1-6, 8-13, 15-19, and 21-23 are pending. Any objections and rejections not repeated below is withdrawn due to Applicant's amendment.
Response to Arguments
Applicant's arguments filed 12/12/2025 have been fully considered but they are not persuasive. Applicant argues in substance:
Claims 8-13 stand rejected under 35 U.S.C. § 101 because the claimed invention is directed to non-statutory subject matter. Claims 8-13 have been amended to include "non-transitory". Therefore, Applicant requests that the 35 U.S.C. § 101 rejections of claims 8-13 be withdrawn.
Claims 1-6, 8-13, and 15-19 stand rejected under 35 U.S.C. § 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more that the judicial exception.
Applicant submits that the broad application of the framework provided in the 2019 Patent Eligibility Guidance was in error, even for the originally filed claims. Regardless, pending claims 1-6, 8-13, and 15-19 have been amended to remove any conception of being to "an abstract idea". In particular, "polling a packet ingress queue for a processor a plurality of times over a plurality of intervals" as recited in independent claims 1, 8 or 15 is something for which a person cannot mentally determine. Therefore, step 2A Prong 1 is not met. Thus, Applicant request that the 35 U.S.C. § 101 rejections of claims 1-6, 8-13, and 15-19 be withdrawn.
With regard to point (a), Examiner agrees with Applicant and all 101 claim rejections are withdrawn due to the addition of the term, “non-transitory”, in claims 8-13 and Applicant’s amendments. Specifically, the limitation of “causing a performance setting for the processor to be changed or maintained based on the determination” cannot be done mentally and thus fails Step 2A Prong One of MPEP 2106.
Applicant submits that Jang only describes monitoring a work queue and does not describe "polling a packet ingress queue" as emphasized above for claim 1. Further, Jang includes no description of "determining ... whether the packet ingress queue is idle for a threshold number of polls for one or more intervals ... " as also emphasized above for claim 1. Bouvier does not cure these deficiencies in Jang. Therefore, Jang in view of Bouvier fails to support a prima facie 35 U.S.C. § 103 rejection of claim 1. Independent claim 8, as currently amended, includes similar subject matter as emphasized above for claim 1. Also, claims 2-4, 6, 10-11 and 13 are dependent on claims 1 or 8. Thus, Applicant requests that the 35 U.S.C. 103 rejections of claims 1-4, 6, 8-11, and 13 be withdrawn…
With regard to point (b), Examiner agrees with Applicant that Jang and previous prior arts fail to teach the amendments recited in the independent claims. Due to Applicant’s amendments, TAZEBAY et al. Pub. No. US 2012/0191998 Al (hereafter TAZEBAY) has been introduced to cure deficiencies. Therefore, independent claims 1, 8, and 15 and their respective dependent claims are still rejected for the reasons in this Office Action’s 103 rejection below. Argument has not been found to be persuasive.
Specification
The disclosure is objected to because of the following informalities:
[0021] 2 instances of “…telemetry intervals 303_1 through 301_5…” should read “…telemetry intervals 303_1 through 303_5…”.
Appropriate correction is required.
Claim Objections
Claim 13 is objected to because of the following informalities:
In Claim 13, "where a counter for the queue is maintained" should read "where a counter for the packet ingress queue is maintained".
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 and 18 of US 11,388,074 B2.
The following table is constructed below to show claims 1 and 8 of the instant application and claims 12 and 18 of US 11,388,074 B2.
My Application (17/966,441)
US 11,388,074 B2 (16/381,237)
1. (Currently Amended) A method, comprising:
polling a packet ingress queue for a processor a plurality of times over a plurality of intervals;
determining, from the polling, whether the packet ingress queue is idle for a threshold number of polls for one or more intervals from among the plurality of intervals; and,
causing a performance setting for the processor to be changed or maintained based on the determination.
12. A method for performance monitoring, the method comprising:
performing, by a computing device, an empty polling training workload by a first one of one or more processor cores of the computing device, the empty polling
training workload based on an empty input queue;
determining, by the computing device, one or more empty polling thresholds in response to performing the empty polling training workload, wherein respective ones of the empty polling threshold are indicative of a number of empty polls per sampling interval;
performing, by the computing device, a packet processing workload on network traffic by second ones of the one or more processor cores of the computing device in response to determining the one or more empty polling thresholds;
comparing, by the computing device, a first number of empty polls by the packet processing workload to the one or more empty polling thresholds in response to performing the packet processing workload, the comparison determining whether the first number of empty polls is less than one of the one or more empty polling thresholds; and
configuring, by the computing device, power management of the second ones of the one or more processor cores in response to comparing the first number of empty polls to the one or more empty polling thresholds, the performance level of the second ones of the one or more processor cores increased in response to determining that the first number of empty polls is greater than one of the one or more empty polling thresholds.
8. (Currently Amended) A computer readable non-transitory storage medium containing program code
that when processed by a processor causes the processor to:
poll a packet ingress queue for the processor a plurality of times over a plurality of intervals;
determine, from the polling, whether the packet ingress queue is idle for a threshold number of polls for one or more intervals from among the plurality of intervals; and
cause a performance setting for the processor to be changed or maintained based on the determination.
18. A memory circuit comprising instructions stored thereon that, in response to being executed, cause a computing device to at least:
perform an empty polling training workload by a first processor core of the computing device, the empty polling training workload based on an empty input queue;
determine one or more empty polling thresholds in response to performing the empty polling training workload, respective empty polling thresholds indicative of a number of empty polls per sampling interval; perform a packet processing workload on network traffic
by second ones of one or more processor cores of the computing device in response to determining the one or more empty polling thresholds;
compare a first number of empty polls by the packet processing workload to the one or more empty polling thresholds in response to performing the packet processing workload;
determine an empty polling trend in response to measuring a second number of empty polls;
compare the first number of empty polls to the one or more empty polling thresholds by comparing the first
number of empty polls and the empty polling trend to the one or more empty polling thresholds; and
configure power management of the second ones of the or more processor cores in response to comparing the first number of empty polls to the one or more empty polling thresholds.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 21-22 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1:
Claims 21-22 are directed to methods and falls within the statutory category of processes. Therefore, "Are the claims to a process, machine, manufacture or composition of matter?" Yes.
In order to evaluate the Step 2A inquiry "Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?" we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claim 21: The limitations of “repeatedly, determining an idle state or a busy state of an ingress queue for a processor based on receipt of network packets to the ingress queue” and “determining a metric based on an aggregation of the determined idle states of the ingress queue over time”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally determine an idle state or a busy state of a queue based on the observed number of packets received, and a person can mentally determine or calculate a metric based on an aggregation of the determined idle states such as counting the number of idle states within a period of time.
Therefore, Yes, claim 21 recites judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will
evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claim 21: The judicial exception is not integrated into a practical application.
Therefore, Do the claims recite additional elements that integrate the judicial
exception into a practical application? No, these additional elements do not integrate
the abstract idea into a practical application and they do not impose any meaningful
limits on practicing the abstract idea. The claims are directed to an abstract idea. After
having evaluated the inquires set forth in Steps 2A Prong 1 and 2, it has been
concluded that the claims not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claim 21: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception.
Therefore, "Do the claims recite additional elements that amount to significantly
more than the judicial exception? No, these additional elements, alone or in
combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, claim 21 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claim 22, it recites an additional element recitation of “wherein determining the idle state or the busy state of the ingress queue comprises determining based on a poll of the ingress queue” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, the claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, the claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 22 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-22 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by TAZEBAY et al. Pub. No. US 2012/0191998 Al (hereafter TAZEBAY).
Regarding claim 21, TAZEBAY anticipates the invention as claimed, including: A method comprising: repeatedly, determining an idle state or a busy state of an ingress queue for a processor based on receipt of network packets to the ingress queue ([0033] “…Each port unit 108 includes a queue manager 202, an Idle Port Monitor (IPM) 204, a MAC layer 210, a PHY layer 212, a port 214…”, [0035] “Each port unit 108 has multiple queues 203a-n in a queue manager 202…”, [0048] “…The transmit statistics are the number of packets transmitted via a port 214 and the receive statistics are the number of packets received via a port 214…”, [0052] “In step 304, queue depth signals are monitored once every pre-determined period of time. For example, IPM 204 periodically monitors queue depth signals every k microseconds…”, [0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”, [0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”); and determining a metric based on an aggregation of the determined idle states of the ingress queue over time ([0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”).
Regarding claim 22, TAZEBAY anticipates: The method of claim 21, wherein determining the idle state or the busy state of the ingress queue comprises determining based on a poll of the ingress queue ([0033] “…Each port unit 108 includes a queue manager 202, an Idle Port Monitor (IPM) 204, a MAC layer 210, a PHY layer 212, a port 214…”, [0035] “Each port unit 108 has multiple queues 203a-n in a queue manager 202…”, [0048] “…The transmit statistics are the number of packets transmitted via a port 214 and the receive statistics are the number of packets received via a port 214…”, [0052] “In step 304, queue depth signals are monitored once every pre-determined period of time. For example, IPM 204 periodically monitors queue depth signals every k microseconds…”, [0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”, [0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-11, 13, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over TAZEBAY et al. Pub. No. US 2012/0191998 Al (hereafter TAZEBAY) in view of Bouvier et al. Pub. No. US 2011/0022871 Al (hereafter Bouvier).
Regarding claim 1, TAZEBAY teaches a method, comprising: polling a packet ingress queue for a processor a plurality of times over a plurality of intervals ([0033] “…Each port unit 108 includes a queue manager 202, an Idle Port Monitor (IPM) 204, a MAC layer 210, a PHY layer 212, a port 214…”, [0035] “Each port unit 108 has multiple queues 203a-n in a queue manager 202…”, [0048] “…The transmit statistics are the number of packets transmitted via a port 214 and the receive statistics are the number of packets received via a port 214…”, [0052] “In step 304, queue depth signals are monitored once every pre-determined period of time. For example, IPM 204 periodically monitors queue depth signals every k microseconds…”, [0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”); determining, from the polling, whether the packet ingress queue is idle for a threshold number of polls for one or more intervals from among the plurality of intervals ([0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”, [0054] “If the transmit queues are not empty for the predetermined number of times then the process proceeds to step 302 where the system is continued to be operated in normal power mode.”, [0055] “If transmit queues are empty for a pre-determined number of times, then the process proceeds to step 308.”, [0056] “In step 308, de-queuing of data is stopped. For example, transition state signal 208 causes traffic shaper 208 to stop de-queuing data from transmit queues 203.”, [0057] “In step 312, the PHY is transitioned to a low power mode. For example, IPM 204 generates transition state signal 224 to transition PHY 212 to a low power mode.”)…
TAZEBAY fails to teach causing a performance setting for the processor to be changed or maintained based on the determination.
In analogous art Bouvier teaches causing a performance setting for the processor to be changed or maintained based on the determination ([0059] “…In response to the number of queued messages exceeding a subscription threshold, Step 608 enables a first processor. The first processor is enabled with an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions…”, [0061] “Step 612 disables the first processor in response to the number of queued messages falling below the subscription threshold. Disabling is defined as ceasing the supply of power to a processor, decreasing the power supply voltage levels to a processor, decreasing the operating frequency of a processor, or a combination of the above-mentioned actions.”).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have modified TAZEBAY to incorporate the teachings of Bouvier to optimize overall energy consumption of the system (Bouvier [0042] “…As overall energy consumption becomes more of a critical factor in system design, it is desirable to have a mechanism that can intelligently adjust the processing resources as the workload increases and decreases over time.”).
Regarding claim 2, TAZEBAY and Bouvier teach the method of claim 1, and Bouvier further teaches further comprising: gathering, from the polling, meta data that is associated with the packet ingress queue, wherein causing the performance setting for the processor to be changed or maintained is based on the determination and based on the meta data, and wherein the meta data indicates at least one of the following: i) an identity of a virtual machine to process packets received in the packet ingress queue; ii) a version of a virtual machine to process packets received in the packet ingress queue; iii) an identity of a container to process packets received in the packet ingress queue; iv) a type and/or version of a container to process packets received in the packet ingress queue; v) an identity of a thread that processes packets received in the packet ingress queue; or vi) an identity of the processor ([0059] “…In response to the number of queued messages exceeding a subscription threshold, Step 608 enables a first processor. The first processor is enabled with an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions…”, [0061] “Step 612 disables the first processor in response to the number of queued messages falling below the subscription threshold. Disabling is defined as ceasing the supply of power to a processor, decreasing the power supply voltage levels to a processor, decreasing the operating frequency of a processor, or a combination of the above-mentioned actions.”, Note: The identity of the processor chosen to be enabled or disabled must be known in order to perform either action).
Regarding claim 3, TAZEBAY and Bouvier teach the method of claim 1, and TAZEBAY further teaches wherein the packet ingress queue is implemented in memory that is accessible to the processor ([0033] “…Each port unit 108 includes a queue manager 202, an Idle Port Monitor (IPM) 204, a MAC layer 210, a PHY layer 212, a port 214…”, [0035] “Each port unit 108 has multiple queues 203a-n in a queue manager 202…”, [0048] “…The transmit statistics are the number of packets transmitted via a port 214 and the receive statistics are the number of packets received via a port 214…”, [0052] “In step 304, queue depth signals are monitored once every pre-determined period of time. For example, IPM 204 periodically monitors queue depth signals every k microseconds…”, [0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”).
Regarding claim 4, TAZEBAY and Bouvier teach the method of claim 3, and TAZEBAY further teaches wherein the processor comprises: a general purpose processor; a graphics processor; an accelerator; a network processor; or an infrastructure processing unit ([0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107, computer logic, application specific circuits (ASIC), digital signal processors, etc., or any combination thereof, as will be understood by those skilled in the arts based on the discussion given herein. Accordingly, any processor that performs the functions described herein is within the scope and spirit of the embodiments presented herein.”).
Regarding claim 6, TAZEBAY and Bouvier teach the method of claim 1, and TAZEBAY further teaches wherein the polling comprises accessing a register or memory space where a counter for the packet ingress queue is maintained, wherein the counter identifies whether the packet ingress queue is idle ([0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”, [0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”, Note: The IPM polls the queue’s count to determine idleness, wherein the queue is maintained in accessible memory).
Regarding claim 8, TAZEBAY further teaches a computer readable non-transitory storage medium containing program code that when processed by a processor causes the processor to: ([0067] “Further, the processing functions described herein could be embodied by computer program instructions that are executed by a computer processor, for example processor 105 based on instructions stored in memory 107, or any one of the hardware devices described herein. The computer program instructions cause the processor to perform the instructions described herein. The computer program instructions (e.g. software) can be stored in a computer usable medium, computer program medium, or any storage medium that can be accessed by a computer or processor…”). The other limitations are substantially the same as those of claim 1. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 9, it is an article of manufacture claim whose limitations are substantially the same as those of claim 2. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 10, it is an article of manufacture claim whose limitations are substantially the same as those of claim 3. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 11, it is an article of manufacture claim whose limitations are substantially the same as those of claim 4. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 13, it is an article of manufacture claim whose limitations are substantially the same as those of claim 6. Accordingly, it is rejected for substantially the same reasons.
Regarding claim 23, TAZEBAY teaches the method of claim 21.
TAZEBAY fails to teach causing a processor operation setting to be modified based on the metric.
In analogous art Bouvier teaches causing a processor operation setting to be modified based on the metric ([0059] “…In response to the number of queued messages exceeding a subscription threshold, Step 608 enables a first processor. The first processor is enabled with an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions…”, [0061] “Step 612 disables the first processor in response to the number of queued messages falling below the subscription threshold. Disabling is defined as ceasing the supply of power to a processor, decreasing the power supply voltage levels to a processor, decreasing the operating frequency of a processor, or a combination of the above-mentioned actions.”).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have modified TAZEBAY to incorporate the teachings of Bouvier to optimize overall energy consumption of the system (Bouvier [0042] “…As overall energy consumption becomes more of a critical factor in system design, it is desirable to have a mechanism that can intelligently adjust the processing resources as the workload increases and decreases over time.”).
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over TAZEBAY et al. Pub. No. US 2012/0191998 Al (hereafter TAZEBAY) in view of Bouvier et al. Pub. No. US 2011/0022871 Al (hereafter Bouvier) as applied to claims 1-4, 6, 8-11, 13, and 23 above, and further in view of Shorey et al. Pat. No. US 6,807,159 Bl (hereafter Shorey).
Regarding claim 5, TAZEBAY and Bouvier teach the method of claim 1.
TAZEBAY and Bouvier fail to teach wherein respective time spans of the plurality of intervals are based on a burst time of packets received in the packet ingress queue.
In analogous art Shorey teaches wherein respective time spans of the plurality of intervals are based on a burst time of packets received in the packet ingress queue (Col. 12 lines 63-67: “3. Mean Variance Policy (MEAN): In this policy, we move a connection to SNIFF mode whenever there is no data at both the master's and the slave's queues with the polling interval based on the mean and variance of inter-arrival times of previous bursts.”, Note: The burst time is less than or equal to the inter-arrival times of previous bursts).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have modified TAZEBAY and Bouvier to incorporate the teachings of Shorey to optimize power consumption while maintaining quality of service requirements (Shorey Col. 4 lines 11-14: “optimizing power consumption while maintaining quality of service requirements for end-to-end packet delay, by adjusting the polling interval for each slave based on the incoming traffic at the slave.”).
Regarding claim 12, it is an article of manufacture claim whose limitations are substantially the same as those of claim 5. Accordingly, it is rejected for substantially the same reasons.
Claims 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over TAZEBAY et al. Pub. No. US 2012/0191998 Al (hereafter TAZEBAY) in view of Bouvier et al. Pub. No. US 2011/0022871 Al (hereafter Bouvier), and further in view of Caulfield et al. Pub. No. US 2018/0205785 Al (hereafter Caulfield).
Regarding claim 15, TAZEBAY teaches …c) a first computer readable storage medium containing first program code that when processed by at least one of the plurality of computers causes a processor of the at least one of the plurality of computers to ([0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”): poll a packet ingress queue for the processor a plurality of times over a plurality of intervals ([0033] “…Each port unit 108 includes a queue manager 202, an Idle Port Monitor (IPM) 204, a MAC layer 210, a PHY layer 212, a port 214…”, [0035] “Each port unit 108 has multiple queues 203a-n in a queue manager 202…”, [0048] “…The transmit statistics are the number of packets transmitted via a port 214 and the receive statistics are the number of packets received via a port 214…”, [0052] “In step 304, queue depth signals are monitored once every pre-determined period of time. For example, IPM 204 periodically monitors queue depth signals every k microseconds…”, [0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”); determine, from the polling, whether the packet ingress queue is idle for a threshold number of polls for one or more intervals from among the plurality of queues for the plurality of intervals ([0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”, [0054] “If the transmit queues are not empty for the predetermined number of times then the process proceeds to step 302 where the system is continued to be operated in normal power mode.”, [0055] “If transmit queues are empty for a pre-determined number of times, then the process proceeds to step 308.”, [0056] “In step 308, de-queuing of data is stopped. For example, transition state signal 208 causes traffic shaper 208 to stop de-queuing data from transmit queues 203.”, [0057] “In step 312, the PHY is transitioned to a low power mode. For example, IPM 204 generates transition state signal 224 to transition PHY 212 to a low power mode.”) … of whether the packet ingress queue is idle for the threshold number of polls for the one or more intervals from among the plurality of intervals ([0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”).
TAZEBAY fails to teach d) a second computer readable storage medium containing second program code that when processed by the at least one of the plurality of computers causes a controller of the at least one of the plurality of computers to cause a performance setting for the processor to be changed or maintained based on the determination.
In analogous art Bouvier teaches d) a second computer readable storage medium containing second program code that when processed by the at least one of the plurality of computers causes a controller of the at least one of the plurality of computers to cause a performance setting for the processor to be changed or maintained based on the determination ([0059] “…In response to the number of queued messages exceeding a subscription threshold, Step 608 enables a first processor. The first processor is enabled with an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions…”, [0061] “Step 612 disables the first processor in response to the number of queued messages falling below the subscription threshold. Disabling is defined as ceasing the supply of power to a processor, decreasing the power supply voltage levels to a processor, decreasing the operating frequency of a processor, or a combination of the above-mentioned actions.”, [0016] “In an SoC including a plurality of selectively enabled asymmetric processors executing independent operating systems (OSs), a power management controller (PMC) hardware device may receive performance requirements from the OSs based upon scheduled software applications. Then, the PMC may enable processors in response to the received performance requirements, as well as queue monitoring.”, [0031] “…A plurality of operating systems (OSs) 200 is shown, each enabled as processor executable instructions stored in a memory 202…”, Note: The PMC must have access to instructions stored in memory in order to perform the functions of queue monitoring and processor adjustment).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have modified TAZEBAY to incorporate the teachings of Bouvier to optimize overall energy consumption of the system (Bouvier [0042] “…As overall energy consumption becomes more of a critical factor in system design, it is desirable to have a mechanism that can intelligently adjust the processing resources as the workload increases and decreases over time.”).
TAZEBAY and Bouvier fail to teach a data center, comprising: a) a plurality of computers communicatively coupled by one or more networks; b) a plurality of racks, the plurality of computers respectively mounted to the plurality of racks.
In analogous art Caulfield teaches a data center, comprising: a) a plurality of computers communicatively coupled by one or more networks ([0016] “In one example, the server system 100 corresponds to a data center environment that communicatively couples the plurality of servers 102 via standard network infrastructure…”); b) a plurality of racks, the plurality of computers respectively mounted to the plurality of racks ([0016] “…For example, each server cluster 200 may correspond to a server rack that provides physical structure, ventilation, etc., for a TOR switch 202 and a plurality of servers 206, 208, ... , and 210 that are located physically proximate to each other in the same server rack…”).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have modified TAZEBAY and Bouvier to incorporate the teachings of Caulfield to facilitate a low latency and high bandwidth exchange of network packets between servers in the same server rack (Caulfield [0016] “…The backplane 204 communicatively coupling each server in the server rack may facilitate a low latency and high bandwidth exchange of network packets between servers in the same server rack.”).
Regarding claim 16, TAZEBAY, Bouvier, and Caulfield teach the data center of claim 15, and Bouvier further teaches wherein the first program code is to further cause the processor to: gather, from the polling, meta data that is associated with the packet ingress queue, wherein the controller to cause the performance setting for the processor to be changed or maintained is also based on the meta data, and wherein the meta data indicates at least one of the following: i) an identity of a virtual machine to process packets received in the packet ingress queue; ii) a version of a virtual machine to process packets received in the packet ingress queue; iii) an identity of a container to process packets received in the packet ingress queue; iv) a type and/or version of a container to process packets received in the packet ingress queue; v) an identity of a thread that processes packets received in the packet ingress queue; or vi) an identity of the processor ([0059] “…In response to the number of queued messages exceeding a subscription threshold, Step 608 enables a first processor. The first processor is enabled with an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions…”, [0061] “Step 612 disables the first processor in response to the number of queued messages falling below the subscription threshold. Disabling is defined as ceasing the supply of power to a processor, decreasing the power supply voltage levels to a processor, decreasing the operating frequency of a processor, or a combination of the above-mentioned actions.”, Note: The identity of the processor chosen to be enabled or disabled must be known in order to perform either action).
Regarding claim 17, TAZEBAY, Bouvier, and Caulfield teach the data center of claim 15, and TAZEBAY further teaches wherein the packet ingress queue are implemented in memory of the computer ([0033] “…Each port unit 108 includes a queue manager 202, an Idle Port Monitor (IPM) 204, a MAC layer 210, a PHY layer 212, a port 214…”, [0035] “Each port unit 108 has multiple queues 203a-n in a queue manager 202…”, [0048] “…The transmit statistics are the number of packets transmitted via a port 214 and the receive statistics are the number of packets received via a port 214…”, [0052] “In step 304, queue depth signals are monitored once every pre-determined period of time. For example, IPM 204 periodically monitors queue depth signals every k microseconds…”, [0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”).
Regarding claim 19, TAZEBAY, Bouvier, and Caulfield teach the data center of claim 15, and TAZEBAY further teaches wherein the polling comprises accessing a register or memory space where a counter for the packet ingress queue is maintained, wherein the counter identifies whether the packet ingress queue is idle ([0066] “…the method of flowchart 300 can be implemented using one or more computer processors, such as processor 105 based on instruction stored in memory 107…”, [0053] “In step 306, it is determined whether transmit queues are empty for a predetermined number of times. For example, IPM 204 determines whether transmit queues 203 are empty m or more times.”, Note: The IPM polls the queue’s count to determine idleness, wherein the queue is maintained in accessible memory).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over TAZEBAY et al. Pub. No. US 2012/0191998 Al (hereafter TAZEBAY) in view of Bouvier et al. Pub. No. US 2011/0022871 Al (hereafter Bouvier), further in view of Caulfield et al. Pub. No. US 2018/0205785 Al (hereafter Caulfield) as applied to claims 15-17 and 19 above, and further in view of Shorey et al. Pat. No. US 6,807,159 Bl (hereafter Shorey).
Regarding claim 18, TAZEBAY, Bouvier, and Caulfield teach the data center of claim 15.
TAZEBAY, Bouvier, and Caulfield to teach wherein respective time spans of the plurality of intervals are based on a burst time of packets received in the packet ingress queue.
In analogous art Shorey teaches wherein respective time spans of the plurality of intervals are based on a burst time of packets received in the packet ingress queue (Col. 12 lines 63-67: “3. Mean Variance Policy (MEAN): In this policy, we move a connection to SNIFF mode whenever there is no data at both the master's and the slave's queues with the polling interval based on the mean and variance of inter-arrival times of previous bursts.”, Note: The burst time is less than or equal to the inter-arrival times of previous bursts).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have modified TAZEBAY, Bouvier, and Caulfield to incorporate the teachings of Shorey to optimize power consumption while maintaining quality of service requirements (Shorey Col. 4 lines 11-14: “optimizing power consumption while maintaining quality of service requirements for end-to-end packet delay, by adjusting the polling interval for each slave based on the incoming traffic at the slave.”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In particular, US 20190238442 A1 is cited because it discloses empty poll thresholds of queues to dynamically configure a processor’s power.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner respectfully requests, in response to this Office action, support be
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When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111 (c).
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/J.C.T./Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196