Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-21 are presented for examination.
Claims 1, 6, 9 and 19-21 were amended.
This is a Non-Final Action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/05/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (EP 3,800,547-IDS) and in view of Minkin et al. (US 2023/0289292) further in view of Brothers et al. (US 2007/0115292)
1. Liu teaches, A system for machine learning (Abstract; Figure 4; Paragraph 119) comprising:
one or more processors; and a non-transitory computer-readable medium storing a program executable by the one or more processors (Fig 4, Paragraphs 6-8, 28 – neural network chip including the data processing apparatus… An electronic device having the neural network chip… A board card including… a storage device… and the neural network chip… The storage device is configured to store data), the program comprising sets of instructions for:
receiving, by a processor, a plurality of commands to perform machine learning operations on multi-dimensional data (Fig 1a – teaches when an operand of a decoded first processing instructions includes an identifier of a descriptor followed by executing the first processing instruction according to the content of the descriptor; Paragraph 18 – teaches that data to be processed may include N-dimensional tensor data and that a matrix can be a tensor or two or more dimensions; Paragraph 22 teaches when a processing instructions is received, the processing instruction can be decoded first; Paragraph 23 – teaches the first processing instruction may include a data access instruction, an operation instruction, a descriptor management instruction a synchronization instruction Paragraphs 15, 17 – a data processing method includes: when an operand of a decoded first processing instruction includes an identifier of a descriptor, obtaining content of the descriptor… and executing the first processing according to the content of the descriptor):
executing, by the processor, the commands to perform the machine learning operations on the multi-dimensional data (Fig 1a:S12a – teaches executing the first processing instruction according to the content of the descriptor; Paragraph 26 – teaches determining a data address of the data corresponding to the operand of the first processing instruction in a data storage space according to the content of the descriptor; and executing data processing corresponding to the first processing instruction according to the data address; Paragraph 102 – teaches an operation corresponding to the first processing instruction according to the data address).
Liu does not explicitly teach,
wherein each command comprises: a plurality of fields embedded within the command and explicitly encoding dimensional parameters of the multi- dimensional data; and
a plurality of fields embedded within the command and describing synchronization of a particular command process with one or more other processes at a plurality of occurrences of partial completion of the particular command process.
However Minkin teaches,
wherein each command comprises: a plurality of fields embedded within the command and explicitly encoding dimensional parameters of the multi- dimensional data (Paragraph 69, Fig 3A – teaches number of dimensions of the tensor, size of each dimension, stride for each dimension, and element size in the tensor. Further teaches the parameters necessary for the TMAU to uniquely identify a block within a tensor are divided to three groups, including tensor descriptor, parameters, access descriptor, parameter and TMAU instruction parameter identifying a particular block and that the TMAU instruction parameters include just the starting coordinate of the block (e.g., (x,y)).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to incorporate Minkin’s multidimensional tensor access parameters into Liu’s tensor instruction/descriptor framework to improve tensor address generation, reduce data-access overhead, support efficient block/tile based tensor transfers and improve throughput for machine learning tensor operations. Such a modification would have amounted to applying a known tensor access technique to a similar tensor processing system to obtain the predictable result of more efficient access to multidimensional machine learning data.
However Brothers teaches,
a plurality of fields embedded within the command and describing synchronization of a particular command process with one or more other processes at a plurality of occurrences of partial completion of the particular command process (Fig 3:122, 124, 126 and 128 – teaches synchronization commands with embedding command fields; command header block ID, fence ID, wait/fence bit, register select bits, address and data words; Fig 4:142 and Paragraphs 57, 60 and 69 – teaches the wait register is updated and wait pending bit is set so as to record that a wait is in progress. The received write cycle operation is not acknowledged by MXU 110, thereby stalling the sending module. A command stream, a fence command with the same value generally precedes a wait command, The driver may establish equal value for internal fence and corresponding internal wait command according to each individual sequential event, Brothers).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to incorporate Brother’s internal wait/fence synchronization command fields into the tensor-processing command framework of Liu as modified by Minkin to coordinate dependent tensor commands, prevent read-after-write and premature-write hazards, avoid unnecessary pipeline draining, and improve throughput of multidimensional machine learning data processing. The modification would have amounted to applying a known GPU synchronization technique to a similar processor-based tensor/multidimensional data-processing system to obtain the predictable result of correctly ordered and more efficient execution of dependent tensor operations.
2. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the multi-dimensional data comprises tensors, and wherein the commands perform a function on one or more complete tensors without the execution of other commands (Paragraphs 18 & 27 – teaches data be processed may include N-dimensional tensor data… the tensor may have different dimensions… the processor can read data… execute an additional (add) operation, and obtain an operation result (A+B), Liu).
3. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the command performs a data movement or matrix multiplication operation (Paragraphs 23 and 27 – teaches the first processing instruction may include a data access instruction (or) an operation instruction… executing an additional (add) operation),
4. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the commands describe operations on the multi-dimensional data (Paragraph 24 – teaches the decoded first processing instruction includes an operation code and one or more operands… the operation code is used to indicate a processing type corresponding to the first processing instruction, Liu).
5. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the commands repeat a plurality of same operations on the multi-dimensional data (Paragraph 23 – teaches the decoded first processing instruction may include… a data access instruction, an operation instruction… the present disclosure does not limit the specific type of the first processing instruction – disclose repetitive issuance of identical operation instructions (e,g,, repeated add, multiply) is implied by Liu’s generalized instruction loop model, Liu).
6. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein at least one command addresses first multi-dimensional data that does not fit in on-chip memory of the one or more processors (Paragraphs 40 & 42 – teaches the tensor data indicated by the descriptor may be stored in an external memory (an off-chip memory) connected to the control unit, Liu).
7. The combination of Liu, Minkin and Brothers teach, The system of claim 6, wherein at least a portion of the first multi-dimensional data operated on during execution of the at least one command is stored in main memory (Paragraph 40 – On-chip storage of the identifier and content of the descriptor and off-chip storage of the tensor data indicated by the descriptor may be adopted, Liu).
8. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the machine learning operations are neural network operations (Paragraph 9 – teaches by introducing a descriptor indicating the shape of a tensor… operator efficiency when an operation of a neural network model is performed can be improved, Liu).
9. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the multi-dimensional data comprises multi-dimensional matrices of data, and wherein the commands encode the dimensions of the multi-dimensional matrices of data (Paragraph 18 – teaches the descriptor is configured to indicate a shape of a tensor… for example, a matrix can be tensor of two or more dimensions, Liu; Fig 3A – teaches command/requests for tensor access using encoded dimensional parameters, Minkin)
10. The combination of Liu, Minkin and Brothers teach, The system of claim 9, wherein the commands specify a plurality of dimension sizes for a plurality of dimensions of one or more matrices (Paragraph 18 – teaches the shape of the tensor includes dimensions of the tensor and size of each dimension of each tensor, Liu).
11. The combination of Liu, Minkin and Brothers teach, The system of claim 9, wherein the commands comprise a base address for at least one multi-dimensional matrix of data (Paragraph 20 – teaches the content of the descriptor may include at least one address parameter (such as base address of a datum point) representing an address of the tensor data, Liu).
12. The combination of Liu, Minkin and Brothers teach, The system of claim 9, wherein the commands comprise a size of each dimension for at least one multi-dimensional matrix of data (Paragraph 45 – teaches the descriptor can use a coordinate (x, y, z) to represent the shape… the size of the data storage space of the tensor data in at least one of the N dimensions, Liu).
13. The combination of Liu, Minkin and Brothers teach, The system of claim 9, wherein the commands comprise a stride size for at least one multi-dimensional matrix of data (Paragraph 45 – teaches the tensor data is stored in a memory, … the descriptor … indicates offset of the storage area in at least one of the N dimensions, Liu).
14. The combination of Liu, Minkin and Brothers teach, The system of claim of claim 9, wherein the commands comprises a data type for at least one multi-dimensional matrix of data (Paragraph 76-78, Fig 5a/5B – teaches the parameters necessary for TMAU to uniquely identify a block within a tensor are divided to three groups: a group of tensor descriptor parameters… a group of access descriptor parameter and a TMAU instruction parameter; Further teaching the tensor descriptor parameters include tensor height, tensor width, tensor stride and the element size, further, the special NaN encoding is format specific and is based on the tensor descriptor format setting, Minkin – thud disclosing tensor-access command/request parameters including element size and a tensor descriptor format setting. An element size/format setting corresponds to the data representation of the tensor elements, i.e. the claimed data type for the multidimensional matrix/tensor).
15. The combination of Liu, Minkin and Brothers teach, The system of claim 9, wherein the commands comprise a base address, a size of each dimension, a stride size, and a data type for at least one multi-dimensional matrix of data (Paragraphs 158 – teaches may take as input parameters tensor descriptor pointer, shared memory destination address, shared memory address for arrive/wait barrier, set of tensor coordinates for the access block origin, pipeline structure, and optional tensor descriptor; Paragraph 146 - teaches tensor descriptor pointer, shared memory base address and coordinates of the destination block in the tensor space, Paragraph 78 – The tensor height, tensor width, tensor stride, block height and block width are specified per dimension of the tensor; Element size, Nan, Minkin; Fig 3A/5A 0 teaches multidimensional tensor/tile parameters, Liu).
16. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the commands encode synchronization points, and wherein a plurality of commands synchronize on a partially processed multi-dimensional data set at the synchronization points (Paragraphs 80-82 – teaches Fig, 1c shows a flowchart of a data synchronization method… determining whether there is a second processing instruction that has not been executed completely… blocking or caching the first processing instruction, Liu).
17. The combination of Liu, Minkin and Brothers teach, The system of claim 16, wherein a dependent command synchronizes a partially processed multi-dimensional data set in main memory being operated on by another command (Paragraphs 40, 80-82 – teaches determining whether there is a second processing instruction that has not been executed completely… blocking or caching the first processing instruction, Liu).
18. The combination of Liu, Minkin and Brothers teach, The system of claim 17, wherein at least one command executes a wait, executes a data transaction, or generates a signal on the occurrence of a predefined event specified in the at least one command (Paragraph 82 – teaches blocking or caching the first processing instruction when there is a second processing instruction that has been executed completely, Liu).
Claims 19 and 20 are similar to claim 1 hence rejected similarly.
21. The combination of Liu, Minkin and Brothers teach, The system of claim 1, wherein the plurality of fields describing synchronization include a field identifying at least one of (Fig 3, Paragraph 44 – teaches an internal sync command format having fields including Block ID, Fence ID, EXT, DWF, Pri, FE, and Flip, It also explains that Block ID is the block ID of the module which should write the data out on receiving the token; further states that Fence ID bits are recommended to be used by the driver to identify CSP external fence registered in an event history buffer, Brothers):
a semaphore identifier that causes command execution to be contingent upon completion of a partial operation (Paragraph 45 – the selected fence/wait register pair acts as the claimed semaphore identifier it identifies the synchronization object/register pair used to determine whether execution may proceed. The wait command is contingent because the MXU holds acknowledgment until the fence/wait condition is satisfied, Brothers);
an event identifier that causes command execution to be contingent upon detection of a predefined event; or
a parameter defining a synchronization granularity that causes command execution to be contingent upon occurrence of a specified degree of partial completion of an operation (Paragraph 59 – teaches contingent execution: the waiting module is stalled until the corresponding fence condition indicates that the earlier producing module has completed the relevant operation, Brothers).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure,
Fowers et al, (US 2018/0341484) – addresses command/instruction execution in a tensor processing hardware accelerator for maching learning/ deep neural network operations, including instruction decoding, tensor operation execution and chaining tensor machine instructions. Thus it is in the same field of endeavor as claim 1 and is relevant to the claimed use of command for performing machine learning operations on multidimensional tensor data (Abstract, Fig 1, Fig3a/3B, paragraphs 23, 74, & 79).
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/AMRESH SINGH/Primary Examiner, Art Unit 2159
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