Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on 08/07/2025.
Specification
The amendment to the title filed on 08/07/2025 appears that it should read as “Circuit, System, and Method for a Power Converter with a Controller Utilizing a Predicted Gate Control Signal.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US Patent Application Publication US 2008/0094861 A1) in view of Maksimovic et al. (US Patent Application Publication US 2005/0168198 A1, hereinafter “Maksimovic”). Regarding claim 1, Wang discloses (see Fig. 4A, , Fig. 4C, Fig. 6) a circuit (see circuit of Fig. 4A), comprising: a sensing circuit (see 20C of Fig. 6) configurable to provide a comparison result (VM) based on a comparison between a reference voltage (Vref) and a feedback voltage (Vin); a synchronization circuit (comprising 19A) configurable to synchronize the comparison result based on a clock signal (synchronizing VM based on CLKINT via 32) to form a synchronous comparison result (VSW); and a controller (57) configurable to, based on the clock signal (based on CLKINT): receive the synchronous comparison result (receiving VSW via 57, which is generated based on CKLINT); determine a gate control signal based on the synchronous comparison result (VGN, VGP); and provide the gate control signal (VGP and VGN are provided to control the boost power converter of Fig. 4A). Wang does not disclose wherein a controller is configured to determine a predicted gate control signal based on the synchronous comparison result; and provide the predicted gate control signal to the sensing circuit as the feedback voltage. However, Maksimovic teaches (see Fig. 2) wherein a controller (130) is configured to determine a predicted gate control signal (d[n]Sc) based on the synchronous comparison result (comparison between ic and i[n-1]); and provide the predicted gate control signal to the sensing circuit as the feedback voltage (providing feedback of d[n]Sc via 136).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Wang wherein the controller is configured to determine a predicted gate control signal based on the synchronous comparison result; and provide the predicted gate control signal to the sensing circuit as the feedback voltage, as taught by Maksimovic, because it can help provide a predictive control method with a shorter feedback loop which can help increase the response speed of the feedback control.
Regarding claim 7, Wang discloses (see Fig. 4A, , Fig. 4C, Fig. 6) wherein the gate control signal corresponds to a charge time for a power converter (VGP and VGN correspond to the charge time of L of the boost power converter of Fig. 4A), wherein the charge time increases responsive to the synchronous comparison result having an asserted value (when VM is larger than VRAMP, VSW is asserted and the charge time increases, see Fig. 4C), and wherein the charge time decreases responsive to the synchronous comparison result having a deasserted value (when VM is smaller than VRAMP, VSW is deasserted and the charge time decreases, see Fig. 4C).
Regarding claim 9, Wang discloses (see Fig. 4A, , Fig. 4C, Fig. 6) a system, comprising: a load (15); a power source (Vin); a power converter (1D) configurable to switch power from the power source to the load; and control circuitry (2) configurable to provide a gate control signal (8B, 8A) for controlling the power converter to switch the power from the power source to the load, the control circuitry including: a sensing circuit (see 20C of Fig. 6) configurable to provide a comparison result (VM) based on a comparison between a reference voltage (Vref) and a feedback voltage (Vin); a synchronization circuit (comprising 19A) configurable to synchronize the comparison result based on a clock signal (synchronizing VM based on CLKINT via 32) to provide a synchronous comparison result (VSW); and a controller (57) configurable to: receive the synchronous comparison result (receiving VSW via 57); determine a gate control signal based on the synchronous comparison result (VGN, VGP); and provide the gate control signal for controlling the power converter (VGP and VGN are provided to control the boost power converter of Fig. 4A). Wang does not disclose wherein a controller is configured to determine a predicted gate control signal based on the synchronous comparison result; and provide the predicted gate control signal to the sensing circuit as the feedback voltage. However, Maksimovic teaches (see Fig. 2) wherein a controller (130) is configured to determine a predicted gate control signal (d[n]Sc) based on the synchronous comparison result (comparison between ic and i[n-1]); and provide the predicted gate control signal to the sensing circuit as the feedback voltage (providing feedback of d[n]Sc via 136). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Wang wherein the controller is configured to determine a predicted gate control signal based on the synchronous comparison result; and provide the predicted gate control signal to the sensing circuit as the feedback voltage, as taught by Maksimovic, because it can help provide a predictive control method with a shorter feedback loop which can help increase the response speed of the feedback control.
Regarding claim 16, Wang discloses (see Fig. 4A, , Fig. 4C, Fig. 6) wherein the gate control signal corresponds to a charge time for the power converter, (VGP and VGN correspond to the charge time of L of the boost power converter of Fig. 4A), wherein the charge time increases responsive to the synchronous comparison result having an asserted value (when VM is larger than VRAMP, VSW is asserted and the charge time increases, see Fig. 4C), and wherein the charge time decreases responsive to the synchronous comparison result having a deasserted value (when VM is smaller than VRAMP, VSW is deasserted and the charge time decreases, see Fig. 4C).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Maksimovic, and further in view of Kahn et al. (US Patent Application Publication US 2013/0207627 A1, hereinafter “Kahn”). Regarding claim 10, Wang does not disclose further comprising a gate driver coupled between the control circuitry and the power converter and configurable to: receive the gate control signal; and provide a gate drive signal based on the gate control signal to the power converter for controlling the power converter to switch the power from the power source to the load, wherein the gate drive signal controls a charge time of the power converter. However, Kahn teaches (see Fig. 1B) further comprising a gate driver (106, 110) coupled between the control circuitry (112) and the power converter (128) and configurable to: receive the gate control signal (signal output from 112 to 110 and 106); and provide a gate drive signal (signal output from 106 to 104 and from 110 to 108) based on the gate control signal to the power converter for controlling the power converter to switch the power from the power source (VDD) to the load (152), wherein the gate drive signal controls a charge time of the power converter (gate drive signals of 110 and 106 control charge time of 148 of the power converter). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Wang to further comprise a gate driver coupled between the control circuitry and the power converter and configurable to: receive the gate control signal; and provide a gate drive signal based on the gate control signal to the power converter for controlling the power converter to switch the power from the power source to the load, wherein the gate drive signal controls a charge time of the power converter, as taught by Kahn, because it can help provide the proper gate operating voltage level for the power switches of the power converter.
Allowable Subject Matter
Claims 17, 19, and 20 are allowable. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 17, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “determining a second predicted gate control signal; … while determining the gate control signal based on the comparison result, determining a second comparison result based on a comparison of the reference value to a feedback signal determined based on the second predicted gate control signal;…”.
Claims 2-6, 8, and 11, 12, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 2, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the sensing circuit is further configurable to provide a second comparison result based on a comparison between the reference voltage and the predicted gate control signal in parallel with the controller determining and providing the gate control signal.”. Regarding Claim 3, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the sensing circuit has a first sensing circuit input coupled to a first output of the controller, a second sensing circuit input configurable to receive the reference voltage; and a third sensing circuit input configurable to receive a voltage from a power supply, and wherein the sensing circuit includes: a second comparator having a first comparator input coupled to the second sensing circuit input, a second comparator input, and a comparator output; a variable resistor coupled between the third sensing circuit input and the first comparator input and having a control input coupled to the first sensing circuit input; and a current source coupled between the second comparator input and ground.”. Claims 4-6 are objected due to their dependency on claim 3. Regarding Claim 8, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the controller implements a state machine configurable to determine the gate control signal, wherein while the controller operates in a first state of the state machine to provide the gate control signal, the sensing circuit is configurable to determine a next comparison result in parallel for causing the controller to operate in a second state of the state machine to provide a subsequent gate control signal.”. Regarding Claim 11, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the sensing circuit includes: a comparator having a first comparator input configurable to receive the reference voltage indicative of a programmed voltage to be output by the power converter to the load, a second comparator input, and a comparator output; a variable resistor coupled between the power source and the second comparator input and having a control input coupled to a first output of the controller; and a current source coupled between the second comparator input and ground.”.
Claim 12 is objected due to its dependency on claim 11. Regarding Claim 14, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the controller implements a state machine configurable to determine the gate control signal, wherein while the controller operates in a first state to provide the gate control signal the sensing circuit is determining a next comparison result in parallel for causing the controller to operate in a second state to provide a subsequent gate control signal.”.
Claim 15 is objected due to its dependency on claim 14.
Response to Arguments
Applicant's arguments filed on 08/07/2025 have been fully considered but they are not persuasive. Regarding Claims 1 and 9, Applicant argued that “Wang and Maksimovic, taken alone or in combination, do not teach or suggest each limitation of claims 1 and 9.” in that “Claim 1, as amended, recites, "a synchronization circuit configurable to synchronize the comparison result based on a clock signal to provide a synchronous comparison result; and a controller configurable to, based on the clock signal: receive the synchronous comparison result; determine a predicted gate control signal based on the synchronous comparison result; determine a gate control signal based on the synchronous comparison result; provide the predicted gate control signal to the sensing circuit as the feedback voltage; and provide the gate control signal."” and “Claim 9, as amended, recites, "a synchronization circuit configurable to synchronize the comparison result based on a clock signal to provide a synchronous comparison result; and a controller configurable to: receive the synchronous comparison result; determine a predicted gate control signal based on the synchronous comparison result; determine the gate control signal based on the synchronous comparison result; provide the predicted gate control signal to the sensing circuit as the feedback voltage; and provide the gate control signal for controlling the power converter."”. However, Wang teaches (see Fig. 6) that the synchronization circuit (19A) and the controller (57) are both synchronized to the clock signal CLKINT, since signal VRAMP is synchronized to CLKINT and VSW is accordingly synchronized to CLKINT, thus VGN and VGP are synchronized and generated based on CLKINT. Therefore Applicant’s arguments are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838