DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 27, 30, and 36 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
The limitations of claims 27, 30, and 36 do not find written description support in the specification. The closest disclosure to these limitations is found in the equation in paragraph 0012 of the specification. However, this equation is explaining the total amount of time spent performing sweep sampling, not the multiple of the base timing interval used for a specific sweep.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7-9, 12-18, 26-29, and 33-36 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7 and 33 includes the phrase “a multiple N of a base timing interval”. It is unclear whether this is intended to be limited to an integer multiple of a base timing interval. On the one hand, these claims do not include “N being an integer greater than one”, which claim 22 includes. This implies that these claims are not limited to integer multiples. On the other hand, this phrase does not provide any practical limitation if all possible multiples are included, since the multiplier would just be the adjustable timing offset interval divided by the base timing interval. Claims 8, 9, 12-18, 26-29, and 34-36 are rejected based on their dependence on claims 7 or 33.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9, 12, 16-18, 22-26, 28, 29, and 31-35 are rejected under 35 U.S.C. 103 as being unpatentable over Manohararajah et al. (US 8,565,033) in view of Butt et al. (US 2007/0002642).
In regards to claim 7, Manohararajah teaches a method comprising:
asserting a plurality of first cycles of a non-clock memory signal (Figure 12 shows 2 cycles of the DQS signal) to a memory of a computing device (“The memory interface may be configured to send write data (DQ) and data strobe (DQS) signals to the first memory device before sending write DQ/DQS signals to the second memory device.”, Col. 2, lines 2-5), a rising edge and a falling edge of the non-clock memory signal for an individual cycle of the plurality of first cycles (“It may be desirable to align the rising edges of DQS with the rising edges of CLK and to align the falling edges of DQS with the falling edges of CLK.”, Col. 12, lines 62-64) offset from an edge of a memory clock signal asserted to the memory by a first adjustable timing offset (The dashed vertical lines in figure 12 show the different timing offsets), the first adjustable timing offset adjusted by an adjustable timing offset interval after assertion of one or more cycles of the plurality of first cycles to the memory (“At step 180, DQ/DQS phase may be swept to search for the first working phase (e.g., incrementing by quarter clock cycle phase steps).”, Col. 13, lines 3-5);
asserting a plurality of second cycles of the non-clock memory signal to the memory, a rising edge and a falling edge of the non-clock memory signal for an individual cycle of the plurality of second cycles offset from an edge of the memory clock signal asserted to the memory by a second adjustable timing offset, the second adjustable timing offset adjusted by a base timing interval after assertion of one or more second cycles of the plurality of second cycles to the memory (“At step 182, the first working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps (as an example) to find the left edge of window ∆Twv. Searching the limits of ∆Twv by adjusting phase and delay settings provides fine timing resolution for greater calibration accuracy.”, Col. 13, lines 9-13);
asserting a plurality of third cycles of the non-clock memory signal to the memory, a rising edge and a falling edge of the non-clock memory signal for an individual cycle of the plurality of third cycles offset from an edge of the memory clock signal asserted to the memory by a third adjustable timing offset, the third adjustable timing offset adjusted by the base timing interval after assertion of one or more third cycles of the plurality of third cycles to the memory (“At step 186, the last working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps to find the right edge of window ∆Twv. Data stream 196 may correspond to the last working delay setting (e.g., a setting for which DQS associated with d0 is aligned to the end time of the write data valid window).”, Col. 13, lines 20-23);
determining a timing offset between the non-clock memory signal and the memory clock signal based on the second adjustable timing offset at which the rising edge of the non-clock memory signal is determined to have been captured by the memory and the third adjustable timing offset at which the falling edge of the non-clock memory signal is determined to have been captured by the memory (“At step 188, DQ/DQS may be centered within ∆Twv (e.g., DQ/DQS is shifted according to an intermediate delay setting that is equal to the average of the first and last working delay settings) so that DQS associated with d0 is substantially aligned with the first rising clock edge of system CLK.”, Col. 13, lines 27-31; “It may be desirable to align the rising edges of DQS with the rising edges of CLK and to align the falling edges of DQS with the falling edges of CLK.”, Col. 12, lines 62-64); and
utilizing the timing offset while transmitting the non-clock memory signal to the memory during operation of the computing device (“Performing such types of calibration procedures may ensure that device 10 operates properly to exhibit reliable reads and writes (state 110).”, Col. 9, lines 27-29).
Manohararajah fails to teach that the adjustable timing offset interval is a multiple N of a base timing interval. Butt teaches that the adjustable timing offset interval is a multiple N of a base timing interval (“The stages 130, 131 and 132 are generally configured to provide three sets of delay adjustments (e.g., coarse, medium, and fine delays) with different granularities (e.g., 1, 1/4, and 1/32 of a 1× clock cycle).”, paragraph 0044). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Manohararajah with Butt such that the adjustable timing offset interval is a multiple N of a base timing interval in order to shorten the read training process.
In regards to claim 22, Manohararajah teaches one or more non-transitory computer-readable storage media storing computer-executable instructions that, when executed, cause one or more processor units of a computing device to:
assert a plurality of first cycles of a non-clock memory signal (Figure 12 shows 2 cycles of the DQS signal) to a memory of the computing device (“The memory interface may be configured to send write data (DQ) and data strobe (DQS) signals to the first memory device before sending write DQ/DQS signals to the second memory device.”, Col. 2, lines 2-5), a rising edge and a falling edge of the non-clock memory signal for an individual cycle of the plurality of first cycles (“It may be desirable to align the rising edges of DQS with the rising edges of CLK and to align the falling edges of DQS with the falling edges of CLK.”, Col. 12, lines 62-64) offset from an edge of a memory clock signal asserted to the memory by a first adjustable timing offset (The dashed vertical lines in figure 12 show the different timing offsets), the first adjustable timing offset adjusted by an adjustable timing offset interval after assertion of one or more cycles of the plurality of first cycles to the memory (“At step 180, DQ/DQS phase may be swept to search for the first working phase (e.g., incrementing by quarter clock cycle phase steps).”, Col. 13, lines 3-5);
asserting a plurality of second cycles of the non-clock memory signal to the memory, a rising edge and a falling edge of the non-clock memory signal for an individual cycle of the plurality of second cycles offset from an edge of the memory clock signal asserted to the memory by a second adjustable timing offset, the second adjustable timing offset adjusted by a base timing interval after assertion of one or more second cycles of the plurality of second cycles to the memory (“At step 182, the first working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps (as an example) to find the left edge of window ∆Twv. Searching the limits of ∆Twv by adjusting phase and delay settings provides fine timing resolution for greater calibration accuracy.”, Col. 13, lines 9-13);
asserting a plurality of third cycles of the non-clock memory signal to the memory, a rising edge and a falling edge of the non-clock memory signal for an individual cycle of the plurality of third cycles offset from an edge of the memory clock signal asserted to the memory by a third adjustable timing offset, the third adjustable timing offset adjusted by the base timing interval after assertion of one or more third cycles of the plurality of third cycles to the memory (“At step 186, the last working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps to find the right edge of window ∆Twv. Data stream 196 may correspond to the last working delay setting (e.g., a setting for which DQS associated with d0 is aligned to the end time of the write data valid window).”, Col. 13, lines 20-23);
determining a timing offset between the non-clock memory signal and the memory clock signal based on the second adjustable timing offset at which the rising edge of the non-clock memory signal is determined to have been captured by the memory and the third adjustable timing offset at which the falling edge of the non-clock memory signal is determined to have been captured by the memory (“At step 188, DQ/DQS may be centered within ∆Twv (e.g., DQ/DQS is shifted according to an intermediate delay setting that is equal to the average of the first and last working delay settings) so that DQS associated with d0 is substantially aligned with the first rising clock edge of system CLK.”, Col. 13, lines 27-31; “It may be desirable to align the rising edges of DQS with the rising edges of CLK and to align the falling edges of DQS with the falling edges of CLK.”, Col. 12, lines 62-64); and
utilizing the timing offset while transmitting the non-clock memory signal to the memory during operation of the computing device (“Performing such types of calibration procedures may ensure that device 10 operates properly to exhibit reliable reads and writes (state 110).”, Col. 9, lines 27-29).
Manohararajah fails to teach that the adjustable timing offset interval is N times a base timing interval, N being an integer greater than one. Butt teaches that the adjustable timing offset interval is N times a base timing interval, N being an integer greater than one (“The stages 130, 131 and 132 are generally configured to provide three sets of delay adjustments (e.g., coarse, medium, and fine delays) with different granularities (e.g., 1, 1/4, and 1/32 of a 1× clock cycle).”, paragraph 0044). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Manohararajah with Butt such that the adjustable timing offset interval is N times a base timing interval, N being an integer greater than one in order to shorten the read training process.
In regards to claim 33, Manohararajah teaches a computing system comprising:
a memory (“The memory interface circuitry may be used to interface with off-chip memory such as random-access memory (RAM).”, Col. 3, lines 55-57);
one or more processor units (“The integrated circuits may be digital signal processors, microprocessors, application specific integrated circuits, or other suitable integrated circuits.”, Col. 3, lines 57-60); and
one or more computer-readable storage media storing computer-executable instructions that, when executed by the one or more processor units (“Programmable elements 20 may be based on any suitable programmable technology, such as fuses, antifuses, electrically-programmable read-only-memory technology, random-access memory cells, mask-programmed elements, etc.”, Col. 4, lines 22-25), cause the computing system to:
(i) assert a plurality of first cycles of a non-clock memory signal (Figure 12 shows 2 cycles of the DQS signal) to the memory (“The memory interface may be configured to send write data (DQ) and data strobe (DQS) signals to the first memory device before sending write DQ/DQS signals to the second memory device.”, Col. 2, lines 2-5), a rising edge and a falling edge of the non-clock memory signal for an individual cycle (“It may be desirable to align the rising edges of DQS with the rising edges of CLK and to align the falling edges of DQS with the falling edges of CLK.”, Col. 12, lines 62-64) offset from an edge of a memory clock signal asserted to the memory by a first adjustable timing offset (The dashed vertical lines in figure 12 show the different timing offsets), the first adjustable timing offset being adjusted through a plurality of values, successive values of the first adjustable timing offset separated by an adjustable timing offset interval (“At step 180, DQ/DQS phase may be swept to search for the first working phase (e.g., incrementing by quarter clock cycle phase steps).”, Col. 13, lines 3-5);
(ii) determine, based on values of the non-clock memory signal captured by the memory during the plurality of first cycles, (a) a rising edge transition occurring between successive values captured at a first one of the plurality of values of the first adjustable timing offset and a second one of the plurality of values of the first adjustable timing offset (“At step 184, DQ/DQS phase may be swept to search for the last working phase.”, Col. 13, lines 17-18), and (b) a falling edge transition occurring between successive values captured at a third one of the plurality of values of the first adjustable timing offset and a fourth one of the plurality of values of the first adjustable timing offset (“At step 180, DQ/DQS phase may be swept to search for the first working phase (e.g., incrementing by quarter clock cycle phase steps).”, Col. 13, lines 3-5);
(iii) assert a plurality of second cycles of the non-clock memory signal to the memory with a second adjustable timing offset adjusted by the base timing interval, the second adjustable timing offset starting at the first one of the plurality of values of the first adjustable timing offset and being adjusted by the base timing interval through timing offsets between the first one and the second one of the plurality of values of the first adjustable timing offset, to determine a second adjustable timing offset at which the rising edge of the non-clock memory signal is determined to have been captured by the memory (“At step 186, the last working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps to find the right edge of window ∆Twv. Data stream 196 may correspond to the last working delay setting (e.g., a setting for which DQS associated with d0 is aligned to the end time of the write data valid window).”, Col. 13, lines 20-26);
(iv) assert a plurality of third cycles of the non-clock memory signal to the memory with a third adjustable timing offset adjusted by the base timing interval, the third adjustable timing offset starting at the third one of the plurality of values of the first adjustable timing offset and being adjusted by the base timing interval through timing offsets between the third one and the fourth one of the plurality of values of the first adjustable timing offset, to determine a third adjustable timing offset at which the falling edge of the non-clock memory signal is determined to have been captured by the memory (“At step 182, the first working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps (as an example) to find the left edge of window ∆Twv. Searching the limits of ∆Twv by adjusting phase and delay settings provides fine timing resolution for greater calibration accuracy.”, Col. 13, lines 9-13);
(v) determine a timing offset between the non-clock memory signal and the memory clock signal based on the second adjustable timing offset at which the rising edge of the non-clock memory signal is determined to have been captured by the memory and the third adjustable timing offset at which the falling edge of the non-clock memory signal is determined to have been captured by the memory (“At step 188, DQ/DQS may be centered within ∆Twv (e.g., DQ/DQS is shifted according to an intermediate delay setting that is equal to the average of the first and last working delay settings) so that DQS associated with d0 is substantially aligned with the first rising clock edge of system CLK.”, Col. 13, lines 27-31); and
(vi) utilize the timing offset by asserting the non-clock memory signal to the memory during operation of the computing system with the rising edge and the falling edge of the non-clock memory signal offset from an edge of the memory clock signal by the timing offset (“Performing such types of calibration procedures may ensure that device 10 operates properly to exhibit reliable reads and writes (state 110).”, Col. 9, lines 27-29).
Manohararajah fails to teach that the adjustable timing offset interval is a multiple N of a base timing interval. Butt teaches that the adjustable timing offset interval is a multiple N of a base timing interval (“The stages 130, 131 and 132 are generally configured to provide three sets of delay adjustments (e.g., coarse, medium, and fine delays) with different granularities (e.g., 1, 1/4, and 1/32 of a 1× clock cycle).”, paragraph 0044). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Manohararajah with Butt such that the adjustable timing offset interval is a multiple N of a base timing interval in order to shorten the read training process.
In regards to claims 8 and 23, Manohararajah further teaches determining as a starting offset time for the second adjustable timing offset, the first adjustable timing offset at which the rising edge or the falling edge of the non-clock memory signal is determined to have been captured by the memory (“At step 186, the last working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps to find the right edge of window ∆Twv.”, Col. 13, lines 20-23); and
determining as a starting offset time for the third adjustable timing offset, the first adjustable timing offset at which the rising edge or the falling edge of the non-clock memory signal not used to determine the starting offset time for the second adjustable timing offset is determined to have been captured by the memory (“At step 182, the first working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps (as an example) to find the left edge of window ∆Twv.”, Col. 13, lines 9-11).
In regards to claims 9 and 24, Manohararajah further teaches that the determining the timing offset occurs during a power-on startup sequence of the computing device (“Sequencer 30 arranged using the exemplary configuration of FIG. 2 may serve to calibrate the interface between memory module 22 and circuit 26 at the startup of device 10 (e.g., by sending control signals over line 44 to make timing adjustments in interface circuit 26).”, Col. 5, lines 40-45) and the utilizing the timing offset occurs after the power-on startup sequence (“Performing such types of calibration procedures may ensure that device 10 operates properly to exhibit reliable reads and writes (state 110).”, Col. 9, lines 27-29).
In regards to claim 12, Butt further teaches determining the base timing interval by dividing a period of a reference signal by a number of divisions for the reference signal (“The stages 130, 131 and 132 are generally configured to provide three sets of delay adjustments (e.g., coarse, medium, and fine delays) with different granularities (e.g., 1, 1/4, and 1/32 of a 1× clock cycle).”, paragraph 0044).
In regards to claims 16 and 25, Manohararajah further teaches that the timing offset is an average of the second adjustable timing offset at which the rising edge of the non-clock memory signal is determined to have been captured by the memory and the third adjustable timing offset at which the falling edge of the non-clock memory signal is determined to have been captured by the memory (“At step 188, DQ/DQS may be centered within ∆Twv (e.g., DQ/DQS is shifted according to an intermediate delay setting that is equal to the average of the first and last working delay settings) so that DQS associated with d0 is substantially aligned with the first rising clock edge of system CLK.”, Col. 13, lines 27-31).
In regards to claim 17, Manohararajah further teaches that the non-clock memory signal is a first non-clock memory signal, and the method of claim 7 is performed for one or more second non-clock memory signals (“In general, the operation of each memory group is somewhat independent, so memory module 22 generates a DQS signal for each of the memory groups. The DQS signals for the different memory groups are generally not phase aligned with each other (e.g., skew may be present among the DQS signals). For example, although the DQS signal for a first memory group is edge-aligned with the DQ signals in the first memory group, the DQS signal for the first memory group and the seventh memory group (as an example) need not be in phase with each other.”, Col. 6, lines 30-39).
In regards to claim 18, Manohararajah further teaches that the adjustable timing offset interval is a first adjustable timing offset interval for the first non-clock memory signal and a second adjustable timing offset interval is associated with at least one of the one or more second non-clock memory signals, the first adjustable timing offset interval different than the second adjustable timing offset interval (“In general, the operation of each memory group is somewhat independent, so memory module 22 generates a DQS signal for each of the memory groups. The DQS signals for the different memory groups are generally not phase aligned with each other (e.g., skew may be present among the DQS signals). For example, although the DQS signal for a first memory group is edge-aligned with the DQ signals in the first memory group, the DQS signal for the first memory group and the seventh memory group (as an example) need not be in phase with each other.”, Col. 6, lines 30-39).
In regards to claim 26, Butt further teaches that N is in a range of 8 to 16 (“The stages 130, 131 and 132 are generally configured to provide three sets of delay adjustments (e.g., coarse, medium, and fine delays) with different granularities (e.g., 1, 1/4, and 1/32 of a 1× clock cycle).”, paragraph 0044, 1/4 is a multiple of 8 times 1/32).
In regards to claims 28, 31, and 35, Manohararajah further teaches that adjusting the first adjustable timing offset comprises stepping the first adjustable timing offset by the adjustable timing offset interval through a plurality of values over a range corresponding to two periods of the memory clock signal (Figure 12 shows steps 1 and 3 sweeping over more than two CLK periods).
In regards to claims 29, 32, and 34, Manohararajah further teaches that, for the plurality of second cycles, the second adjustable timing offset is adjusted by the base timing interval for N-1 successive intervals, and wherein, for the plurality of third cycles, the third adjustable timing offset is adjusted by the base timing interval for N-1 successive intervals (“At step 186, the last working phase setting is decreased by one, and DQ/DQS is increased by 50 ps steps to find the right edge of window ∆Twv.”, Col. 13, lines 20-23, N-1 would correspond to the last step before the previously working phase setting).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Manohararajah et al. (US 8,565,033) in view of Butt et al. (US 2007/0002642) and Mayer et al. (US 2020/0065185).
In regards to claim 13, Manohararajah in view of Butt teaches claim 12. Manohararajah in view of Butt fails to teach that the reference signal and/or the number of divisions for the reference signal is specified in computer-executable instructions executable by one or more processing units of the computing device, the computer-executable instructions to be executed during a power-on startup sequence of the computing device. Mayer teaches that the reference signal and/or the number of divisions for the reference signal is specified in computer-executable instructions executable by one or more processing units of the computing device (“In cases when there is no checksum data to be provided to the external memory controller 105, the EDC line may alternatively be used to communicate a timing signal (e.g., a clock-like pattern) to the external memory controller 105 for tracking of the timing of the memory device 110. Such clock-like patterns may comprise a hold pattern (e.g., an EDC hold pattern) driven by EDC signaling and defined by one or more mode register settings (e.g., a quantity of bits in a mode register may define the hold pattern).”, paragraph 0054), the computer-executable instructions to be executed during a power-on startup sequence of the computing device (“In some examples, the predefined timing offset may be stored in BIOS, and may be loaded into the mode register upon system startup.”, paragraph 0108; “The BIOS component 125 may be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system 100.”, paragraph 0027) in order “to minimize crosstalk” (paragraph 0108). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Manohararajah with Butt and Mayer such that the reference signal and/or the number of divisions for the reference signal is specified in computer-executable instructions executable by one or more processing units of the computing device, the computer-executable instructions to be executed during a power-on startup sequence of the computing device in order “to minimize crosstalk” (id.).
In regards to claim 14, Manohararajah further teaches that the adjustable timing offset interval is specified during a power-on startup sequence of the computing device (“The memory interface circuitry may be calibrated at the startup of an integrated circuit to ensure reliable read and write operations.”, Col. 2, lines 6-8). Manohararajah in view of Butt fails to teach that the adjustable timing offset interval is specified in computer-executable instructions executable by one or more processing units of the computing device, the computer-executable instructions to be executed during a power-on startup sequence of the computing device. Mayer teaches that the adjustable timing offset interval is specified in computer-executable instructions executable by one or more processing units of the computing device, the computer-executable instructions to be executed during a power-on startup sequence of the computing device (“In some examples, the predefined timing offset may be stored in BIOS, and may be loaded into the mode register upon system startup.”, paragraph 0108; “The BIOS component 125 may be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system 100.”, paragraph 0027) in order “to minimize crosstalk” (paragraph 0108). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Manohararajah with Butt and Mayer such that the adjustable timing offset interval is specified in computer-executable instructions executable by one or more processing units of the computing device, the computer-executable instructions to be executed during a power-on startup sequence of the computing device in order “to minimize crosstalk” (id.).
In regards to claim 15, Manohararajah in view of Butt teaches claim 7. Manohararajah in view of Butt fails to teach that the adjustable timing offset interval is user-defined. Mayer teaches that the adjustable timing offset interval is user-defined (“In some examples, the predefined timing offset may be stored in BIOS, and may be loaded into the mode register upon system startup.”, paragraph 0108, the user in this context is the processor) in order “to minimize crosstalk” (paragraph 0108). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Manohararajah with Butt and Mayer such that the adjustable timing offset interval is user-defined in order “to minimize crosstalk” (id.).
Response to Arguments
Applicant’s arguments, see page 12-13, filed 27 February 2026, with respect to the objections and 101 rejections have been fully considered and are persuasive. The corresponding objections and 101 rejections have been withdrawn.
Applicant’s arguments, see pages 13-15, filed 27 February 2026, with respect to the prior art rejections of the claims have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection is made in view of Butt.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (US 2020/0143854) teaches coarse and fine training of data signal delay.
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 23 March 2026