DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 31 March 2026 have been fully considered but they are not persuasive. Applicant’s arguments with respect to the prior art have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 12-16, and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Boyd (U.S. Publication 2020/0175646) in view of Das (U.S. Publication 2020/0293858).
As to claim 1, Boyd discloses a non-transitory computer-readable medium comprising instructions (p. 17, section 0204) to cause at least one processor circuit (p. 2-3, section 0043; the processing system can be a GPU) to at least:
retrieve, from a memory device, pixel data of an image corresponding to a kernel grid size into one or more registers (p. 12, sections 0118-0120; p. 13, section 0130; the requested/retrieved pixel block of a particular size to be operated on, reading on kernel grid size, is sent to registers after being retrieved from block data memories), the retrieved pixel data including neighboring pixel data relative to the target pixel region (fig. 19; fig. 23; p. 17, sections 0158-0164; a target region overlaps 4 blocks and so at least the 4 blocks, including pixel data in the region and pixel data neighboring the region are fetched for the kernel at once);
and process the retrieved pixel data based on the filter kernel to determine output pixel data corresponding to the target pixel region (fig. 19; fig. 23; p. 14, section 0140; the filter kernel, for example, a warp filter kernel, processes a tile for output image pixel data in a target region, then moves on to the next, neighboring, tile; neighboring tiles would correspond to pre-fetched pixel data from adjacent blocks, and would be processed based on the position of already retrieved pixel data for previous kernel grids).
Boyd does not disclose, but Das discloses determining a kernel grid size based on a pixel region size and a filter kernel size, the pixel region size corresponding to a size of a target pixel region of an image, the filter kernel size corresponding to a size of a filter kernel (p. 8, section 0086; the fetched tile grid to be operated on by the filter kernel, reading on a kernel grid, is sized based on the target pixel region size T plus the kernel size S or R in each dimension, minus 1). The motivation for this is to fetch pixels that enable fewer unwanted computations and decrease processing (p. 3, section 0045). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Boyd to determine a kernel grid size based on a pixel region size and a filter kernel size, the pixel region size corresponding to a size of a target pixel region of an image, the filter kernel size corresponding to a size of a filter kernel in order to fetch pixels that enable fewer unwanted computations and decrease processing as taught by Das.
As to claim 2, Boyd discloses wherein to process the retrieved pixel data, the instructions are to cause one or more of the at least one processor circuit to convolve the kernel weight matrix over the retrieved pixel data (p. 16, section 0166-p. 17, section 0199; a kernel weight matrix, implementing a bicubic or bilinear filter, is applied to/convolved with the retrieved region of pixels).
As to claim 4, Boyd discloses wherein to process the retrieved pixel data the instructions are to cause one or more of the at least one processor circuit to perform convolution by sliding a kernel weight matrix over the retrieved pixel data, the kernel weight matrix based on the filter kernel (fig. 19; fig. 23; p. 14, sections 0137-0140; p. 16, section 0166-p. 17, section 0199; the filter kernel, for example, a warp filter kernel with a weight/coefficient matrix defining a bicubic or bilinear function, processes a tile then moves on to the next, neighboring, tile, reading on a slide to that next tile).
As to claim 5, Boyd discloses wherein the target pixel region includes multiple pixels (fig. 23, an 8x8 target pixel region is shown).
As to claim 6, Boyd discloses wherein the target pixel region includes an M×N pixel region, where M≥1 and/or N≥1 (fig. 23, an 8x8 target pixel region is shown, corresponding to M=N=8).
As to claim 12, see the rejection to claim 1.
As to claim 13, see the rejection to claim 2.
As to claim 15, see the rejection to claim 4.
As to claim 16, see the rejection to claim 6.
As to claim 21, see the rejection to claim 1.
As to claim 22, see the rejection to claim 2.
As to claim 23, see the rejection to claim 4.
As to claim 24, see the rejection to claim 6.
As to claim 26, Boyd does not explicitly disclose, but Das discloses wherein a dimension of the kernel grid size is one less than a sum of a dimension of the pixel region size and a dimension of the filter kernel size (p. 8, section 0086; the fetched tile grid to be operated on by the filter kernel, reading on a kernel grid, is sized to be the target pixel region size T plus the kernel size S or R in each dimension, minus 1). Motivation for the combination is given in the rejection to claim 1.
As to claim 27, see the rejection to claim 26.
As to claim 28, see the rejection to claim 26.
Claims 7-10, 17-20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Boyd in view of Matveev (U.S. Publication 2021/0042624).
As to claim 7, Boyd does not disclose, but Matveev discloses wherein the instructions are to cause one or more of the at least one processor circuit is to execute in Single Instruction Multiple Threads (SIMT) mode, Single Instruction Multiple Data (SIMD) mode, or SIMT+SIMD execution mode (p. 2, section 0024; p. 11, sections 0147-0148; a filter kernel is applied using an SIMD mode). The motivation for this is to enable performing of parallel computation between respective entries of at least two multidimensional tensors. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Boyd and Das to execute in Single Instruction Multiple Threads (SIMT) mode, Single Instruction Multiple Data (SIMD) mode, or SIMT+SIMD execution mode in order to enable performing of parallel computation between respective entries of at least two multidimensional tensors as taught by Matveev.
As to claim 8, Boyd does not disclose, but Matveev discloses wherein the kernel grid size is based on occupancy of the one or more registers (p. 12, section 0161; p. 12, section 0166; p. 13, sections 0170-0171; the number of elements in the kernel grid and the bit-length of weight elements in the grid, together reading on the kernel grid size, are determined based on how many entries can fit in/occupy the register as well as how many bits can fit in/occupy each entry). The motivation for this is to take advantage of modern instruction sets and boost executions of neural networks (p. 1, sections 0007-0008). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Boyd and Das to have a kernel grid size based on occupancy of the one or more registers in order to take advantage of modern instruction sets and boost executions of neural networks as taught by Matveev.
As to claim 9, Boyd does not disclose, but Matveev discloses a medium wherein the instructions are to cause one or more of the at least one processor circuit to: determine a range of kernel grid sizes and a range of target pixel region sizes that are within a range of occupancy of the one or more registers and select the kernel grid size and the target pixel region to be within the range of occupancy of the one or more registers (p. 12, section 0157; p. 12, section 0161; p. 12, section 0166; p. 13, sections 0170-0171; a range smaller than a total range of the kernel grid size is determined by setting it to equal the maximum capacity/occupancy of the registers and, using sparsification, the values in the range are determined; each kernel value corresponds to a pixel with the target region when applied, and so determination and selection of largest kernel grid size to fit a range would also necessarily determine a size for the pixel target region). Motivation for the combination is given in the rejection to claim 8.
As to claim 10, Boyd does not disclose, but Matveev discloses a medium wherein the instructions are to cause one or more processors of the at least one processor circuit to: determine a range of kernel grid sizes and a range of target pixel region sizes that are within a range of occupancy of two of the one or more registers and select the kernel grid size and the target pixel region to be within the range of occupancy of the two of the one or more registers (p. 1-2, section 0011; p. 8, section 0109; p. 12, section 0157; p. 12, section 0161; p. 12, section 0166; p. 13, sections 0170-0171; a range smaller than a total range of the kernel grid size is determined by setting it to equal the maximum capacity/occupancy of the registers and, using sparsification, the values in the range are determined; each kernel value corresponds to a pixel with the target region when applied, and so determination and selection of largest kernel grid size to fit a range would also necessarily determine a size for the pixel target region; the process is done with respect to “vector registers” necessitating at least two registers as part of the steps above). Motivation for the combination is given in the rejection to claim 8.
As to claim 17, see the rejection to claim 7.
As to claim 18, see the rejection to claim 9.
As to claim 19, see the rejection to claim 10.
As to claim 20, Boyd does not disclose, but Matveev discloses wherein the kernel grid size is based on occupancy of the at least one register (p. 12, section 0161; section 0166; p. 13, sections 0170-0171; the number of elements in the kernel grid and the bit-length of weight elements in the grid, together reading on the kernel grid size, are determined based on how many entries can fit in/occupy the register as well as how many bits can fit in/occupy each entry). Motivation for the combination is given in the rejection to claim 8.
As to claim 25, see the rejection to claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON M RICHER whose telephone number is (571)272-7790. The examiner can normally be reached 9AM-5PM.
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/AARON M RICHER/Primary Examiner, Art Unit 2617
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