DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 12-16, and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boyd (U.S. Publication 2020/0175646).
As to claim 1, Boyd discloses a non-transitory computer-readable medium comprising instructions stored thereon (p. 17, section 0204), that if executed by one or more processors of a graphics processing unit (GPU) (p. 2-3, section 0043; the processing system can be a GPU), cause the one or more processors to:
retrieve, from a memory device, pixel data of a kernel grid into one or more registers of the GPU (p. 12, section 0118; p. 13, section 0130; the requested/retrieved pixel block is sent to registers after being retrieved from block data memories) to load pixel data neighboring a target pixel region once into the one or more registers (fig. 19; fig. 23; p. 17, sections 0158-0164; a target region overlaps 4 blocks and so at least the 4 blocks, including pixel data in the region and pixel data neighboring the region are fetched for the kernel at once)
and process the neighboring pixel data based on the retrieved pixel data of the kernel grid from the one or more registers (fig. 19; fig. 23; p. 14, section 0140; the filter kernel, for example, a warp filter kernel, processes a tile then moves on to the next, neighboring, tile; neighboring tiles would correspond to pre-fetched pixel data from adjacent blocks, and would be processed based on the position of already retrieved pixel data for previous kernel grids).
As to claim 2, Boyd discloses wherein the process the neighboring pixel data based on the retrieved pixel data of the kernel grid from the one or more registers comprises convolve a kernel weight matrix over the retrieved pixel data of the kernel grid (p. 16, section 0166-p. 17, section 0199; a kernel weight matrix, implementing a bicubic or bilinear filter, is applied to/convolved with the retrieved region of pixels).
As to claim 3, Boyd discloses wherein the process the neighboring pixel data based on the retrieved pixel data of the kernel grid from the one or more registers comprises perform image processing on the neighboring pixels (fig. 19; fig. 23; p. 14, sections 0137-0140; p. 16, section 0166-p. 17, section 0199; the filter kernel, for example, a warp filter kernel with a weight/coefficient matrix defining a bicubic or bilinear function, processes a tile then moves on to the next, neighboring, tile; the filtering can include distortion correction, which is an image processing operation).
As to claim 4, Boyd discloses wherein the process the neighboring pixel data based on the retrieved pixel data of the kernel grid from the one or more registers comprises perform convolution on pixels of a kernel weight matrix of the kernel grid by a sliding kernel weight matrix (fig. 19; fig. 23; p. 14, sections 0137-0140; p. 16, section 0166-p. 17, section 0199; the filter kernel, for example, a warp filter kernel with a weight/coefficient matrix defining a bicubic or bilinear function, processes a tile then moves on to the next, neighboring, tile, reading on a slide to that next tile).
As to claim 5, Boyd discloses wherein the target pixel region comprises multiple pixels (fig. 23, an 8x8 target pixel region is shown).
As to claim 6, Boyd discloses wherein the target pixel region comprises an M×N pixel region, where M≥1 and/or N≥1 (fig. 23, an 8x8 target pixel region is shown, corresponding to M=N=8).
As to claim 12, see the rejection to claim 1.
As to claim 13, see the rejection to claim 2.
As to claim 14, see the rejection to claim 3.
As to claim 15, see the rejection to claim 4.
As to claim 16, see the rejection to claim 6.
As to claim 21, see the rejection to claim 1.
As to claim 22, see the rejection to claim 2.
As to claim 23, see the rejection to claim 4.
As to claim 24, see the rejection to claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-11, 17-20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Boyd in view of Matveev (U.S. Publication 2021/0042624).
As to claim 7, Boyd does not disclose, but Matveev discloses wherein the one or more processors is to execute in Single Instruction Multiple Threads (SIMT) mode, Single Instruction Multiple Data (SIMD) mode, or SIMT+SIMD execution mode (p. 2, section 0024; p. 11, sections 0147-0148; a filter kernel is applied using an SIMD mode). The motivation for this is to enable performing of parallel computation between respective entries of at least two multidimensional tensors. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Boyd to execute in Single Instruction Multiple Threads (SIMT) mode, Single Instruction Multiple Data (SIMD) mode, or SIMT+SIMD execution mode in order to enable performing of parallel computation between respective entries of at least two multidimensional tensors as taught by Matveev.
As to claim 8, Boyd does not disclose, but Matveev discloses wherein a size of the kernel grid is based on occupancy of the one or more registers (p. 12, section 0161; p. 12, section 0166; p. 13, sections 0170-0171; the number of elements in the kernel grid and the bit-length of weight elements in the grid, together reading on the kernel grid size, are determined based on how many entries can fit in/occupy the register as well as how many bits can fit in/occupy each entry). The motivation for this is to take advantage of modern instruction sets and boost executions of neural networks (p. 1, sections 0007-0008). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Boyd to have a size of the kernel grid based on occupancy of the one or more registers in order to take advantage of modern instruction sets and boost executions of neural networks as taught by Matveev.
As to claim 9, Boyd does not disclose, but Matveev discloses a medium comprising instructions stored thereon, that if executed by one or more processors of the GPU, cause the one or more processors to: determine a range of kernel grid sizes and a range of target pixel region sizes that are within a range of occupancy of the one or more registers and select a largest kernel grid size and a largest target pixel region that is within the range of occupancy of the one or more registers (p. 12, section 0157; p. 12, section 0161; p. 12, section 0166; p. 13, sections 0170-0171; a range smaller than a total range of the kernel grid size is determined by setting it to equal the maximum capacity/occupancy of the registers and, using sparsification, the values in the range are determined; each kernel value corresponds to a pixel with the target region when applied, and so determination and selection of largest kernel grid size to fit a range would also necessarily determine a size for the pixel target region). Motivation for the combination is given in the rejection to claim 8.
As to claim 10, Boyd does not disclose, but Matveev discloses a medium comprising instructions stored thereon, that if executed by one or more processors of the GPU, cause the one or more processors to: determine a range of kernel grid sizes and a range of target pixel region sizes that are within a range of occupancy of two of the one or more registers and select a largest kernel grid size and a largest target pixel region that is within the range of occupancy of the two of the one or more registers (p. 1-2, section 0011; p. 8, section 0109; p. 12, section 0157; p. 12, section 0161; p. 12, section 0166; p. 13, sections 0170-0171; a range smaller than a total range of the kernel grid size is determined by setting it to equal the maximum capacity/occupancy of the registers and, using sparsification, the values in the range are determined; each kernel value corresponds to a pixel with the target region when applied, and so determination and selection of largest kernel grid size to fit a range would also necessarily determine a size for the pixel target region; the process is done with respect to “vector registers” necessitating at least two registers as part of the steps above). Motivation for the combination is given in the rejection to claim 8.
As to claim 11, Boyd does not disclose, but Matveev discloses a medium comprising instructions stored thereon, that if executed by one or more processors of the GPU, cause the one or more processors to: select a size of the kernel grid to load into the one or more registers based on occupancy of the at least one register by the kernel grid (p. 12, section 0161; section 0166; p. 13, sections 0170-0171; the number of elements in the kernel grid and the bit-length of weight elements in the grid, together reading on the kernel grid size, are determined based on how many entries can fit in/occupy the register as well as how many bits can fit in/occupy each entry). Motivation for the combination is given in the rejection to claim 8.
As to claim 17, see the rejection to claim 7.
As to claim 18, see the rejection to claim 9.
As to claim 19, see the rejection to claim 10.
As to claim 20, see the rejection to claim 11.
As to claim 25, see the rejection to claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON M RICHER whose telephone number is (571)272-7790. The examiner can normally be reached 9AM-5PM.
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/AARON M RICHER/Primary Examiner, Art Unit 2617