DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 11 and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The Specification discloses in [0302]-[0303], “... the method includes identifying one or more bottlenecks in the chain of accelerators... identifying the bottleneck(s) may include collecting and analyzing operational data for the chain of accelerators to help identify the bottleneck(s)... if the bottleneck is caused by a given set of accelerator resources, then identifying the changes may include identifying one or more sets of accelerator resources to supplant or replace the given set of accelerator resources.” Nowhere in the Specification is it disclosed that at least one of the first and second accelerators identifies a bottleneck associated with data flow in the chained accelerator operation and that at least one of the first and second accelerators makes changes to address the bottleneck, as claimed in the amended portions of claims 1, 11 and 19. The Specification discloses that the bottleneck is identified and that changes are identified to address the bottleneck. Therefore, these amended claim limitations of claims 1, 11 and 19 are considered to be NEW MATTER.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 11, 19; 5, 8, 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer et al. U.S. Patent No. 11,281,602 in view of Paltashev et al U.S. Patent No. 10,664,942.
Re: claims 1 and 11 (which are rejected under the same rationale) (which are rejected under the same rationale), Iyer teaches
1. (Currently Amended) An apparatus comprising: a first accelerator having support for a chained accelerator operation, the first accelerator to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data; (“Fig. 7 illustrates a method for chaining operations with multiple SDXI hardware devices... In the present example, data from a source buffer 722 of memory 720 is compressed by a compress engine 712 of SDXI hardware device 710, stored to an intermediate buffer 724 of the memory, encrypted by an encrypt engine 717 of the SDZI hardware device 715 and returned to a destination buffer 726 of the memory. The chained operations are invoked when a first SDXI command 705 is provided to SDXI hardware device 710 and a second SDXI command 707 is provided to SDXI hardware device 715... SDXI command 707 includes a dependency field that indicates to SDXI hardware device 715 that the operation to be performed on the data from intermediate buffer 724 is dependent upon the prior completion of the operation performed by SDXI hardware device 710.”; Iyer, col. 11, lines 1- 13, lines 32-36, Fig. 7)
Fig. 7 illustrates chaining operations with multiple SDXI hardware devices (accelerators), that includes SDXI 710 (first accelerator having support for a chained accelerator operation) and SDXI 715 (second accelerator having support for the chained accelerator operation). SDXI 710 (first accelerator) accesses data (input data) from a source buffer 722 (source memory location) of memory 720 (in system memory), compresses the data (process the input data) and stores the compressed data to an intermediate buffer 724 (generate first intermediate data).
and a second accelerator having support for the chained accelerator operation, the second accelerator to be controlled as part of the chained accelerator operation to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data, “Fig. 7 illustrates a method for chaining operations with multiple SDXI hardware devices... In the present example, data from a source buffer 722 of memory 720 is compressed by a compress engine 712 of SDXI hardware device 710, stored to an intermediate buffer 724 of the memory, encrypted by an encrypt engine 717 of the SDZI hardware device 715 and returned to a destination buffer 726 of the memory. The chained operations are invoked when a first SDXI command 705 is provided to SDXI hardware device 710 and a second SDXI command 707 is provided to SDXI hardware device 715... SDXI command 707 includes a dependency field that indicates to SDXI hardware device 715 that the operation to be performed on the data from intermediate buffer 724 is dependent upon the prior completion of the operation performed by SDXI hardware device 710.”; Iyer, col. 11, lines 1- 13, lines 32-36, Fig. 7)
Fig. 7 also illustrates SDXI 715 (second accelerator) receives the compressed data (receive the first intermediate data) from the intermediate buffer 724, encrypts the compressed data (process the first intermediate data), and store the encrypted data in the destination buffer 726 (and generate additional data).
(“In a particular embodiment, SDXI hardware devices 710 and 715 share a common data communication interface, whereby SDXI hardware devices 710 and 715 share a common data communication interface, whereby SDXI hardware device 710 operates to provide the compressed data directly to SDXI hardware device 715, without storing the data to intermediate buffer 724.”; Iyer, col. 12, lines 2-7)
Fig. 7 also illustrates that the chaining operations of the SDXI 710 (first accelerator) and SDXI 7156 (second accelerator) can be performed directly without storing the data to intermediate buffer 724 (the second accelerator to be controlled as part of the chained accelerator operation to receive the first intermediate data, without the first intermediate data having been sent to the system memory).
Iyer is silent regarding at least one of the first and second accelerators is to identify a bottleneck associated with data flow in the chained accelerator operation and is to make one or more changes to address the bottleneck, however, Paltashev teaches
wherein at least one of the first and second accelerators is to identify a bottleneck associated with data flow in the chained accelerator operation and is to make one or more changes to address the bottleneck. (“For example, emulations of the fixed function hardware blocks 641-645 can be instantiated in shader firmware in response to detecting bottlenecks in the fixed function hardware blocks 641-645. The shader firmware emulations of the fixed function hardware blocks 641-645 can then be used to perform the requested operations instead of using the actual hardware, thereby alleviating the bottlenecks in the fixed function hardware blocks 641-645.”; Paltashev, col. 14, line 62-col. 15, line 3)
When a bottleneck is detected (identify... a bottleneck associated with data flow in the chained accelerator operation) in the fixed function hardware blocks (at least one of the first and second accelerators), the shader firmware emulations of the fixed function hardware blocks (at least one of the first and second accelerators) are used to perform the requested operations (make... one or more changes to address the bottleneck) instead of using the actual hardware. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of at least one of the first and second accelerators is to identify a bottleneck associated with data flow in the chained accelerator operation and is to make one or more changes to address the bottleneck, in order to provide additional processing resources to unclog the bottleneck, as taught by Paltashev (col. 5, lines 19-25).
Claim 19 is a medium analogous to the apparatus of claim 1, is similar in scope and is rejected under the same rationale. Claim 19 has additional limitations. Re: claim 19, Iyer teaches
19. (Currently Amended) At least one non-transitory machine-readable storage medium, the at least one non-transitory machine-readable storage medium storing instructions that, if performed by a machine, are to cause the machine to perform operations comprising to: (“... the information handling system 800 can include processing resources for executing machine-executable code... Information handling system 800 can also include one or more computer-readable medium for storing machine readable code, such as software or data.”; Iyer, col. 13, Fig. 8)
Fig. 8 illustrates an information handling system that includes a computer readable medium storing machine readable code, executed by processing resources.
Iyer is silent regarding identify, with at least one of the first and second accelerators, a bottleneck associated with data flow in the chained accelerator operation; make with at least one of the first and second accelerators, one or more changes to address the bottleneck, however, Paltashev teaches
... identify, with at least one of the first and second accelerators, a bottleneck associated with data flow in the chained accelerator operation; make, with at least one of the first and second accelerators, one or more changes to address the bottleneck. (“For example, emulations of the fixed function hardware blocks 641-645 can be instantiated in shader firmware in response to detecting bottlenecks in the fixed function hardware blocks 641-645. The shader firmware emulations of the fixed function hardware blocks 641-645 can then be used to perform the requested operations instead of using the actual hardware, thereby alleviating the bottlenecks in the fixed function hardware blocks 641-645.”; Paltashev, col. 14, line 62-col. 15, line 3)
When a bottleneck is detected (identify... a bottleneck associated with data flow in the chained accelerator operation) in the fixed function hardware blocks (at least one of the first and second accelerators), the shader firmware emulations of the fixed function hardware blocks (at least one of the first and second accelerators) are used to perform the requested operations (make.. one or more changes to address the bottleneck) instead of using the actual hardware. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of identify, with at least one of the first and second accelerators, a bottleneck associated with data flow in the chained accelerator operation; make with at least one of the first and second accelerators, one or more changes to address the bottleneck, in order to provide additional processing resources to unclog the bottleneck, as taught by Paltashev (col. 5, lines 19-25).
Re: claims 5 and 15 (which are rejected under the same rationale), Iyer and Paltashev teach
5. (Original) The apparatus of claim 1, wherein the additional data is output data and the second accelerator is to store the output data to a destination memory location in the system memory. (“Fig. 7 illustrates a method for chaining operations with multiple SDXI hardware devices... In the present example, data from a source buffer 722 of memory 720 is compressed by a compress engine 712 of SDXI hardware device 710, stored to an intermediate buffer 724 of the memory, encrypted by an encrypt engine 717 of the SDZI hardware device 715 and returned to a destination buffer 726 of the memory.”; Iyer, col. 11, lines 1-10, Fig. 7)
Fig. 7 illustrates that SDXI 715 (second accelerator) performs encryptions and stores the output (additional data is output data) in a destination buffer 726 in memory (and the second accelerator is to store the output data to a destination memory location in the system memory).
Re: claim 8, Iyer and Paltashev teach
8. (Original) The apparatus of claim 1, wherein the first and second accelerators respectively have first logic having support for an instruction and second logic having support for the instruction, the instruction to specify the chained accelerator operation. (“Fig. 7 illustrates a method for chaining operations with multiple SDXI hardware devices... In the present example, data from a source buffer 722 of memory 720 is compressed by a compress engine 712 of SDXI hardware device 710, stored to an intermediate buffer 724 of the memory, encrypted by an encrypt engine 717 of the SDZI hardware device 715 and returned to a destination buffer 726 of the memory. The chained operations are invoked when a first SDXI command 705 is provided to SDXI hardware device 710 and a second SDXI command 707 is provided to SDXI hardware device 715... SDXI command 707 includes a dependency field that indicates to SDXI hardware device 715 that the operation to be performed on the data from intermediate buffer 724 is dependent upon the prior completion of the operation performed by SDXI hardware device 710.”; Iyer, col. 11, lines 1- 13, lines 32-36, Fig. 7)
Fig. 7 illustrates a first SDXI command (first logic having support for an instruction) 705 second SDXI command 707 (second logic having support for an instruction). The chained operations are invoked (the instruction to specify the chained accelerator operation) when a first SDXI command is provided to SDXI device 710 (first accelerator) and the second SDXI command is provided to SDXI device 715 (second accelerator).
Re: claim 18, Iyer and Paltashev teach
18. (Original) The method of claim 11, wherein said performing the operations with the first accelerator comprises performing operations selected from a group consisting of performing data decompression operations, performing matrix processing operations, performing tensor processing operations, performing artificial intelligence processing operations, performing machine learning processing operations, and performing data analytics processing operations. (“Fig. 7 illustrates a method for chaining operations with multiple SDXI hardware devices... In the present example, data from a source buffer 722 of memory 720 is compressed by a compress engine 712 of SDXI hardware device 710, stored to an intermediate buffer 724 of the memory, encrypted by an encrypt engine 717 of the SDZI hardware device 715 and returned to a destination buffer 726 of the memory. The chained operations are invoked when a first SDXI command 705 is provided to SDXI hardware device 710 and a second SDXI command 707 is provided to SDXI hardware device 715... SDXI command 707 includes a dependency field that indicates to SDXI hardware device 715 that the operation to be performed on the data from intermediate buffer 724 is dependent upon the prior completion of the operation performed by SDXI hardware device 710.”; Iyer, col. 11, lines 1- 13, lines 32-36, Fig. 7)
Fig. 7 illustrates that SDXI 712 (first accelerator) performs compression (performing data compression operations).
Claim(s) 2, 12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer in view of Paltashev as applied to claims 1 and 11 above, and further in view of Golas et al. U.S. Pub. No. 2019/0005703.
Re: claim 2, Iyer and Paltashev are silent regarding one of the first and second accelerators includes a first set of virtual accelerator resources and a second set of virtual accelerator resources, and wherein the first set of virtual accelerator resources but not the second set of virtual accelerator resources is to be controlled as part of the chained accelerator operation, however, Golas teaches
2. (Original) The apparatus of claim 1, wherein one of the first and second accelerators includes a first set of virtual accelerator resources and a second set of virtual accelerator resources, and wherein the first set of virtual accelerator resources but not the second set of virtual accelerator resources is to be controlled as part of the chained accelerator operation. (“While the GPU 102 is described herein as a physical GPU component, it will be appreciated that the GPU 102 can correspond to a virtual GPU.”; Golas, [0044], Fig. 1)
Fig. 1 illustrates a graphics processing system, where the GPU 102 (accelerator) can be a virtual GPU.
(“The scheduling of the processing of the tile read and write operations may be selected to generate an interleaved schedule such that after a tile of image A is produced and stored to on-chip cache memory 160, that tile is “immediately read back” to produce a tile of RT B, thus saving memory bandwidth. It will be appreciated that “immediately read back” (also referred to as “directly consumed” or “consumed immediately”) can include processing intervening operations between the storing of the tile of image A to on-chip cache memory 160 and the reading of the stored tile from the on-chip cache memory to produce a tile of RT B. For example, “immediately read back” can correspond to reading the tile of image A from the on-chip cache memory 160 rather than reading the tile from external memory 120 to produce the tile of RT B.”; Golas, [0058], Fig. 3)
The virtual GPU (virtual accelerator) a dependency chain of operations, performed by the different stages (first and second accelerators), such that after a tile of image A is produced and stored to on-chip cache memory, the tile is consumed immediately to produce a tile of RT B. The virtual GPU uses GPU resources and on-chip memory resources to perform the dependency chain of operations (first set of virtual accelerator resources), rather than reading the tile from external memory (second set of virtual accelerator resources) to produce the tile of RT B. .
(“That is, once a dependency chain of operations is established, the present embodiment enables determination of an improved/near optimal order of operations such that data from one stage is immediately consumed by another stage, thereby achieving an improved optimal locality of reference to enable rendering of tiles followed immediately by the consumption of the data corresponding thereto, without going off chip.”; Golas, [0083])
Once the dependency chain of operation is established, an order of operations is enables such that data from one stage (first accelerator) is immediately consumed by another stage (second accelerator).
(“Further, dependencies may be defined such that a dependency structure is “size-agnostic,” and can therefore operate on pixel blocks of different dimensions without any recompilation of any workload, and without accessing external memory.”; Golas, [0086])
The virtual GPU uses GPU resources and on-chip memory resources to perform the dependency chain of operations, without accessing external memory (and wherein the first set of virtual accelerator resources but not the second set of virtual accelerator resources is to be controlled as part of the chained accelerator operation). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of one of the first and second accelerators includes a first set of virtual accelerator resources and a second set of virtual accelerator resources, and wherein the first set of virtual accelerator resources but not the second set of virtual accelerator resources is to be controlled as part of the chained accelerator operation, in order to save memory bandwidth by consuming intermediate data from the on-chip memory instead of using the external memory, as taught by Golas ([0058]).
Re: claim 12, Iyer and Paltashev are silent regarding performing the operations with the second accelerator includes said performing the operations with a first set of virtual accelerator resources of the second accelerator, but not a second set of virtual accelerator resources of the second accelerator, however, Golas teaches
12. (Original) The method of claim 11, wherein said performing the operations with the second accelerator includes said performing the operations with a first set of virtual accelerator resources of the second accelerator, but not a second set of virtual accelerator resources of the second accelerator. (“While the GPU 102 is described herein as a physical GPU component, it will be appreciated that the GPU 102 can correspond to a virtual GPU.”; Golas, [0044], Fig. 1)
Fig. 1 illustrates a graphics processing system, where the GPU 102 (accelerator) can be a virtual GPU.
(“The scheduling of the processing of the tile read and write operations may be selected to generate an interleaved schedule such that after a tile of image A is produced and stored to on-chip cache memory 160, that tile is “immediately read back” to produce a tile of RT B, thus saving memory bandwidth. It will be appreciated that “immediately read back” (also referred to as “directly consumed” or “consumed immediately”) can include processing intervening operations between the storing of the tile of image A to on-chip cache memory 160 and the reading of the stored tile from the on-chip cache memory to produce a tile of RT B. For example, “immediately read back” can correspond to reading the tile of image A from the on-chip cache memory 160 rather than reading the tile from external memory 120 to produce the tile of RT B.”; Golas, [0058], Fig. 3)
The virtual GPU (virtual accelerator) a dependency chain of operations, performed by the different stages (first and second accelerators), such that after a tile of image A is produced and stored to on-chip cache memory, the tile is consumed immediately to produce a tile of RT B. The virtual GPU uses GPU resources and on-chip memory resources to perform the dependency chain of operations (first set of virtual accelerator resources), rather than reading the tile from external memory (second set of virtual accelerator resources) to produce the tile of RT B. .
(“That is, once a dependency chain of operations is established, the present embodiment enables determination of an improved/near optimal order of operations such that data from one stage is immediately consumed by another stage, thereby achieving an improved optimal locality of reference to enable rendering of tiles followed immediately by the consumption of the data corresponding thereto, without going off chip.”; Golas, [0083])
Once the dependency chain of operation is established, an order of operations is enables such that data from one stage (first accelerator) is immediately consumed by another stage (second accelerator).
(“Further, dependencies may be defined such that a dependency structure is “size-agnostic,” and can therefore operate on pixel blocks of different dimensions without any recompilation of any workload, and without accessing external memory.”; Golas, [0086])
The virtual GPU uses GPU resources and on-chip memory resources to perform the dependency chain of operations, without accessing external memory (and wherein the first set of virtual accelerator resources but not the second set of virtual accelerator resources is to be controlled as part of the chained accelerator operation). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of performing the operations with the second accelerator includes said performing the operations with a first set of virtual accelerator resources of the second accelerator, but not a second set of virtual accelerator resources of the second accelerator, in order to save memory bandwidth by consuming intermediate data from the on-chip memory instead of using the external memory, as taught by Golas ([0058]).
Re: claim 20, Iyer and Paltashev are silent regarding cause the machine to perform the operations with a first set of virtual accelerator resources of the first accelerator, but not a second set of virtual accelerator resources of the first accelerator, however, Golas teaches
(Original) The at least one non-transitory machine-readable storage medium of claim 19, wherein the instructions that, if performed by the machine, are to cause the machine to perform the operations with the first accelerator further comprise instructions that, if performed by the machine, are to cause the machine to perform the operations with a first set of virtual accelerator resources of the first accelerator, but not a second set of virtual accelerator resources of the first accelerator. (“While the GPU 102 is described herein as a physical GPU component, it will be appreciated that the GPU 102 can correspond to a virtual GPU.”; Golas, [0044], Fig. 1)
Fig. 1 illustrates a graphics processing system, where the GPU 102 (accelerator) can be a virtual GPU.
(“The scheduling of the processing of the tile read and write operations may be selected to generate an interleaved schedule such that after a tile of image A is produced and stored to on-chip cache memory 160, that tile is “immediately read back” to produce a tile of RT B, thus saving memory bandwidth. It will be appreciated that “immediately read back” (also referred to as “directly consumed” or “consumed immediately”) can include processing intervening operations between the storing of the tile of image A to on-chip cache memory 160 and the reading of the stored tile from the on-chip cache memory to produce a tile of RT B. For example, “immediately read back” can correspond to reading the tile of image A from the on-chip cache memory 160 rather than reading the tile from external memory 120 to produce the tile of RT B.”; Golas, [0058], Fig. 3)
The virtual GPU (virtual accelerator) a dependency chain of operations, performed by the different stages (first and second accelerators), such that after a tile of image A is produced and stored to on-chip cache memory, the tile is consumed immediately to produce a tile of RT B. The virtual GPU uses GPU resources and on-chip memory resources to perform the dependency chain of operations (first set of virtual accelerator resources), rather than reading the tile from external memory (second set of virtual accelerator resources) to produce the tile of RT B. .
(“That is, once a dependency chain of operations is established, the present embodiment enables determination of an improved/near optimal order of operations such that data from one stage is immediately consumed by another stage, thereby achieving an improved optimal locality of reference to enable rendering of tiles followed immediately by the consumption of the data corresponding thereto, without going off chip.”; Golas, [0083])
Once the dependency chain of operation is established, an order of operations is enables such that data from one stage (first accelerator) is immediately consumed by another stage (second accelerator).
(“Further, dependencies may be defined such that a dependency structure is “size-agnostic,” and can therefore operate on pixel blocks of different dimensions without any recompilation of any workload, and without accessing external memory.”; Golas, [0086])
The virtual GPU uses GPU resources and on-chip memory resources to perform the dependency chain of operations, without accessing external memory (and wherein the first set of virtual accelerator resources but not the second set of virtual accelerator resources is to be controlled as part of the chained accelerator operation). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of cause the machine to perform the operations with a first set of virtual accelerator resources of the first accelerator, but not a second set of virtual accelerator resources of the first accelerator, in order to save memory bandwidth by consuming intermediate data from the on-chip memory instead of using the external memory, as taught by Golas ([0058]).
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer, Paltashev and Golas as applied to claims 2 and 12 above, and further in view of Kutch et al. U.S. Pub. No. 2021/0117360.
Re: claims 3 and 13 (which are rejected under the same rationale), Iyer and Golas are silent regarding the first set of virtual accelerator resources comprises a Scalable Input/Output Virtualization (SIOV) virtual device (VDEV), and wherein the VDEV has an Assignable Device Interface (ADI) to receive an instruction specifying the chained accelerator operation, however, Kutch teaches
3. (Original) The apparatus of claim 2, wherein the first set of virtual accelerator resources comprises a Scalable Input/Output Virtualization (SIOV) virtual device (VDEV), and wherein the VDEV has an Assignable Device Interface (ADI) to receive an instruction specifying the chained accelerator operation. (“OS can call a NEXT driver, which can initialize NEXT and create a virtual session to a guest and guest access to NEXT resources through a virtual interface (e.g., VF or SIOV ADI).”; Kutch, [0090])
The OS creates a virtual session to a guest and guest access to NEXT resources (first set of virtual accelerator resources) through a virtual interface such as an SIOV ADI (scalable input/output virtualization (SIOV).
(“A VDCM can compose SIOV virtual devices (VDEVs). A VDEV driver can provide access to WAT to a VNF or application running in VM, container, etc.”; Kutch, [0098])
The VDCM (virtual device composition module) composes SIOV virtual devices (scalable input/output virtualization (SIOV) virtual device (VDEV).
(“SIOV provides for scalable sharing of I/O devices, such as network controllers, storage controllers, graphics processing units, and other hardware accelerators across a large number of containers or virtual machines.”; Kutch, [0150])
The SIOV provides scalable sharing of I/O devices, such as network controllers, storage controllers and graphics processing units.
(“VDEV can include a virtual device where the PCIe configuration space is emulated in software in the host, while the parts of the device used by the data plane, such as queue pairs used for receipt/transmission of data, can be mapped directly to NEXT. In some examples, NEXT exposes these queue pairs as Assignable Device Interfaces (ADIs).”; Kutch, [0217])
The VDEV includes a virtual device, where parts of the device, such as queue pairs, for receiving data, are assignable device interfaces ADIs) (the VDEV has an assignable device interface (ADI)). Kutch is combined with Iyer such that the queue pairs of Kutch receive the SDXI commands of Iyer. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of the first set of virtual accelerator resources comprises a Scalable Input/Output Virtualization (SIOV) virtual device (VDEV), and wherein the VDEV has an Assignable Device Interface (ADI) to receive an instruction specifying the chained accelerator operation, in order to allow programming of a network interface to provide, for example, packet processing capabilities, as taught by Kutch ([0304]).
Claim(s) 4, 6, 14, 16, 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer and Paltashev as applied to claims 1, 11 and 19 above, and further in view of Appu et al. U.S. Patent No. 10,891,707.
Re: claims 4 and 14 (which are rejected under the same rationale), Iyer and Paltashev are silent regarding one of the first and second accelerators includes a first set of physical accelerator resources and a second set of physical accelerator resources, and wherein the first set of physical accelerator resources but not the second set of physical accelerator resources is to be controlled as part of the chained accelerator operation, however, Appu teaches
4. (Original) The apparatus of claim 1, wherein one of the first and second accelerators includes a first set of physical accelerator resources and a second set of physical accelerator resources, (“The processing cluster array 212 can include up to “N” processing clusters (e.g., cluster 214A-214N)... different clusters 214A-214N of processing cluster array 212 can be allocated for processing different types of programs or for performing different types of computations.”; Appu, col. 6, lines 29-31, lines 42-45, Fig. 2A)
Fig. 2A illustrates processing cluster 212. Different clusters (accelerators) of the processing cluster array perform different types of computations.
(“... portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214A-214N for further processing.”; Appu, col. 7, lines 11-22, Fig. 1-2A)
Fig. 2A illustrates parallel processors that include a processing cluster array 212 that performs pipeline (chained) operations, where the first portion (first accelerator) performs vertex shading, and the second portion (second accelerator) performs tessellation and geometry shading. The first and second portions have resources such as for example, vertex shading, geometry shading, parallel processor memory (a first set of physical accelerator resources and a second set of physical accelerator resources). Fig. 1 illustrates parallel processors 112 with resources such as, for example, system memory, processors 102, display device 110B, memory hub 105. And, Fig. 2A illustrates resources such as parallel processor memory and the processing operations of the clusters, such as vertex and geometry shading.
and wherein the first set of physical accelerator resources but not the second set of physical accelerator resources is to be controlled as part of the chained accelerator operation. (“... portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214A-214N for further processing”; Appu, col. 7, lines 11-22, Fig. 2A)
Fig. 2A illustrates a processing cluster array 212 the performs pipeline operations, where a first portion (first accelerator) performs vertex shading, a second portion (second accelerator) performs tessellation and geometry shading, and a third portion (third accelerator) performs pixel shading. The third portion receives, as input, intermediate data from the second portion. The third portion performs pixel shading for rendering. This pipeline chained operation uses, for example, the processing clusters and the parallel processor memory (first set of physical accelerator resources) but does not use processors 102 (but not the second set of physical accelerator resources is to be controlled as part of the chained accelerator operation). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of one of the first and second accelerators includes a first set of physical accelerator resources and a second set of physical accelerator resources, and wherein the first set of physical accelerator resources but not the second set of physical accelerator resources is to be controlled as part of the chained accelerator operation, in order to allow the partition units to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory, as taught by Appu (col. 8, lines 1-5).
Re: claim 21, Iyer and Paltashev are silent regarding to cause the machine to perform the operations with the second accelerator further comprise instructions that, if performed by the machine, are to cause the machine to perform the operations with a first set of physical accelerator resources of the second accelerator, but not a second set of physical accelerator resources of the second accelerator, however, Appu teaches
21. The at least one non-transitory machine-readable storage medium of claim 19, wherein the instructions that, if performed by the machine, are to cause the machine to perform the operations with the second accelerator further comprise instructions that, if performed by the machine, are to cause the machine to perform the operations with a first set of physical accelerator resources of the second accelerator, but not a second set of physical accelerator resources of the second accelerator. (“The processing cluster array 212 can include up to “N” processing clusters (e.g., cluster 214A-214N)... different clusters 214A-214N of processing cluster array 212 can be allocated for processing different types of programs or for performing different types of computations.”; Appu, col. 6, lines 29-31, lines 42-45, Fig. 2A)
Fig. 2A illustrates processing cluster 212. Different clusters (accelerators) of the processing cluster array perform different types of computations.
(“... portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214A-214N for further processing.”; Appu, col. 7, lines 11-22, Fig. 1-2A)
Fig. 2A illustrates parallel processors that include a processing cluster array 212 that performs pipeline (chained) operations, where the first portion (first accelerator) performs vertex shading, and the second portion (second accelerator) performs tessellation and geometry shading. The second portion has resources such as for example, geometry shading, parallel processor memory (a first set of physical accelerator resources of the second accelerator). Fig. 1 illustrates parallel processors 112 with resources such as, for example, system memory, processors 102, display device 110B, memory hub 105. And, Fig. 2A illustrates resources such as parallel processor memory and the processing operations of the clusters, such as geometry shading.
(“... portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214A-214N for further processing”; Appu, col. 7, lines 11-22, Fig. 2A)
Fig. 2A illustrates a processing cluster array 212 the performs pipeline operations, where a first portion (first accelerator) performs vertex shading, a second portion (second accelerator) performs tessellation and geometry shading, and a third portion (third accelerator) performs pixel shading. The third portion receives, as input, intermediate data from the second portion. The third portion performs pixel shading for rendering. For the second portion (second accelerator), this pipeline chained operation uses, for example, the processing clusters performing geometry shading and the parallel processor memory (first set of physical accelerator resources of the second accelerator) but does not use processors 102 (but not a second set of physical accelerator resources of the second accelerator). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of to cause the machine to perform the operations with the second accelerator further comprise instructions that, if performed by the machine, are to cause the machine to perform the operations with a first set of physical accelerator resources of the second accelerator, but not a second set of physical accelerator resources of the second accelerator, in order to allow the partition units to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory, as taught by Appu (col. 8, lines 1-5).
Re: claims 6 and 16 (which are rejected under the same rationale), Iyer and Paltashev are silent regarding the additional data is second intermediate data, and further comprising a third accelerator having support for the chained accelerator operation, the third accelerator to be controlled as part of the chained accelerator operation to receive the second intermediate data, without the second intermediate data having been sent to the system memory, process the second intermediate data, and generate second additional data, wherein the second additional data is either to be third intermediate data to be processed by zero or more additional accelerators or output data the third accelerator is to store to a destination memory location in the system memory, however, Appu teaches
6. (Original) The apparatus of claim 1, wherein the additional data is second intermediate data, and further comprising a third accelerator having support for the chained accelerator operation, the third accelerator to be controlled as part of the chained accelerator operation to receive the second intermediate data, without the second intermediate data having been sent to the system memory, process the second intermediate data, and generate second additional data, wherein the second additional data is either to be third intermediate data to be processed by zero or more additional accelerators or output data the third accelerator is to store to a destination memory location in the system memory. (“... portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214A-214N for further processing”; Appu, col. 7, lines 11-22, Fig. 2A)
Fig. 2A illustrates a processing cluster array 212 the performs pipeline operations (chained accelerator operations), where a first portion (first accelerator) performs vertex shading, a second portion (second accelerator) performs tessellation and geometry shading, and a third portion (third accelerator) performs pixel shading. The third portion receives, as input, intermediate data (additional data is second intermediate data) from the second portion (the third accelerator to be controlled as part of the chained accelerator operation to receive the second intermediate data, without the second intermediate data having been sent to the system memory). The third portion performs pixel shading for rendering (process the second intermediate data, and generate second additional data).
(“... any one of the clusters 214A-214N of the processing cluster array 212 can process data that will be written to any of the memory units 224A-224N within parallel processor memory 222. The memory crossbar 216 can be configured to transfer the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output.”; Appu, col. 8, lines 10-17)
Any one of the clusters can, for example, process data that will be written to any one of the parallel processor memory units 224A-224N for further processing OR the processed data can be sent to another cluster for further processing (wherein the second additional data is either to be third intermediate data to be processed by zero or more additional accelerators or output data the third accelerator is to store to a destination memory location in the system memory). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of the additional data is second intermediate data, and further comprising a third accelerator having support for the chained accelerator operation, the third accelerator to be controlled as part of the chained accelerator operation to receive the second intermediate data, without the second intermediate data having been sent to the system memory, process the second intermediate data, and generate second additional data, wherein the second additional data is either to be third intermediate data to be processed by zero or more additional accelerators or output data the third accelerator is to store to a destination memory location in the system memory, in order to allow the partition units to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory, as taught by Appu (col. 8, lines 1-5).
Re: claim 22, Iyer and Paltashev are silent regarding the additional data is second intermediate data, and wherein the instructions further comprise instructions that, if performed by the machine, are to cause the machine to perform operations of the chained accelerator operation with a third accelerator, including receiving the second intermediate data, without the second intermediate being sent to the system memory, processing the second intermediate data, and generating second additional data, however, Appu teaches
22. The at least one non-transitory machine-readable storage medium of claim 19, wherein the additional data is second intermediate data, and wherein the instructions further comprise instructions that, if performed by the machine, are to cause the machine to perform operations of the chained accelerator operation with a third accelerator, including receiving the second intermediate data, without the second intermediate being sent to the system memory, processing the second intermediate data, and generating second additional data. (“... portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A-214N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214A-214N for further processing”; Appu, col. 7, lines 11-22, Fig. 2A)
Fig. 2A illustrates a processing cluster array 212 the performs pipeline operations (perform operations of the chained accelerator operation with a third accelerator), where a first portion (first accelerator) performs vertex shading, a second portion (second accelerator) performs tessellation and geometry shading, and a third portion (third accelerator) performs pixel shading. The third portion receives, as input, intermediate data (additional data is second intermediate data) from the second portion (the third accelerator to be controlled as part of the chained accelerator operation to receive the second intermediate data, without the second intermediate data having been sent to the system memory). The third portion performs pixel shading for rendering (processing the second intermediate data, and generate second additional data). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of the additional data is second intermediate data, and wherein the instructions further comprise instructions that, if performed by the machine, are to cause the machine to perform operations of the chained accelerator operation with a third accelerator, including receiving the second intermediate data, without the second intermediate being sent to the system memory, processing the second intermediate data, and generating second additional data, in order to allow the partition units to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory, as taught by Appu (col. 8, lines 1-5).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer, Paltashev and Appu as applied to claim 6 above, and further in view of Kutch.
Re: claim 7 (which are rejected under the same rationale), Iyer and Appu are silent regarding the chained accelerator operation is to implement a Directed Acyclic Graph (DAG) involving at least the first, second, and third accelerators, however, Kutch teaches
7. (Original) The apparatus of claim 6, wherein the chained accelerator operation is to implement a Directed Acyclic Graph (DAG) involving at least the first, second, and third accelerators. (“... a device (e.g., ASIC, FPGA, etc.) node corresponding to each of the UE can be programmed with a policy and one or more CLOSs supported by the UE. A QOS tree can represent multiple hierarchical levels representing various aspects of 5G Wireless Hierarchy from the UE to Front Haul to Mid Haul to Back Haul to UPF to VNF. Each level of the QOS tree can include a leaf which represents UE and make a scheduling decision to pick a winner from that level to move forward to transmission or processing... Processor-executed software may be used to pre-process 5G UPF packets and extract and filter the 5G QOS information that can be used either by a 5G QOS accelerator or a 5G QOS application.”; Kutch, [0285])
A device node, such as an ASIC or FPGA, corresponding to each of the UE (accelerator) is represented in a QOS hierarchical tree (directed acyclic graph). A QOS tree (chained accelerator operation) has multiple hierarchical levels, where each level of the QOS tree includes a leaf representing a UE (directed acyclic graph involving at least the first, second and third accelerators). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer, by adding the feature of the chained accelerator operation is to implement a Directed Acyclic Graph (DAG) involving at least the first, second, and third accelerators, in order to enforce a QOS policy to satisfy the QOS requirements of the wide ranges of class of service (CLOS) associated with the traffic, as taught by Kutch ([0281]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer in view of Paltashev as applied to claims 11 above, and further in view of Kutch.
Claim 17 is a method analogous to the apparatus of claim 7, is similar in scope and is rejected under the same rationale.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer in view of Paltashev as applied to claims 1 and 11 above, and further in view of Kutch.
Re: claim 9, Iyer teaches
9. (Original) The apparatus of claim 1, wherein the first and second accelerators are different types of accelerators, (“... data from a source buffer 722 of memory 720 is compressed by a compress engine 712 of SDXI hardware device 710, stored to an intermediate buffer 724 of the memory, encrypted by an encrypt engine 717 of SDXI hardware device 715 and returned to a destination buffer 726 of the memory.”; Iyer, col. 11, lines 4-11, Fig. 7)
Fig 7 illustrates that the smart data accelerator interfaces (SDXIs) 710 and 715 (first and second accelerators) are different types of accelerators. For example, SDXI 710 performs compression and SDXI 715 performs encryption. Iyer is silent regarding each of the first and second accelerators is selected from a group consisting of a digital signal processors (DSP), a matrix accelerator, a tensor processing unit, an artificial intelligence (AI) accelerator, a data analytics accelerators, a cryptographic accelerator, a data compression and/or decompression accelerator, a storage accelerator, a network processors, an accelerator implemented as a Field Programmable Gate Array (FPGA), and an accelerator implemented as an Application Specific Integrated Circuit (ASIC), however, Kutch teaches
and wherein each of the first and second accelerators is selected from a group consisting of a digital signal processors (DSP), a matrix accelerator, a tensor processing unit, an artificial intelligence (AI) accelerator, a data analytics accelerators, a cryptographic accelerator, a data compression and/or decompression accelerator, a storage accelerator, a network processors, an accelerator implemented as a Field Programmable Gate Array (FPGA), and an accelerator implemented as an Application Specific Integrated Circuit (ASIC). (“”For example, an accelerator among accelerators 4242 can provide compression (DC) capability, cryptography services such as public key encryption (PKE), cipher, hash/authentication capabilities, decryption, or other capabilities or services... For example, accelerator 4242 can include... graphics processing unit... application specific integrated circuits (ASICs), neural network processors (NNPs)... programmable processing elements such as field programmable gate arrays (FGPAs)... Accelerators 4242 can provide multiple neural networks, CPUs, processor cores, general purpose graphics processing units, or graphical processing units can be made available for use by artificial intelligence (AI) or machine learning (ML) models. ”; Kutch, [0313], Fig. 42)
The accelerators (which include first and second accelerators) are selected from for example, accelerators that provide compression capability (data compression and/or decompression accelerator), accelerators that provide cryptography services (cryptographic accelerator), application specific integrated circuits (ASICs), neural network processors (artificial intelligence (AI) accelerator) and field programmable gate arrays (FPGAs). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Iyer by adding the feature of each of the first and second accelerators is selected from a group consisting of a digital signal processors (DSP), a matrix accelerator, a tensor processing unit, an artificial intelligence (AI) accelerator, a data analytics accelerators, a cryptographic accelerator, a data compression and/or decompression accelerator, a storage accelerator, a network processors, an accelerator implemented as a Field Programmable Gate Array (FPGA), and an accelerator implemented as an Application Specific Integrated Circuit (ASIC), in order to allow programming of a network interface to provide, for example, packet processing capabilities, as taught by Kutch ([0304]).
Re: claim 10, Iyer, Paltashev and Kutch teach
10. (Original) The apparatus of claim 9, wherein one of the first and second accelerators is a data compression and/or decompression accelerator. (“Fig. 7 illustrates a method for chaining operations with multiple SDXI hardware devices... In the present example, data from a source buffer 722 of memory 720 is compressed by a compress engine 712 of SDXI hardware device 710, stored to an intermediate buffer 724 of the memory, encrypted by an encrypt engine 717 of the SDZI hardware device 715 and returned to a destination buffer 726 of the memory.”; Iyer, col. 11, lines 1-10, Fig. 7)
Fig. 7 illustrates that SDXI 712 (first accelerator) performs compression (one of the first and second accelerators is a data compression and/or decompression accelerator).
Response to Arguments
Applicant’s arguments, see Amendment/Request for Reconsideration-After Non-Final Rejection, filed 7/08/2026, with respect to the provisional nonstatutory double patenting rejection of claims 1, 2, 4, 11, 12, 14 and 19-22 have been fully considered and are persuasive. The provisional nonstatutory double patenting rejection of the previous Office Action has been withdrawn.
Applicant’s arguments with respect to claim(s) 1, 11 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s arguments, see Amendment/Request for Reconsideration-After Non-Final Rejection, filed 7/08/2026, with respect to the rejection(s) of claim(s) 1, 11 and 19 under 35 U.S.C § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Iyer and Paltashev. Applicant argues:
“As understood by Applicants, Iyer does not disclose these limitations. For example, as understood by Applicants, Iyer does not disclose that "at least one of the first and second accelerators is to identify a bottleneck associated with data flow in the chained accelerator operation and is to make one or more changes to address the bottleneck." Anticipation under 35 U.S.C. §102 requires every element of the claimed invention be identically shown in a single prior art reference. For at least one or more of these reasons, independent claim 1 is believed to be allowable. The dependent claims of claim 1, each include all of the limitations of independent claim 1, and are believed to be allowable for at least this reason, as well as for the recitations separately set forth in each of these dependent claims. Independent claims 11 and 19 are believed to be allowable for one or more similar reasons based on one or more similar limitations as recited therein. The dependent claims of claims 11 and 19 include all of the limitations of their respective independent claims, and are believed to be allowable therefor, as well as for the recitations separately set forth in each of these dependent claims.”
Examiner agrees. A new rejection has been set forth necessitated by the amendment. Paltashev teaches that when a bottleneck is detected (identify... a bottleneck associated with data flow in the chained accelerator operation) in the fixed function hardware blocks (at least one of the first and second accelerators), the shader firmware emulations of the fixed function hardware blocks (at least one of the first and second accelerators) are used to perform the requested operations (make... one or more changes to address the bottleneck) instead of using the actual hardware. (Paltashev, col. 14, line 62-col. 15, line 3),
Applicant's arguments filed 7/08/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 2, 12, and 20 respecfully depend from, and include all the limitations of, independent claims 1, 11, and 19. As discussed above, Iyer not disclose or render obvious the limitations of independent claims 1, 11, and 19. As understood by Applicants, Golas does not remedy all of what is missing from these references and/or the Examiner does not appear to have sufficiently articulated where all these missing limitations are found in Golas. Accordingly, without admitting that these references could or should be combined in the manner proposed, Applicants respectfully submit that independent claims 1, 11, and 19 are believed to be allowable over Iver and Golas. Dependent claims 2, 12, and 20 are believed to be allowable for at least this reason, as well as for the recitations separately set forth in each of these dependent claims.”
Examiner disagrees. Claims 1, 11 and 19 and claims 2, 12 and 20 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 7/08/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 3 and 13 depend from, and include all the limitations of, independent claims 1 and 11. As discussed above, Iver does not disclose or render obvious the limitations of independent claim 1 and 11. As understood by Applicants, Golas and Kutch does not remedy all of what is missing from these references and/or the Examiner does not appear to have sufficiently articulated where all these missing limitations are found in Golas and Kutch. Accordingly, without admitting that these references could or should be combined in the manner proposed, Applicants respectfully submit that independent claim 1 and 11 are believed to be allowable over Iver, Golas and Kutch. Dependent claims 3 and 13 are believed to be allowable for at least this reason, as well as for the recitations separately set forth in each of these dependent claims.”
Examiner disagrees. Claims 1, 11 and 19 and claims 3 and 13 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 7/08/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 4 and 6 depend from, and include all the limitations of, independent claim 1. Claims 14 and 16 depend from, and include all the limitations of, independent claim 11. Claims 21-22 depend from, and include all the limitations of, independent claim 19. As discussed above, Iver does not disclose or render obvious the limitations of independent claim 1, 11, or 19. As understood by Applicants, Appu does not remedy all of what is missing from these references and/or the Examiner does not appear to have sufficiently articulated where all these missing limitations are found in Appu. Accordingly, without admitting that these references could or should be combined in the manner proposed, Applicants respectfully submit that independent claim 1, 11, and 19 is believed to be allowable over Iver and Appu. Dependent claims 4, 6, 14, 16, and 21-22 are believed to be allowable for at least this reason, as well as for the recitations separately set forth in each of these dependent claims.”
Examiner disagrees. Claims 1, 11 and 19 and claims 4, 6, 14, 16, 21 and 22 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 7/08/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claim 7 depends from, and includes all the limitations of, independent claim 1. As discussed above, Iver and Appu do not disclose or render obvious the limitations of independent claim 1. As understood by Applicants, Appu and Kutch do not remedy all of what is missing from these references and/or the Examiner does not appear to have sufficiently articulated where all these missing limitations are found in Appu and Kutch . Accordingly, without admitting that these references could or should be combined in the manner proposed, Applicants respectfully submit that independent claim 1 is believed to be allowable over Iver, Appu and Kutch. Dependent claim 7 is believed to be allowable for at least this reason, as well as for the recitations separately set forth in each of these dependent claims.”
Examiner disagrees. Claims 1 and 7 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 7/08/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claim 17 depends from, and include all the limitations of, independent claim 11. As discussed above, Iver does not disclose or render obvious the limitations of independent claim 11. As understood by Applicants, Kutch does not remedy all of what is missing from these references and/or the Examiner does not appear to have sufficiently articulated where all these missing limitations are found in Kutch. Accordingly, without admitting that these references could or should be combined in the manner proposed, Applicants respectfully submit that independent claim 11 is believed to be allowable over Iyer and Kutch. Dependent claim 17 is believed to be allowable for at least this reason, as well as for the recitations separately set forth in each of these dependent claims.”
Examiner disagrees. Claims 11 and 17 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 7/08/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 9-10 depend from, and include all the limitations of, independent claim 1. As discussed above, Iver does not disclose or render obvious the limitations of independent claim 1. As understood by Applicants, Kutch does not remedy all of what is missing from these references and/or the Examiner does not appear to have sufficiently articulated where all these missing limitations are found in Kutch. Accordingly, without admitting that these references could or should be combined in the manner proposed, Applicants respectfully submit that independent claim 1 is believed to be allowable over Iver and Kutch. Dependent claims 9-10 are believed to be allowable for at least this reason, as well as for the recitations separately set forth in each of these dependent claims.”
Examiner disagrees. Claims 1 and claims 9-10 have been rejected. Please see the corresponding rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONNA J RICKS whose telephone number is (571)270-7532. The examiner can normally be reached on M-F 7:30am-5pm EST (alternate Fridays off).
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/Donna J. Ricks/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618
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